source: firmware/FTM/FTM_top_tb.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 21.7 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08.12.2010
6-- Design Name:
7-- Module Name: FTM_top_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for FTM firmware
12--
13-- VHDL Test Bench Created by ISE for module: FTM_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTM_top_tb is
37end FTM_top_tb;
38
39architecture behavior of FTM_top_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTM_top
44 port(
45
46 -- Clock
47 clk : IN STD_LOGIC; -- external clock from oscillator U47
48
49 -- connection to the WIZnet W5300 ethernet controller
50 -------------------------------------------------------------------------------
51 -- W5300 data bus
52 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
53
54 -- W5300 address bus
55 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
56 -- the W5300 is operated in the
57 -- 16-bit mode
58 -- -> W_A<0> assigned to unconnected pin
59
60 -- W5300 control signals
61 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
62 -- W_CS is also routed to testpoint JP7
63 W_CS : out STD_LOGIC; -- W5300 chip select
64 W_INT : IN STD_LOGIC; -- interrupt
65 W_RD : out STD_LOGIC; -- read
66 W_WR : out STD_LOGIC; -- write
67 W_RES : out STD_LOGIC; -- reset W5300 chip
68
69 -- W5300 buffer ready indicator
70 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
71
72 -- testpoints (T18) associated with the W5300
73 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
74
75
76 -- SPI Interface
77 -- connection to the EEPROM U36 (AL25L016M) and
78 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
79 -------------------------------------------------------------------------------
80 -- S_CLK : out STD_LOGIC; -- SPI clock
81
82 -- EEPROM
83 -- MOSI : out STD_LOGIC; -- master out slave in
84 -- MISO : in STD_LOGIC; -- master in slave out
85 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
86
87 -- temperature sensors U45, U46, U48 and U49
88 -- SIO : inout STD_LOGIC; -- serial IO
89 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
90
91
92 -- Trigger primitives inputs
93 -------------------------------------------------------------------------------
94 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
95 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
96 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
97 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
98
99
100 -- NIM inputs
101 ------------------------------------------------------------------------------
102 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
103 Veto : in STD_LOGIC; -- trigger veto input
104 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
105
106 -- alternative external clock input for FPGA
107 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
108
109
110 -- LEDs
111 -------------------------------------------------------------------------------
112 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
113 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
114 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
115
116
117 -- Clock conditioner LMK03000
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
125
126
127 -- various RS-485 Interfaces
128 -------------------------------------------------------------------------------
129 -- Bus 1: FTU slow control
130 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
131 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
132
133 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
134 Bus1_TxD_0 : out STD_LOGIC;
135
136 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
137 Bus1_TxD_1 : out STD_LOGIC;
138
139 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
140 Bus1_TxD_2 : out STD_LOGIC;
141
142 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
143 Bus1_TxD_3 : out STD_LOGIC;
144
145
146 -- Bus 2: Trigger-ID to FAD boards
147 -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
148 -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
149
150 -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
151 -- Bus2_TxD_0 : out STD_LOGIC;
152
153 -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
154 -- Bus2_TxD_1 : out STD_LOGIC;
155
156 -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
157 -- Bus2_TxD_2 : out STD_LOGIC;
158
159 -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
160 -- Bus2_TxD_3 : out STD_LOGIC;
161
162
163 -- auxiliary access
164 -- Aux_Rx_D : in STD_LOGIC;
165 -- Aux_Tx_D : out STD_LOGIC;
166 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
167 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
168
169
170 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
171 -- TrID_Rx_D : in STD_LOGIC;
172 -- TrID_Tx_D : out STD_LOGIC;
173
174
175 -- Crate-Resets
176 -------------------------------------------------------------------------------
177 -- Crate_Res0 : out STD_LOGIC;
178 -- Crate_Res1 : out STD_LOGIC;
179 -- Crate_Res2 : out STD_LOGIC;
180 -- Crate_Res3 : out STD_LOGIC;
181
182
183 -- Busy signals from the FAD boards
184 -------------------------------------------------------------------------------
185 Busy0 : in STD_LOGIC;
186 Busy1 : in STD_LOGIC;
187 Busy2 : in STD_LOGIC;
188 Busy3 : in STD_LOGIC;
189
190
191 -- NIM outputs
192 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
193 -------------------------------------------------------------------------------
194 -- calibration
195 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
196 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
197 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
198 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
199
200 -- auxiliarry / spare NIM outputs
201 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
202 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
203 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
204 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
205
206
207 -- fast control signal outputs
208 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
209 -------------------------------------------------------------------------------
210-- RES_p : out STD_LOGIC; -- RES+ Reset
211-- RES_n : out STD_LOGIC; -- RES-
212
213 TRG_p : out STD_LOGIC; -- TRG+ Trigger
214 TRG_n : out STD_LOGIC; -- TRG-
215
216 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
217 TIM_Run_n : out STD_LOGIC -- TIM_Run-
218-- TIM_Sel : out STD_LOGIC; -- Time Marker selector
219
220 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
221
222
223 -- LVDS calibration outputs
224 -------------------------------------------------------------------------------
225 -- to connector J13
226 -- for light pulsar in the mirror dish
227-- Cal_0_p : out STD_LOGIC;
228-- Cal_0_n : out STD_LOGIC;
229-- Cal_1_p : out STD_LOGIC;
230-- Cal_1_n : out STD_LOGIC;
231-- Cal_2_p : out STD_LOGIC;
232-- Cal_2_n : out STD_LOGIC;
233-- Cal_3_p : out STD_LOGIC;
234-- Cal_3_n : out STD_LOGIC;
235
236 -- to connector J12
237 -- for light pulsar inside shutter
238-- Cal_4_p : out STD_LOGIC;
239-- Cal_4_n : out STD_LOGIC;
240-- Cal_5_p : out STD_LOGIC;
241-- Cal_5_n : out STD_LOGIC;
242-- Cal_6_p : out STD_LOGIC;
243-- Cal_6_n : out STD_LOGIC;
244-- Cal_7_p : out STD_LOGIC;
245-- Cal_7_n : out STD_LOGIC
246
247
248 -- Testpoints
249 -------------------------------------------------------------------------------
250 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
251 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
252
253 -- Board ID - inputs
254 -- local board-ID "solder programmable"
255 -- all on 'input only' pins
256 -------------------------------------------------------------------------------
257 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
258
259 );
260 end component;
261
262 --Inputs
263 signal clk_sig : STD_LOGIC := '0';
264 signal W_INT_sig : STD_LOGIC := '0';
265 signal W_BRDY_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
266 signal Trig_Prim_A_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
267 signal Trig_Prim_B_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
268 signal Trig_Prim_C_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
269 signal Trig_Prim_D_sig : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
270 signal ext_Trig_sig : STD_LOGIC_VECTOR(2 downto 1) := (others => '0');
271 signal Veto_sig : STD_LOGIC := '0';
272 signal NIM_In_sig : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
273 signal NIM_In3_GCLK_sig : STD_LOGIC := '0';
274 signal LD_Clk_Cond_sig : STD_LOGIC := '1';
275 signal Bus1_RxD_0_sig : STD_LOGIC := '1';
276 signal Bus1_RxD_1_sig : STD_LOGIC := '1';
277 signal Bus1_RxD_2_sig : STD_LOGIC := '1';
278 signal Bus1_RxD_3_sig : STD_LOGIC := '1';
279 signal Bus2_RxD_0_sig : STD_LOGIC := '1';
280 signal Bus2_RxD_1_sig : STD_LOGIC := '1';
281 signal Bus2_RxD_2_sig : STD_LOGIC := '1';
282 signal Bus2_RxD_3_sig : STD_LOGIC := '1';
283 signal Busy0_sig : STD_LOGIC := '0';
284 signal Busy1_sig : STD_LOGIC := '0';
285 signal Busy2_sig : STD_LOGIC := '0';
286 signal Busy3_sig : STD_LOGIC := '0';
287
288 --Input/Output Pins
289 signal W_D_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
290 signal W_T_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
291 signal SIO_sig : STD_LOGIC := '0';
292
293 --Outputs
294 signal W_A_sig : STD_LOGIC_VECTOR(9 downto 0);
295 signal W_CS_sig : STD_LOGIC;
296 signal W_RD_sig : STD_LOGIC;
297 signal W_WR_sig : STD_LOGIC;
298 signal W_RES_sig : STD_LOGIC;
299 signal S_CLK_sig : STD_LOGIC;
300 signal TS_CS_sig : STD_LOGIC_VECTOR(3 downto 0);
301 signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0);
302 signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0);
303 signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0);
304 signal CLK_Clk_Cond_sig : STD_LOGIC;
305 signal LE_Clk_Cond_sig : STD_LOGIC;
306 signal DATA_Clk_Cond_sig : STD_LOGIC;
307 signal SYNC_Clk_Cond_sig : STD_LOGIC;
308 signal Bus1_Tx_En_sig : STD_LOGIC;
309 signal Bus1_Rx_En_sig : STD_LOGIC;
310 signal Bus1_TxD_0_sig : STD_LOGIC;
311 signal Bus1_TxD_1_sig : STD_LOGIC;
312 signal Bus1_TxD_2_sig : STD_LOGIC;
313 signal Bus1_TxD_3_sig : STD_LOGIC;
314 signal Bus2_Tx_En_sig : STD_LOGIC;
315 signal Bus2_Rx_En_sig : STD_LOGIC;
316 signal Bus2_TxD_0_sig : STD_LOGIC;
317 signal Bus2_TxD_1_sig : STD_LOGIC;
318 signal Bus2_TxD_2_sig : STD_LOGIC;
319 signal Bus2_TxD_3_sig : STD_LOGIC;
320 signal Crate_Res0_sig : STD_LOGIC;
321 signal Crate_Res1_sig : STD_LOGIC;
322 signal Crate_Res2_sig : STD_LOGIC;
323 signal Crate_Res3_sig : STD_LOGIC;
324 signal RES_p_sig : STD_LOGIC;
325 signal RES_n_sig : STD_LOGIC;
326 signal TRG_p_sig : STD_LOGIC;
327 signal TRG_n_sig : STD_LOGIC;
328 signal TIM_Run_p_sig : STD_LOGIC;
329 signal TIM_Run_n_sig : STD_LOGIC;
330 signal TIM_Sel_sig : STD_LOGIC;
331 signal Cal_0_p_sig : STD_LOGIC;
332 signal Cal_0_n_sig : STD_LOGIC;
333 signal Cal_1_p_sig : STD_LOGIC;
334 signal Cal_1_n_sig : STD_LOGIC;
335 signal Cal_2_p_sig : STD_LOGIC;
336 signal Cal_2_n_sig : STD_LOGIC;
337 signal Cal_3_p_sig : STD_LOGIC;
338 signal Cal_3_n_sig : STD_LOGIC;
339 signal Cal_4_p_sig : STD_LOGIC;
340 signal Cal_4_n_sig : STD_LOGIC;
341 signal Cal_5_p_sig : STD_LOGIC;
342 signal Cal_5_n_sig : STD_LOGIC;
343 signal Cal_6_p_sig : STD_LOGIC;
344 signal Cal_6_n_sig : STD_LOGIC;
345 signal Cal_7_p_sig : STD_LOGIC;
346 signal Cal_7_n_sig : STD_LOGIC;
347
348 -- Clock period definitions
349 constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47
350 constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate
351
352begin
353
354 -- Instantiate the Unit Under Test (UUT)
355 uut: FTM_top
356 port map(
357 clk => clk_sig,
358 W_D => W_D_sig,
359 W_A => W_A_sig,
360 W_CS => W_CS_sig,
361 W_INT => W_INT_sig,
362 W_RD => W_RD_sig,
363 W_WR => W_WR_sig,
364 W_RES => W_RES_sig,
365-- W_BRDY => W_BRDY_sig,
366-- W_T => W_T_sig,
367-- S_CLK => S_CLK_sig,
368-- SIO => SIO_sig,
369-- TS_CS => TS_CS_sig,
370 Trig_Prim_A => Trig_Prim_A_sig,
371 Trig_Prim_B => Trig_Prim_B_sig,
372 Trig_Prim_C => Trig_Prim_C_sig,
373 Trig_Prim_D => Trig_Prim_D_sig,
374 ext_Trig => ext_Trig_sig,
375 Veto => Veto_sig,
376-- NIM_In => NIM_In_sig,
377-- NIM_In3_GCLK => NIM_In3_GCLK_sig,
378 LED_red => LED_red_sig,
379 LED_ye => LED_ye_sig,
380 LED_gn => LED_gn_sig,
381 CLK_Clk_Cond => CLK_Clk_Cond_sig,
382 LE_Clk_Cond => LE_Clk_Cond_sig,
383 DATA_Clk_Cond => DATA_Clk_Cond_sig,
384 SYNC_Clk_Cond => SYNC_Clk_Cond_sig,
385 LD_Clk_Cond => LD_Clk_Cond_sig,
386 Bus1_Tx_En => Bus1_Tx_En_sig,
387 Bus1_Rx_En => Bus1_Rx_En_sig,
388 Bus1_RxD_0 => Bus1_RxD_0_sig,
389 Bus1_TxD_0 => Bus1_TxD_0_sig,
390 Bus1_RxD_1 => Bus1_RxD_1_sig,
391 Bus1_TxD_1 => Bus1_TxD_1_sig,
392 Bus1_RxD_2 => Bus1_RxD_2_sig,
393 Bus1_TxD_2 => Bus1_TxD_2_sig,
394 Bus1_RxD_3 => Bus1_RxD_3_sig,
395 Bus1_TxD_3 => Bus1_TxD_3_sig,
396-- Bus2_Tx_En => Bus2_Tx_En_sig,
397-- Bus2_Rx_En => Bus2_Rx_En_sig,
398-- Bus2_RxD_0 => Bus2_RxD_0_sig,
399-- Bus2_TxD_0 => Bus2_TxD_0_sig,
400-- Bus2_RxD_1 => Bus2_RxD_1_sig,
401-- Bus2_TxD_1 => Bus2_TxD_1_sig,
402-- Bus2_RxD_2 => Bus2_RxD_2_sig,
403-- Bus2_TxD_2 => Bus2_TxD_2_sig,
404-- Bus2_RxD_3 => Bus2_RxD_3_sig,
405-- Bus2_TxD_3 => Bus2_TxD_3_sig,
406-- Crate_Res0 => Crate_Res0_sig,
407-- Crate_Res1 => Crate_Res1_sig,
408-- Crate_Res2 => Crate_Res2_sig,
409-- Crate_Res3 => Crate_Res3_sig,
410 Busy0 => Busy0_sig,
411 Busy1 => Busy1_sig,
412 Busy2 => Busy2_sig,
413 Busy3 => Busy3_sig,
414-- RES_p => RES_p_sig,
415-- RES_n => RES_n_sig,
416 TRG_p => TRG_p_sig,
417 TRG_n => TRG_n_sig,
418 TIM_Run_p => TIM_Run_p_sig,
419 TIM_Run_n => TIM_Run_n_sig
420-- TIM_Sel => TIM_Sel_sig,
421-- Cal_0_p => Cal_0_p_sig,
422-- Cal_0_n => Cal_0_n_sig,
423-- Cal_1_p => Cal_1_p_sig,
424-- Cal_1_n => Cal_1_n_sig,
425-- Cal_2_p => Cal_2_p_sig,
426-- Cal_2_n => Cal_2_n_sig,
427-- Cal_3_p => Cal_3_p_sig,
428-- Cal_3_n => Cal_3_n_sig,
429-- Cal_4_p => Cal_4_p_sig,
430-- Cal_4_n => Cal_4_n_sig,
431-- Cal_5_p => Cal_5_p_sig,
432-- Cal_5_n => Cal_5_n_sig,
433-- Cal_6_p => Cal_6_p_sig,
434-- Cal_6_n => Cal_6_n_sig,
435-- Cal_7_p => Cal_7_p_sig,
436-- Cal_7_n => Cal_7_n_sig
437 );
438
439 -- Stimulus process for clock
440 clk_proc: process
441 begin
442 clk_sig <= '0';
443 wait for clk_period/2;
444 clk_sig <= '1';
445 wait for clk_period/2;
446 end process clk_proc;
447
448 -- Stimulus process for busy signals
449 busy_proc: process
450 begin
451 wait for 500us;
452 Busy0_sig <= '1';
453 wait for 100us;
454 Busy0_sig <= '0';
455 wait for 1ms;
456 Busy0_sig <= '1';
457 wait for 500us;
458 Busy0_sig <= '0';
459 wait;
460 end process busy_proc;
461
462 -- Stimulus process for trigger
463 trigger_proc: process
464 begin
465 ---------------------------------------------------------------------------
466 -- FTUs not yet initialized
467 ---------------------------------------------------------------------------
468 wait for 10us;
469 Trig_Prim_A_sig(0) <= '1';
470 wait for 100ns;
471 Trig_Prim_A_sig(0) <= '0';
472 wait for 99us;
473 Trig_Prim_B_sig(0) <= '1';
474 wait for 100ns;
475 Trig_Prim_B_sig(0) <= '0';
476 wait for 1us;
477 Trig_Prim_B_sig(0) <= '1';
478 wait for 100ns;
479 Trig_Prim_B_sig(0) <= '0';
480 ---------------------------------------------------------------------------
481 -- now FTUs are initialized
482 ---------------------------------------------------------------------------
483 wait for 2200us;
484 Trig_Prim_A_sig(0) <= '1';
485 Trig_Prim_B_sig(0) <= '1';
486 wait for 100ns;
487 Trig_Prim_A_sig(0) <= '0';
488 Trig_Prim_B_sig(0) <= '0';
489 wait for 4us;
490 Trig_Prim_A_sig(0) <= '1';
491 wait for 100ns;
492 Trig_Prim_A_sig(0) <= '0';
493 wait for 22us;
494 Trig_Prim_B_sig(0) <= '1';
495 wait for 100ns;
496 Trig_Prim_B_sig(0) <= '0';
497 wait;
498 end process trigger_proc;
499
500 -- Stimulus process for RS485 of crate 0
501 rs485_0_proc: process
502
503 procedure assign_rs485_0 (data: std_logic_vector(7 downto 0)) is
504 begin
505 Bus1_RxD_0_sig <= '0'; --start bit
506 wait for baud_rate_period;
507 Bus1_RxD_0_sig <= data(0); --bit 0
508 wait for baud_rate_period;
509 Bus1_RxD_0_sig <= data(1); --bit 1
510 wait for baud_rate_period;
511 Bus1_RxD_0_sig <= data(2); --bit 2
512 wait for baud_rate_period;
513 Bus1_RxD_0_sig <= data(3); --bit 3
514 wait for baud_rate_period;
515 Bus1_RxD_0_sig <= data(4); --bit 4
516 wait for baud_rate_period;
517 Bus1_RxD_0_sig <= data(5); --bit 5
518 wait for baud_rate_period;
519 Bus1_RxD_0_sig <= data(6); --bit 6
520 wait for baud_rate_period;
521 Bus1_RxD_0_sig <= data(7); --bit 7
522 wait for baud_rate_period;
523 Bus1_RxD_0_sig <= '1'; --stop bit
524 wait for baud_rate_period;
525 Bus1_RxD_0_sig <= '1'; --stop bit
526 wait for baud_rate_period;
527 end assign_rs485_0;
528
529 begin
530 ---------------------------------------------------------------------------
531 -- time of FTU answer
532 ---------------------------------------------------------------------------
533 wait for 2ms;
534 ---------------------------------------------------------------------------
535 -- data package of FTU answer (28 byte)
536 ---------------------------------------------------------------------------
537 assign_rs485_0(X"40"); --start delimiter
538 wait for 0us;
539 assign_rs485_0(X"C0"); --FTM address
540 wait for 0ns;
541 assign_rs485_0(X"00"); --FTU address
542 wait for 0ns;
543 assign_rs485_0(X"01"); --FTM firmware ID
544 wait for 0ns;
545 assign_rs485_0(X"05"); --instruction
546 wait for 0us;
547 assign_rs485_0(X"00"); --data byte 01
548 wait for 0ns;
549 assign_rs485_0(X"00"); --data byte 02
550 wait for 0ns;
551 assign_rs485_0(X"00"); --data byte 03
552 wait for 0ns;
553 assign_rs485_0(X"00"); --data byte 04
554 wait for 0ns;
555 assign_rs485_0(X"00"); --data byte 05
556 wait for 0ns;
557 assign_rs485_0(X"00"); --data byte 06
558 wait for 0ns;
559 assign_rs485_0(X"00"); --data byte 07
560 wait for 0ns;
561 assign_rs485_0(X"00"); --data byte 08
562 wait for 0ns;
563 assign_rs485_0(X"00"); --data byte 09
564 wait for 0ns;
565 assign_rs485_0(X"00"); --data byte 10
566 wait for 0ns;
567 assign_rs485_0(X"00"); --data byte 11
568 wait for 0ns;
569 assign_rs485_0(X"00"); --data byte 12
570 wait for 0ns;
571 assign_rs485_0(X"00"); --data byte 13
572 wait for 0ns;
573 assign_rs485_0(X"00"); --data byte 14
574 wait for 0ns;
575 assign_rs485_0(X"00"); --data byte 15
576 wait for 0ns;
577 assign_rs485_0(X"00"); --data byte 16
578 wait for 0ns;
579 assign_rs485_0(X"00"); --data byte 17
580 wait for 0ns;
581 assign_rs485_0(X"00"); --data byte 18
582 wait for 0ns;
583 assign_rs485_0(X"00"); --data byte 19
584 wait for 0ns;
585 assign_rs485_0(X"00"); --data byte 20
586 wait for 0ns;
587 assign_rs485_0(X"00"); --data byte 21
588 wait for 0ns;
589 assign_rs485_0(X"00"); --CRC error counter (not used)
590 wait for 0ns;
591 --assign_rs485_0(X"9E"); --check sum for rates
592 assign_rs485_0(X"A5"); --check sum for ping
593 ---------------------------------------------------------------------------
594 -- don't forget final wait!
595 ---------------------------------------------------------------------------
596 wait;
597
598 end process rs485_0_proc;
599
600end;
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