source: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd@ 10942

Last change on this file since 10942 was 10879, checked in by weitzel, 14 years ago
FTM: new light pulser interface, new timing constraint in .ucf file
File size: 8.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 24 February 2010
6-- Design Name:
7-- Module Name: FTM Lightpulser interface Basic
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Interface to the lightpulsers LP1 (in the mirror dish)
12-- and LP2 (inside the shutter)
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20--
21-- modifications: May 13 2011
22--
23-- Version 2
24--
25--
26-- modified: May 26 2011
27-- by Patrick Vogler
28-- "Lightpulser Basic Version"
29--
30-- modified: May 27 2011
31-- by Patrick Vogler, Quirin Weitzel
32-- -> clean up
33--
34----------------------------------------------------------------------------------
35
36library IEEE;
37use IEEE.STD_LOGIC_1164.ALL;
38use IEEE.STD_LOGIC_ARITH.ALL;
39use IEEE.STD_LOGIC_UNSIGNED.ALL;
40
41---- Uncomment the following library declaration if instantiating
42---- any Xilinx primitives in this code.
43library UNISIM;
44use UNISIM.VComponents.all;
45
46library ftm_definitions;
47USE ftm_definitions.ftm_array_types.all;
48USE ftm_definitions.ftm_constants.all;
49
50
51entity Lightpulser_interface_Basic is
52 port(
53
54-- Clock
55-------------------------------------------------------------------------------
56 clk_50 : IN STD_LOGIC; -- 50 MHz system clock
57-- clk_250 : IN STD_LOGIC; -- 250 MHz system clock
58
59-- Lightpulser
60-- RJ-45 connectors J13 or J12 on the FTM board
61-- LVDS calibration outputs
62-- on IO-Bank 0
63-------------------------------------------------------------------------------
64-- connector J13 => Light Pulser 1 in the mirror dish
65 Cal_0_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation
66 Cal_0_n : out STD_LOGIC := '1';
67 Cal_1_p : out STD_LOGIC := '0'; -- Pulse
68 Cal_1_n : out STD_LOGIC := '1';
69 Cal_2_p : out STD_LOGIC := '0'; -- Gate_1_4_7
70 Cal_2_n : out STD_LOGIC := '1';
71 Cal_3_p : out STD_LOGIC := '0'; -- Gate_3_5_8
72 Cal_3_n : out STD_LOGIC := '1';
73
74-- connector J12 => Light Pulser 2 in the shutter
75 Cal_4_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation
76 Cal_4_n : out STD_LOGIC := '1';
77 Cal_5_p : out STD_LOGIC := '0'; -- Pulse
78 Cal_5_n : out STD_LOGIC := '1';
79 Cal_6_p : out STD_LOGIC := '0'; -- Gate_1_4_7
80 Cal_6_n : out STD_LOGIC := '1';
81 Cal_7_p : out STD_LOGIC := '0'; -- Gate_3_5_8
82 Cal_7_n : out STD_LOGIC := '1';
83
84
85-- FPGA intern signals: Lightpulser brightness
86-------------------------------------------------------------------------------
87
88 LP1_ampl : in std_logic_vector (15 downto 0);
89 LP2_ampl : in std_logic_vector (15 downto 0);
90
91-- LP1_delay : in std_logic_vector (15 downto 0);
92-- LP2_delay : in std_logic_vector (15 downto 0);
93
94
95 LP1_pulse : in std_logic; -- trigger lightpulse in the mirror dish
96 LP2_pulse : in std_logic; -- trigger lightpulse in the shutter
97
98
99 start_config : in std_logic; -- handshaking
100 config_started : out std_logic := '0';
101 config_done : out std_logic := '0'
102
103 );
104end Lightpulser_interface_Basic;
105
106
107architecture Behavioral of Lightpulser_interface_Basic is
108
109
110component FM_pulse_generator_Basic is
111 port(
112 clk : in std_logic; -- 50 MHz
113 pulse_freq : in std_logic_vector (5 downto 0);
114 FM_out : out std_logic := '0'
115 );
116end component;
117
118
119component single_LP_Basic is
120 port(
121 clk_50 : in STD_LOGIC;
122 LP_Pulse_out : out STD_LOGIC;
123 LP_pulse_in : in std_logic
124 );
125end component;
126
127
128-- LP1: mirror dish
129signal Cal_0_1 : STD_LOGIC := '0';
130-- signal Cal_1_1 : STD_LOGIC;
131
132-- LP2: shutter
133signal Cal_0_2 : STD_LOGIC := '0';
134-- signal Cal_1_2 : STD_LOGIC;
135
136-- PWM for amplitude stabilization
137signal PWM_sig_1 : std_logic := '0'; -- LP1: mirror dish
138signal PWM_sig_2 : std_logic := '0'; -- LP2: shutter
139
140-- control data latch
141signal LP1_ampl_sig : std_logic_vector (15 downto 0) := (others => '0');
142signal LP2_ampl_sig : std_logic_vector (15 downto 0) := (others => '0');
143
144
145type type_latch_state is (IDLE, COPY, CONFIGURED);
146signal latch_state : type_latch_state := IDLE;
147
148
149begin
150
151
152 -- input latch
153 input_latch : process (clk_50)
154 begin
155 if rising_edge(clk_50) then
156 case latch_state is
157
158 when IDLE =>
159 if start_config = '1' then
160 config_done <= '0';
161 config_started <= '1';
162 latch_state <= COPY;
163 end if;
164
165 when COPY =>
166 LP1_ampl_sig <= LP1_ampl;
167 LP2_ampl_sig <= LP2_ampl;
168 -- LP1_delay_sig <= LP1_delay;
169 -- LP2_delay_sig <= LP2_delay;
170 latch_state <= CONFIGURED;
171
172 when CONFIGURED =>
173 config_started <= '0';
174 config_done <= '1';
175 latch_state <= IDLE;
176
177 end case;
178 end if;
179 end process input_latch;
180
181
182 Inst_LP1_mirror_dish:single_LP_Basic
183 port map (
184 clk_50 => clk_50,
185 LP_Pulse_out => Cal_0_1,
186 LP_pulse_in => LP1_pulse
187 );
188
189
190 Inst_LP2_shutter:single_LP_Basic
191 port map (
192 clk_50 => clk_50,
193 LP_Pulse_out => Cal_0_2,
194 LP_pulse_in => LP2_pulse
195 );
196
197 Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic -- LP1: mirror dish
198 port map(
199 clk => clk_50,
200 pulse_freq => LP1_ampl_sig(5 downto 0),
201 FM_out => PWM_sig_1
202 );
203
204
205 Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic -- LP2: shutter
206 port map(
207 clk => clk_50,
208 pulse_freq => LP2_ampl_sig(5 downto 0),
209 FM_out => PWM_sig_2
210 );
211
212
213 -- Light Pulser 1 (in the mirror dish): differential output buffers
214
215 OBUFDS_inst_Cal_0 : OBUFDS
216 generic map (
217 IOSTANDARD => "DEFAULT")
218 port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port)
219 OB => Cal_0_n , -- Diff_n output (connect directly to top-level port)
220 I => Cal_0_1 -- Buffer input
221 );
222
223 OBUFDS_inst_Cal_1 : OBUFDS
224 generic map (
225 IOSTANDARD => "DEFAULT")
226 port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port)
227 OB => Cal_1_n , -- Diff_n output (connect directly to top-level port)
228 I => PWM_sig_1 -- Buffer input
229 );
230
231 OBUFDS_inst_Cal_2 : OBUFDS
232 generic map (
233 IOSTANDARD => "DEFAULT")
234 port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port)
235 OB => Cal_2_n , -- Diff_n output (connect directly to top-level port)
236 I => LP1_ampl_sig(14) -- Buffer input
237 );
238
239 OBUFDS_inst_Cal_3 : OBUFDS
240 generic map (
241 IOSTANDARD => "DEFAULT")
242 port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port)
243 OB => Cal_3_n , -- Diff_n output (connect directly to top-level port)
244 I => LP1_ampl_sig(15) -- Buffer input
245 );
246
247
248
249 -- Light Pulser 2 (in the shutter): differential output buffers
250
251 OBUFDS_inst_Cal_4 : OBUFDS
252 generic map (
253 IOSTANDARD => "DEFAULT")
254 port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port)
255 OB => Cal_4_n , -- Diff_n output (connect directly to top-level port)
256 I => Cal_0_2 -- Buffer input
257 );
258
259 OBUFDS_inst_Cal_5 : OBUFDS
260 generic map (
261 IOSTANDARD => "DEFAULT")
262 port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port)
263 OB => Cal_5_n , -- Diff_n output (connect directly to top-level port)
264 I => PWM_sig_2 -- Buffer input
265 );
266
267 OBUFDS_inst_Cal_6 : OBUFDS
268 generic map (
269 IOSTANDARD => "DEFAULT")
270 port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port)
271 OB => Cal_6_n , -- Diff_n output (connect directly to top-level port)
272 I => LP2_ampl_sig(14)
273 );
274
275 OBUFDS_inst_Cal_7 : OBUFDS
276 generic map (
277 IOSTANDARD => "DEFAULT")
278 port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port)
279 OB => Cal_7_n , -- Diff_n output (connect directly to top-level port)
280 I => LP2_ampl_sig(15) -- Buffer input
281 );
282
283
284end Behavioral;
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