1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: ETH Zurich, Institute for Particle Physics |
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3 | -- Engineer: Patrick Vogler |
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4 | -- |
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5 | -- Create Date: 24 February 2010 |
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6 | -- Design Name: |
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7 | -- Module Name: FTM Lightpulser interface |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: Interface to the lightpulsers LP1 (in the mirror dish) |
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12 | -- and LP2 (inside the shutter) |
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13 | -- |
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14 | -- Dependencies: |
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15 | -- |
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16 | -- Revision: |
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17 | -- Revision 0.01 - File Created |
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18 | -- Additional Comments: |
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19 | -- |
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20 | -- |
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21 | -- modifications: May 13 2011 |
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22 | -- |
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23 | -- Version 2 |
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24 | -- |
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25 | -- |
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26 | -- modified: May 26 2011 |
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27 | -- by Patrick Vogler |
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28 | -- "Lightpulser Basic Version" |
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29 | -- |
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30 | ---------------------------------------------------------------------------------- |
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31 | |
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32 | library IEEE; |
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33 | use IEEE.STD_LOGIC_1164.ALL; |
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34 | use IEEE.STD_LOGIC_ARITH.ALL; |
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35 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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36 | |
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37 | ---- Uncomment the following library declaration if instantiating |
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38 | ---- any Xilinx primitives in this code. |
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39 | library UNISIM; |
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40 | use UNISIM.VComponents.all; |
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41 | |
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42 | library ftm_definitions; |
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43 | USE ftm_definitions.ftm_array_types.all; |
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44 | USE ftm_definitions.ftm_constants.all; |
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45 | |
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46 | |
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47 | |
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48 | entity Lightpulser_interface is |
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49 | port( |
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50 | |
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51 | -- Clock |
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52 | ------------------------------------------------------------------------------- |
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53 | clk_50 : IN STD_LOGIC; -- 50 MHz system clock |
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54 | -- clk_250 : IN STD_LOGIC; -- 250 MHz system clock |
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55 | |
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56 | -- Lightpulser |
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57 | -- RJ-45 connectors J13 or J12 on the FTM board |
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58 | -- LVDS calibration outputs |
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59 | -- on IO-Bank 0 |
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60 | ------------------------------------------------------------------------------- |
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61 | -- connector J13 => Light Pulser 1 in the mirror dish |
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62 | Cal_0_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation |
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63 | Cal_0_n : out STD_LOGIC := '1'; |
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64 | Cal_1_p : out STD_LOGIC := '0'; -- Pulse |
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65 | Cal_1_n : out STD_LOGIC := '1'; |
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66 | Cal_2_p : out STD_LOGIC := '0'; -- Gate_1_4_7 |
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67 | Cal_2_n : out STD_LOGIC := '1'; |
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68 | Cal_3_p : out STD_LOGIC := '0'; -- Gate_3_5_8 |
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69 | Cal_3_n : out STD_LOGIC := '1'; |
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70 | |
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71 | -- connector J12 => Light Pulser 2 in the shutter |
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72 | Cal_4_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation |
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73 | Cal_4_n : out STD_LOGIC := '1'; |
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74 | Cal_5_p : out STD_LOGIC := '0'; -- Pulse |
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75 | Cal_5_n : out STD_LOGIC := '1'; |
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76 | Cal_6_p : out STD_LOGIC := '0'; -- Gate_1_4_7 |
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77 | Cal_6_n : out STD_LOGIC := '1'; |
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78 | Cal_7_p : out STD_LOGIC := '0'; -- Gate_3_5_8 |
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79 | Cal_7_n : out STD_LOGIC := '1'; |
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80 | |
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81 | |
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82 | -- FPGA intern signals: Lightpulser brightness |
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83 | ------------------------------------------------------------------------------- |
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84 | |
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85 | LP1_ampl : in std_logic_vector (15 downto 0); |
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86 | LP2_ampl : in std_logic_vector (15 downto 0); |
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87 | |
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88 | -- LP1_delay : in std_logic_vector (15 downto 0); |
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89 | -- LP2_delay : in std_logic_vector (15 downto 0); |
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90 | |
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91 | |
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92 | LP1_pulse : in std_logic; -- trigger lightpulse in the mirror dish |
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93 | LP2_pulse : in std_logic; -- trigger lightpulse in the shutter |
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94 | |
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95 | |
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96 | start_config : in std_logic; -- handshaking |
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97 | config_started : out std_logic := '0'; |
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98 | config_done : out std_logic := '0' |
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99 | |
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100 | ); |
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101 | end Lightpulser_interface; |
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102 | |
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103 | |
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104 | architecture Behavioral of Lightpulser_interface is |
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105 | |
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106 | |
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107 | |
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108 | component FM_pulse_generator_Basic is |
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109 | port( |
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110 | clk : in std_logic; -- 50 MHz |
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111 | pulse_freq : in std_logic_vector (5 downto 0); |
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112 | FM_out : out std_logic := '0' |
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113 | ); |
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114 | end component; |
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115 | |
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116 | |
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117 | component single_LP_Basic is |
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118 | port( |
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119 | clk_50 : in STD_LOGIC; |
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120 | LP_Pulse_out : out STD_LOGIC; |
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121 | LP_pulse_in : in std_logic |
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122 | ); |
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123 | end component; |
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124 | |
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125 | |
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126 | |
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127 | |
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128 | -- LP1: mirror dish |
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129 | signal Cal_0_1 : STD_LOGIC := '0'; |
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130 | -- signal Cal_1_1 : STD_LOGIC; |
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131 | |
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132 | -- LP2: shutter |
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133 | signal Cal_0_2 : STD_LOGIC := '0'; |
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134 | -- signal Cal_1_2 : STD_LOGIC; |
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135 | |
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136 | -- PWM for amplitude stabilization |
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137 | signal PWM_sig_1 : std_logic := '0'; -- LP1: mirror dish |
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138 | signal PWM_sig_2 : std_logic := '0'; -- LP2: shutter |
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139 | |
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140 | -- control data latch |
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141 | signal LP1_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); |
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142 | signal LP2_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); |
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143 | |
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144 | |
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145 | type type_latch_state is (IDLE, COPY, CONFIGURED); |
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146 | signal latch_state : type_latch_state := IDLE; |
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147 | |
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148 | |
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149 | |
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150 | |
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151 | |
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152 | begin |
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153 | |
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154 | |
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155 | -- input latch |
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156 | input_latch : process (clk_50) |
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157 | begin |
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158 | if rising_edge(clk_50) then |
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159 | case latch_state is |
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160 | |
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161 | when IDLE => |
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162 | if start_config = '1' then |
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163 | config_done <= '0'; |
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164 | config_started <= '1'; |
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165 | latch_state <= COPY; |
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166 | end if; |
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167 | |
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168 | when COPY => |
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169 | LP1_ampl_sig <= LP1_ampl; |
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170 | LP2_ampl_sig <= LP2_ampl; |
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171 | -- LP1_delay_sig <= LP1_delay; |
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172 | -- LP2_delay_sig <= LP2_delay; |
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173 | latch_state <= CONFIGURED; |
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174 | |
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175 | when CONFIGURED => |
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176 | config_started <= '0'; |
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177 | config_done <= '1'; |
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178 | latch_state <= IDLE; |
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179 | |
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180 | end case; |
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181 | end if; |
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182 | end process input_latch; |
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183 | |
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184 | |
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185 | |
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186 | Inst_LP1_mirror_dish:single_LP_Basic |
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187 | port map ( |
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188 | clk_50 => clk_50, |
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189 | LP_Pulse_out => Cal_0_1, |
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190 | LP_pulse_in => LP1_pulse |
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191 | ); |
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192 | |
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193 | |
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194 | Inst_LP2_shutter:single_LP_Basic |
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195 | port map ( |
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196 | clk_50 => clk_50, |
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197 | LP_Pulse_out => Cal_0_2, |
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198 | LP_pulse_in => LP2_pulse |
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199 | ); |
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200 | |
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201 | Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic -- LP1: mirror dish |
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202 | port map( |
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203 | clk => clk_50, |
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204 | pulse_freq => LP1_ampl_sig(5 downto 0), |
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205 | FM_out => PWM_sig_1 |
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206 | ); |
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207 | |
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208 | |
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209 | Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic -- LP2: shutter |
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210 | port map( |
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211 | clk => clk_50, |
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212 | pulse_freq => LP2_ampl_sig(5 downto 0), |
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213 | FM_out => PWM_sig_2 |
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214 | ); |
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215 | |
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216 | |
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217 | -- Light Pulser 1 (in the mirror dish): differential output buffers |
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218 | |
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219 | OBUFDS_inst_Cal_0 : OBUFDS |
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220 | generic map ( |
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221 | IOSTANDARD => "DEFAULT") |
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222 | port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) |
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223 | OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) |
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224 | I => Cal_0_1 -- Buffer input |
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225 | ); |
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226 | |
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227 | OBUFDS_inst_Cal_1 : OBUFDS |
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228 | generic map ( |
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229 | IOSTANDARD => "DEFAULT") |
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230 | port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) |
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231 | OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) |
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232 | I => PWM_sig_1 -- Buffer input |
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233 | ); |
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234 | |
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235 | OBUFDS_inst_Cal_2 : OBUFDS |
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236 | generic map ( |
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237 | IOSTANDARD => "DEFAULT") |
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238 | port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) |
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239 | OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) |
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240 | I => LP1_ampl_sig(14) -- Buffer input |
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241 | ); |
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242 | |
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243 | OBUFDS_inst_Cal_3 : OBUFDS |
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244 | generic map ( |
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245 | IOSTANDARD => "DEFAULT") |
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246 | port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) |
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247 | OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) |
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248 | I => LP1_ampl_sig(15) -- Buffer input |
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249 | ); |
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250 | |
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251 | |
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252 | |
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253 | -- Light Pulser 2 (in the shutter): differential output buffers |
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254 | |
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255 | OBUFDS_inst_Cal_4 : OBUFDS |
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256 | generic map ( |
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257 | IOSTANDARD => "DEFAULT") |
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258 | port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) |
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259 | OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) |
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260 | I => Cal_0_2 -- Buffer input |
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261 | ); |
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262 | |
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263 | OBUFDS_inst_Cal_5 : OBUFDS |
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264 | generic map ( |
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265 | IOSTANDARD => "DEFAULT") |
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266 | port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) |
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267 | OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) |
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268 | I => PWM_sig_2 -- Buffer input |
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269 | ); |
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270 | |
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271 | OBUFDS_inst_Cal_6 : OBUFDS |
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272 | generic map ( |
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273 | IOSTANDARD => "DEFAULT") |
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274 | port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) |
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275 | OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) |
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276 | I => LP2_ampl_sig(14) |
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277 | ); |
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278 | |
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279 | OBUFDS_inst_Cal_7 : OBUFDS |
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280 | generic map ( |
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281 | IOSTANDARD => "DEFAULT") |
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282 | port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) |
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283 | OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) |
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284 | I => LP2_ampl_sig(15) -- Buffer input |
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285 | ); |
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286 | |
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287 | |
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288 | end Behavioral; |
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289 | |
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290 | |
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