source: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basci_tb.vhd@ 14788

--------------------------------------------------------------------------------
-- Company:       IPP
-- Engineer:      Patrick Vogler
--
-- Create Date:   10:45:29 05/27/2011
-- Design Name:   
-- Module Name:   /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//single_LP_Basci_tb.vhd
-- Project Name:  Lightpulser_Basic
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: single_LP_Basic
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY single_LP_Basci_tb IS
END single_LP_Basci_tb;
 
ARCHITECTURE behavior OF single_LP_Basci_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT single_LP_Basic
    PORT(
         clk_50 : IN  std_logic;
         LP_Pulse_out : OUT  std_logic;
         LP_pulse_in : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_50 : std_logic := '0';
   signal LP_pulse_in : std_logic := '0';

        --Outputs
   signal LP_Pulse_out : std_logic;

   -- Clock period definitions
   constant clk_50_period : time := 20 ns;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: single_LP_Basic PORT MAP (
          clk_50 => clk_50,
          LP_Pulse_out => LP_Pulse_out,
          LP_pulse_in => LP_pulse_in
        );

   -- Clock process definitions
   clk_50_process :process
   begin
                clk_50 <= '0';
                wait for clk_50_period/2;
                clk_50 <= '1';
                wait for clk_50_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin                
      -- hold reset state for 100 ms.
 --     wait for 100 ms;        

      wait for clk_50_period*10;

      -- insert stimulus here 

      LP_pulse_in <= '0';               -- init input
      wait for clk_50_period*10;
      
      LP_pulse_in <= '1';               -- short 20ns pulse
      wait for clk_50_period*1;      
      LP_pulse_in <= '0';
      wait for clk_50_period*10;



      LP_pulse_in <= '1';               -- 60ns pulse
      wait for clk_50_period*3;      
      LP_pulse_in <= '0';
      wait for clk_50_period*10;



      LP_pulse_in <= '1';               -- long 200ns pulse
      wait for clk_50_period*10;      
      LP_pulse_in <= '0';
      wait for clk_50_period*10;





      
      wait;
   end process;

END;