source: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd@ 14065

Last change on this file since 14065 was 11513, checked in by vogler, 13 years ago
lightpulser interface modified to reduce LED current and light output
File size: 2.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Patrick Vogler
4--
5-- Create Date: March 2 2010
6-- Design Name:
7-- Module Name: FTM Lightpulser interface: single lightpulser
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: generates the signals to control a single lightpulser
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications:
21--
22--
23--
24-- modified: May 26 2011
25-- by Patrick Vogler
26-- "Lightpulser Basic Version"
27--
28-- modified: May 27 2011
29-- by Patrick Vogler
30--
31-- modified: May 27 2011
32-- by Patrick Vogler, Quirin Weitzel
33-- -> clean up
34--
35--
36-- modified: July 20 2011
37-- by Patrick Vogler
38-- reduce minimal LED light output and increase dynamic range
39--
40----------------------------------------------------------------------------------
41----------------------------------------------------------------------------------
42
43library IEEE;
44use IEEE.STD_LOGIC_1164.ALL;
45use IEEE.STD_LOGIC_ARITH.ALL;
46use IEEE.STD_LOGIC_UNSIGNED.ALL;
47
48
49library ftm_definitions;
50USE ftm_definitions.ftm_array_types.all;
51USE ftm_definitions.ftm_constants.all;
52
53
54
55entity single_LP_Basic is
56 port(
57
58-- Clock
59-------------------------------------------------------------------------------
60 clk_50 : IN STD_LOGIC; -- 50 MHz system clock
61-- clk_250 : IN STD_LOGIC; -- 250 MHz system clock
62
63-- Lightpulser
64-------------------------------------------------------------------------------
65 LP_Pulse_out : out STD_LOGIC :='0'; --
66
67
68-- FPGA intern signals: Lightpulser brightness
69-------------------------------------------------------------------------------
70 LP_pulse_in : in std_logic -- trigger lightpulse
71
72-- LP_delay : in std_logic_vector (15 downto 0)
73 );
74end single_LP_Basic;
75
76architecture Behavioral of single_LP_Basic is
77
78signal LP_in_prev : STD_LOGIC := '0';
79signal Pulse_Flag : STD_LOGIC := '0';
80
81begin
82
83single_LP_Basic_proc: process (clk_50)
84
85variable Y : integer range 0 to FLD_PULSE_LENGTH_Pulse;
86
87begin
88
89 if rising_edge(clk_50) then
90 LP_in_prev <= LP_pulse_in;
91
92 if ((LP_pulse_in = '1') and (LP_in_prev = '0')) then
93 Pulse_Flag <= '1';
94 end if;
95
96 if (Pulse_Flag = '1') then
97 if (Y < FLD_PULSE_LENGTH_Pulse) then
98 Y := Y + 1;
99 LP_Pulse_out <= '1';
100 else
101 Y := 0;
102 LP_Pulse_out <= '0';
103 Pulse_Flag <= '0';
104 end if;
105 end if;
106
107 end if;
108
109end process single_LP_Basic_proc;
110
111end Behavioral;
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