source: firmware/FTM/Lightpulser_interface/Lightpulser_interface_tb.vhd@ 16318

Last change on this file since 16318 was 10761, checked in by vogler, 14 years ago
Lightpulser first version added
File size: 6.5 KB
Line 
1--------------------------------------------------------------------------------
2-- Company:
3-- Engineer: Patrick Vogler
4--
5-- Create Date: 14:09:52 05/13/2011
6-- Design Name:
7-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface//Lightpulser_interface_tb.vhd
8-- Project Name: FLD
9-- Target Device:
10-- Tool versions:
11-- Description:
12--
13-- VHDL Test Bench Created by ISE for module: Lightpulser_interface
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28LIBRARY ieee;
29USE ieee.std_logic_1164.ALL;
30USE ieee.std_logic_unsigned.all;
31USE ieee.numeric_std.ALL;
32
33ENTITY Lightpulser_interface_tb IS
34END Lightpulser_interface_tb;
35
36ARCHITECTURE behavior OF Lightpulser_interface_tb IS
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 COMPONENT Lightpulser_interface
41 PORT(
42 clk_50 : IN std_logic;
43 clk_250 : IN std_logic;
44 Cal_0_p : OUT std_logic;
45 Cal_0_n : OUT std_logic;
46 Cal_1_p : OUT std_logic;
47 Cal_1_n : OUT std_logic;
48 Cal_2_p : OUT std_logic;
49 Cal_2_n : OUT std_logic;
50 Cal_3_p : OUT std_logic;
51 Cal_3_n : OUT std_logic;
52 Cal_4_p : OUT std_logic;
53 Cal_4_n : OUT std_logic;
54 Cal_5_p : OUT std_logic;
55 Cal_5_n : OUT std_logic;
56 Cal_6_p : OUT std_logic;
57 Cal_6_n : OUT std_logic;
58 Cal_7_p : OUT std_logic;
59 Cal_7_n : OUT std_logic;
60 LP1_ampl : IN std_logic_vector(15 downto 0);
61 LP2_ampl : IN std_logic_vector(15 downto 0);
62 LP1_delay : IN std_logic_vector(15 downto 0);
63 LP2_delay : IN std_logic_vector(15 downto 0);
64 LP1_pulse : IN std_logic;
65 LP2_pulse : IN std_logic;
66 start_config : IN std_logic;
67 config_started : OUT std_logic;
68 config_done : OUT std_logic
69 );
70 END COMPONENT;
71
72
73 --Inputs
74 signal clk_50 : std_logic := '0';
75 signal clk_250 : std_logic := '0';
76 signal LP1_ampl : std_logic_vector(15 downto 0) := (others => '0');
77 signal LP2_ampl : std_logic_vector(15 downto 0) := (others => '0');
78 signal LP1_delay : std_logic_vector(15 downto 0) := (others => '0');
79 signal LP2_delay : std_logic_vector(15 downto 0) := (others => '0');
80 signal LP1_pulse : std_logic := '0';
81 signal LP2_pulse : std_logic := '0';
82 signal start_config : std_logic := '0';
83
84 --Outputs
85 signal Cal_0_p : std_logic;
86 signal Cal_0_n : std_logic;
87 signal Cal_1_p : std_logic;
88 signal Cal_1_n : std_logic;
89 signal Cal_2_p : std_logic;
90 signal Cal_2_n : std_logic;
91 signal Cal_3_p : std_logic;
92 signal Cal_3_n : std_logic;
93 signal Cal_4_p : std_logic;
94 signal Cal_4_n : std_logic;
95 signal Cal_5_p : std_logic;
96 signal Cal_5_n : std_logic;
97 signal Cal_6_p : std_logic;
98 signal Cal_6_n : std_logic;
99 signal Cal_7_p : std_logic;
100 signal Cal_7_n : std_logic;
101 signal config_started : std_logic;
102 signal config_done : std_logic;
103
104 -- Clock period definitions
105 constant clk_50_period : time := 20 ns;
106 constant clk_250_period : time := 4 ns;
107
108BEGIN
109
110 -- Instantiate the Unit Under Test (UUT)
111 uut: Lightpulser_interface PORT MAP (
112 clk_50 => clk_50,
113 clk_250 => clk_250,
114 Cal_0_p => Cal_0_p,
115 Cal_0_n => Cal_0_n,
116 Cal_1_p => Cal_1_p,
117 Cal_1_n => Cal_1_n,
118 Cal_2_p => Cal_2_p,
119 Cal_2_n => Cal_2_n,
120 Cal_3_p => Cal_3_p,
121 Cal_3_n => Cal_3_n,
122 Cal_4_p => Cal_4_p,
123 Cal_4_n => Cal_4_n,
124 Cal_5_p => Cal_5_p,
125 Cal_5_n => Cal_5_n,
126 Cal_6_p => Cal_6_p,
127 Cal_6_n => Cal_6_n,
128 Cal_7_p => Cal_7_p,
129 Cal_7_n => Cal_7_n,
130 LP1_ampl => LP1_ampl,
131 LP2_ampl => LP2_ampl,
132 LP1_delay => LP1_delay,
133 LP2_delay => LP2_delay,
134 LP1_pulse => LP1_pulse,
135 LP2_pulse => LP2_pulse,
136 start_config => start_config,
137 config_started => config_started,
138 config_done => config_done
139 );
140
141 -- Clock process definitions
142 clk_50_process :process
143 begin
144 clk_50 <= '0';
145 wait for clk_50_period/2;
146 clk_50 <= '1';
147 wait for clk_50_period/2;
148 end process;
149
150 clk_250_process :process
151 begin
152 clk_250 <= '0';
153 wait for clk_250_period/2;
154 clk_250 <= '1';
155 wait for clk_250_period/2;
156 end process;
157
158
159 -- Stimulus process
160 stim_proc: process
161 begin
162 -- hold reset state for 100 ms.
163 -- wait for 100 ms;
164
165 wait for clk_50_period*10;
166
167 -- insert stimulus here
168
169 -- init input signals
170 start_config <= '0';
171 LP1_pulse <= '0';
172 LP2_pulse <= '0';
173
174
175
176 -- latch settings
177 LP1_ampl <= "1000000000000111";
178 LP2_ampl <= "0100000000010000";
179
180 LP1_delay <= "0000000000010000";
181 LP2_delay <= "0000000000000001";
182
183 wait for clk_50_period*5;
184 start_config <= '1';
185 wait for clk_50_period*1;
186 start_config <= '0';
187
188
189 wait for clk_50_period*5;
190
191
192 -- trigger lightpulses
193
194 -- LP1: mirror dish
195 LP1_pulse <= '1';
196 wait for clk_50_period*5;
197 LP1_pulse <= '0';
198
199 -- LP2: shutter
200 LP2_pulse <= '1';
201 wait for clk_50_period*5;
202 LP2_pulse <= '0';
203
204
205
206
207
208 -- next cyclus
209 wait for clk_50_period*10;
210
211
212 -- latch settings
213 LP1_ampl <= "1100000000000111";
214 LP2_ampl <= "0000000000010000";
215
216 LP1_delay <= "0000000001010000";
217 LP2_delay <= "0000000000000101";
218
219 wait for clk_50_period*5;
220 start_config <= '1';
221 wait for clk_50_period*1;
222 start_config <= '0';
223
224
225 wait for clk_50_period*5;
226
227 -- trigger lightpulses
228
229 -- LP1: mirror dish
230 LP1_pulse <= '1';
231 wait for clk_50_period*2;
232 LP1_pulse <= '0';
233
234 -- LP2: shutter
235 LP2_pulse <= '1';
236 wait for clk_50_period*2;
237 LP2_pulse <= '0';
238
239
240
241 wait;
242 end process;
243
244END;
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