source: firmware/FTM/Timing_counters/Timing_counter.vhd @ 10779

Last change on this file since 10779 was 10779, checked in by weitzel, 8 years ago
some changes in FTM Timing_counter
File size: 3.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:        ETH Zurich, Institute for Particle Physics
3-- Engineer:       Patrick Vogler
4--
5-- Create Date:    March 11  2011
6-- Design Name:   
7-- Module Name:    FTM Timing counter
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:    48 bit counter for time stamping and on-time counting
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19--
20-- modifications:
21--
22-- April 12 2011 by Patrick Vogler
23--
24-- May 18 2011 by Patrick Vogler
25--
26-- May 20, 2011, by Q. Weitzel
27-- counting was wrong by one clock cycle (1 us)
28--
29-- May 23, 2011, by Q. Weitzel
30-- counter reset changed from async to sync reset
31-- reset, enable and read_counter removed from sensitity lists
32--
33----------------------------------------------------------------------------------
34
35library IEEE;
36use IEEE.STD_LOGIC_1164.ALL;
37use IEEE.STD_LOGIC_ARITH.ALL;
38use IEEE.STD_LOGIC_UNSIGNED.ALL;
39
40use IEEE.NUMERIC_STD.ALL;
41
42---- Uncomment the following library declaration if instantiating
43---- any Xilinx primitives in this code.
44library UNISIM;
45use UNISIM.VComponents.all;
46
47library ftm_definitions;
48USE ftm_definitions.ftm_array_types.all;
49USE ftm_definitions.ftm_constants.all;
50
51
52entity Timing_counter is
53  port(
54   
55-- Clock
56-------------------------------------------------------------------------------
57   clk              : in   STD_LOGIC;       -- 50 MHz system clock
58
59   enable           : in   STD_LOGIC;       -- enable counter
60   reset            : in   Std_LOGIC;       -- reset counter
61
62   -- handshake signal
63   read_counter     : in   STD_LOGIC;       -- read counter
64   reading_started  : out  STD_LOGIC;
65   reading_valid    : out  STD_LOGIC;       -- counter reading at output ready
66
67   -- counter reading
68   counter_reading  : out  std_logic_vector (TC_WIDTH - 1 downto 0)   
69  );
70end Timing_counter; 
71
72
73architecture Behavioral of Timing_counter is
74
75type type_read_counter_state is (IDLE, COPY, SET_VALID, RESET_STARTED);   
76signal read_counter_state       : type_read_counter_state  := IDLE;   
77 
78signal counting            : std_logic_vector (TC_WIDTH - 1       downto 0) := (others => '0');
79signal counter_reading_sig : std_logic_vector (TC_WIDTH - 1       downto 0) := (others => '0');
80signal precounting         : std_logic_vector (PRECOUNT_WIDTH - 1 downto 0) := (others => '0');
81
82
83begin
84--  counting
85-------------------------------------------------------------------------------
86  count :  process (clk)
87  begin
88     
89    if rising_edge(clk) then
90      if (reset = '1') then
91        counting    <= (others => '0');
92        precounting <= (others => '0');       
93      elsif enable = '1' then
94        precounting <= precounting + 1;
95        if (precounting = (PRECOUNT_DIVIDER - 1)) then         
96          counting <= counting + 1;
97          precounting <= (others => '0');       
98        end if;         
99      end if;       
100    end if;
101   
102  end process count;
103
104-- read counter
105-------------------------------------------------------------------------------
106  readout_counter : process (clk)
107  begin
108    if rising_edge(clk) then
109       case read_counter_state is
110
111         when IDLE =>
112              if read_counter = '1' then 
113                 reading_valid <= '0';
114                 reading_started <= '1'; 
115                 read_counter_state <= COPY;
116              end if;
117                       
118         when COPY =>
119              counter_reading_sig <= counting;           
120              read_counter_state <= SET_VALID;
121
122         when SET_VALID =>               
123              read_counter_state <= RESET_STARTED;
124
125         when RESET_STARTED =>
126              if read_counter = '0' then 
127                 reading_started <= '0';
128                 reading_valid <= '1';
129                 read_counter_state <= IDLE;
130              end if;
131               
132       end case;           
133    end if; 
134end process readout_counter; 
135                 
136counter_reading <= counter_reading_sig;
137
138end Behavioral;
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