--------------------------------------------------------------------------------
-- Company:       Patrick Vogler
-- Engineer:
--
-- Create Date:   14:01:52 05/18/2011
-- Design Name:   
-- Module Name:   /home/pavogler/ISDC_repos/firmware/FTM/Timing_counters/Timing_counters_V2//Timing_counter_tb.vhd
-- Project Name:  Timing_counter_2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Timing_counter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
library ftm_definitions;
USE ftm_definitions.ftm_array_types.all;
USE ftm_definitions.ftm_constants.all; 
 
 
 
ENTITY Timing_counter_tb IS
END Timing_counter_tb;
 
ARCHITECTURE behavior OF Timing_counter_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Timing_counter
    PORT(
         clk : IN  std_logic;
         enable : IN  std_logic;
         reset : IN  std_logic;
         read_counter : IN  std_logic;
         reading_started : OUT  std_logic;
         reading_valid : OUT  std_logic;
         counter_reading : OUT  std_logic_vector(TC_WIDTH - 1 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal enable : std_logic := '0';
   signal reset : std_logic := '0';
   signal read_counter : std_logic := '0';

 	--Outputs
   signal reading_started : std_logic;
   signal reading_valid : std_logic;
   signal counter_reading : std_logic_vector(TC_WIDTH - 1 downto 0);

   -- Clock period definitions
   constant clk_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Timing_counter PORT MAP (
          clk => clk,
          enable => enable,
          reset => reset,
          read_counter => read_counter,
          reading_started => reading_started,
          reading_valid => reading_valid,
          counter_reading => counter_reading
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
   --   wait for 100 ms;	

      wait for clk_period*10;

      -- insert stimulus here 

    -- insert stimulus here 
      
      reset <= '0';
		enable <= '0';
		wait for clk_period*10;
      reset <= '1';    
      wait for clk_period*10;
      reset <= '0';
      wait for clk_period*10;
		
		
		
		
		
		-- readout		
		read_counter <= '1';
		wait for clk_period*2;
      read_counter <= '0';
		
		
		
		
		
		
		-- counting	50 periodes
		enable <= '1';
		wait for clk_period*500;
		enable <= '0';
				
		
		-- readout		
		read_counter <= '1';
		wait for clk_period*2;
      read_counter <= '0';




   -- new run
		
      reset <= '0';
		enable <= '0';
		wait for clk_period*10;
      reset <= '1';    
      wait for clk_period*10;
      reset <= '0';
      wait for clk_period*10;
		
		
		-- counting	251 periodes
		enable <= '1';
		wait for clk_period*250;
		enable <= '0';
				
		
		-- readout		
		read_counter <= '1';
		wait for clk_period*2;
      read_counter <= '0';


      




        -- new run
		
      reset <= '0';
		enable <= '0';
		wait for clk_period*10;
      reset <= '1';    
      wait for clk_period*10;
      reset <= '0';
      wait for clk_period*10;
		
		
		-- counting	70251 periodes
		enable <= '0';
		wait for clk_period*70251;
		enable <= '0';
				
		
		wait for clk_period*10;		
		-- readout		
		read_counter <= '1';
		wait for clk_period*2;
      read_counter <= '0';



		wait for clk_period*10;
		
	
	    enable <= '0';
	   wait for clk_period*10;
      reset <= '1';    
      wait for clk_period*10;
      reset <= '0';
      wait for clk_period*10;
		
      		
		-- readout		
		read_counter <= '1';
		wait for clk_period*2;
      read_counter <= '0';




      wait;
   end process;

END;