| 1 | --------------------------------------------------------------------------------
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| 2 | -- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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| 3 | --------------------------------------------------------------------------------
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| 4 | -- ____ ____
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| 5 | -- / /\/ /
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| 6 | -- /___/ \ / Vendor: Xilinx
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| 7 | -- \ \ \/ Version : 11.5
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| 8 | -- \ \ Application : xaw2vhdl
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| 9 | -- / / Filename : FTM_dcm_40M_to_250M.vhd
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| 10 | -- /___/ /\ Timestamp : 03/02/2011 11:02:39
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| 11 | -- \ \ / \
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| 12 | -- \___\/\___\
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| 13 | --
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| 14 | --Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_250M.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_250M
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| 15 | --Design Name: FTM_dcm_40M_to_250M
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| 16 | --Device: xc3sd3400a-4fg676
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| 17 | --
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| 18 | -- Module FTM_dcm_40M_to_250M
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| 19 | -- Generated by Xilinx Architecture Wizard
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| 20 | -- Written for synthesis tool: XST
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| 21 | -- Period Jitter (unit interval) for block DCM_SP_INST = 0.20 UI
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| 22 | -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.79 ns
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| 23 |
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| 24 | library ieee;
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| 25 | use ieee.std_logic_1164.ALL;
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| 26 | use ieee.numeric_std.ALL;
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| 27 | library UNISIM;
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| 28 | use UNISIM.Vcomponents.ALL;
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| 29 |
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| 30 | entity FTM_dcm_40M_to_250M is
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| 31 | port ( CLKIN_IN : in std_logic;
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| 32 | RST_IN : in std_logic;
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| 33 | CLKFX_OUT : out std_logic;
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| 34 | CLKFX180_OUT : out std_logic;
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| 35 | LOCKED_OUT : out std_logic);
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| 36 | end FTM_dcm_40M_to_250M;
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| 37 |
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| 38 | architecture BEHAVIORAL of FTM_dcm_40M_to_250M is
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| 39 | signal CLKFX_BUF : std_logic;
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| 40 | signal CLKFX180_BUF : std_logic;
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| 41 | signal GND_BIT : std_logic;
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| 42 | begin
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| 43 | GND_BIT <= '0';
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| 44 | CLKFX_BUFG_INST : BUFG
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| 45 | port map (I=>CLKFX_BUF,
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| 46 | O=>CLKFX_OUT);
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| 47 |
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| 48 | CLKFX180_BUFG_INST : BUFG
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| 49 | port map (I=>CLKFX180_BUF,
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| 50 | O=>CLKFX180_OUT);
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| 51 |
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| 52 | DCM_SP_INST : DCM_SP
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| 53 | generic map( CLK_FEEDBACK => "NONE",
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| 54 | CLKDV_DIVIDE => 2.0,
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| 55 | CLKFX_DIVIDE => 4,
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| 56 | CLKFX_MULTIPLY => 25,
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| 57 | CLKIN_DIVIDE_BY_2 => FALSE,
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| 58 | CLKIN_PERIOD => 25.000,
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| 59 | CLKOUT_PHASE_SHIFT => "NONE",
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| 60 | DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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| 61 | DFS_FREQUENCY_MODE => "LOW",
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| 62 | DLL_FREQUENCY_MODE => "LOW",
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| 63 | DUTY_CYCLE_CORRECTION => TRUE,
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| 64 | FACTORY_JF => x"C080",
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| 65 | PHASE_SHIFT => 0,
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| 66 | STARTUP_WAIT => FALSE)
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| 67 | port map (CLKFB=>GND_BIT,
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| 68 | CLKIN=>CLKIN_IN,
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| 69 | DSSEN=>GND_BIT,
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| 70 | PSCLK=>GND_BIT,
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| 71 | PSEN=>GND_BIT,
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| 72 | PSINCDEC=>GND_BIT,
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| 73 | RST=>RST_IN,
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| 74 | CLKDV=>open,
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| 75 | CLKFX=>CLKFX_BUF,
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| 76 | CLKFX180=>CLKFX180_BUF,
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| 77 | CLK0=>open,
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| 78 | CLK2X=>open,
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| 79 | CLK2X180=>open,
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| 80 | CLK90=>open,
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| 81 | CLK180=>open,
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| 82 | CLK270=>open,
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| 83 | LOCKED=>LOCKED_OUT,
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| 84 | PSDONE=>open,
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| 85 | STATUS=>open);
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| 86 |
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| 87 | end BEHAVIORAL;
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| 88 |
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| 89 |
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