source: firmware/FTM/clock/FTM_dcm_40M_to_50M.vhd@ 13371

Last change on this file since 13371 was 10227, checked in by weitzel, 14 years ago
first version of FTM firmware including ethernet and FTU interface; still some debugging needed
File size: 2.7 KB
Line 
1--------------------------------------------------------------------------------
2-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
3--------------------------------------------------------------------------------
4-- ____ ____
5-- / /\/ /
6-- /___/ \ / Vendor: Xilinx
7-- \ \ \/ Version : 11.5
8-- \ \ Application : xaw2vhdl
9-- / / Filename : FTM_dcm_40M_to_50M.vhd
10-- /___/ /\ Timestamp : 03/01/2011 18:26:24
11-- \ \ / \
12-- \___\/\___\
13--
14--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M
15--Design Name: FTM_dcm_40M_to_50M
16--Device: xc3sd3400a-4fg676
17--
18-- Module FTM_dcm_40M_to_50M
19-- Generated by Xilinx Architecture Wizard
20-- Written for synthesis tool: XST
21-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
22-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns
23
24library ieee;
25use ieee.std_logic_1164.ALL;
26use ieee.numeric_std.ALL;
27library UNISIM;
28use UNISIM.Vcomponents.ALL;
29
30entity FTM_dcm_40M_to_50M is
31 port ( CLKIN_IN : in std_logic;
32 RST_IN : in std_logic;
33 CLKFX_OUT : out std_logic;
34 LOCKED_OUT : out std_logic);
35end FTM_dcm_40M_to_50M;
36
37architecture BEHAVIORAL of FTM_dcm_40M_to_50M is
38 signal CLKFX_BUF : std_logic;
39 signal GND_BIT : std_logic;
40begin
41 GND_BIT <= '0';
42 CLKFX_BUFG_INST : BUFG
43 port map (I=>CLKFX_BUF,
44 O=>CLKFX_OUT);
45
46 DCM_SP_INST : DCM_SP
47 generic map( CLK_FEEDBACK => "NONE",
48 CLKDV_DIVIDE => 2.0,
49 CLKFX_DIVIDE => 4,
50 CLKFX_MULTIPLY => 5,
51 CLKIN_DIVIDE_BY_2 => FALSE,
52 CLKIN_PERIOD => 25.000,
53 CLKOUT_PHASE_SHIFT => "NONE",
54 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
55 DFS_FREQUENCY_MODE => "LOW",
56 DLL_FREQUENCY_MODE => "LOW",
57 DUTY_CYCLE_CORRECTION => TRUE,
58 FACTORY_JF => x"C080",
59 PHASE_SHIFT => 0,
60 STARTUP_WAIT => FALSE)
61 port map (CLKFB=>GND_BIT,
62 CLKIN=>CLKIN_IN,
63 DSSEN=>GND_BIT,
64 PSCLK=>GND_BIT,
65 PSEN=>GND_BIT,
66 PSINCDEC=>GND_BIT,
67 RST=>RST_IN,
68 CLKDV=>open,
69 CLKFX=>CLKFX_BUF,
70 CLKFX180=>open,
71 CLK0=>open,
72 CLK2X=>open,
73 CLK2X180=>open,
74 CLK90=>open,
75 CLK180=>open,
76 CLK270=>open,
77 LOCKED=>LOCKED_OUT,
78 PSDONE=>open,
79 STATUS=>open);
80
81end BEHAVIORAL;
82
83
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