source: firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 3.1 KB
Line 
1--------------------------------------------------------------------------------
2-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
3--------------------------------------------------------------------------------
4-- ____ ____
5-- / /\/ /
6-- /___/ \ / Vendor: Xilinx
7-- \ \ \/ Version : 11.5
8-- \ \ Application : xaw2vhdl
9-- / / Filename : FTM_dcm_50M_to_250M_2.vhd
10-- /___/ /\ Timestamp : 04/12/2011 10:57:30
11-- \ \ / \
12-- \___\/\___\
13--
14--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2
15--Design Name: FTM_dcm_50M_to_250M_2
16--Device: xc3sd3400a-4fg676
17--
18-- Module FTM_dcm_50M_to_250M_2
19-- Generated by Xilinx Architecture Wizard
20-- Written for synthesis tool: XST
21-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI
22-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns
23
24library ieee;
25use ieee.std_logic_1164.ALL;
26use ieee.numeric_std.ALL;
27library UNISIM;
28use UNISIM.Vcomponents.ALL;
29
30entity FTM_dcm_50M_to_250M_2 is
31 port ( CLKIN_IN : in std_logic;
32 RST_IN : in std_logic;
33 CLKFX_OUT : out std_logic;
34 CLKFX180_OUT : out std_logic;
35 CLK0_OUT : out std_logic;
36 LOCKED_OUT : out std_logic);
37end FTM_dcm_50M_to_250M_2;
38
39architecture BEHAVIORAL of FTM_dcm_50M_to_250M_2 is
40 signal CLKFB_IN : std_logic;
41 signal CLKFX_BUF : std_logic;
42 signal CLKFX180_BUF : std_logic;
43 signal CLK0_BUF : std_logic;
44 signal GND_BIT : std_logic;
45begin
46 GND_BIT <= '0';
47 CLK0_OUT <= CLKFB_IN;
48 CLKFX_BUFG_INST : BUFG
49 port map (I=>CLKFX_BUF,
50 O=>CLKFX_OUT);
51
52 CLKFX180_BUFG_INST : BUFG
53 port map (I=>CLKFX180_BUF,
54 O=>CLKFX180_OUT);
55
56 CLK0_BUFG_INST : BUFG
57 port map (I=>CLK0_BUF,
58 O=>CLKFB_IN);
59
60 DCM_SP_INST : DCM_SP
61 generic map( CLK_FEEDBACK => "1X",
62 CLKDV_DIVIDE => 2.0,
63 CLKFX_DIVIDE => 1,
64 CLKFX_MULTIPLY => 5,
65 CLKIN_DIVIDE_BY_2 => FALSE,
66 CLKIN_PERIOD => 20.000,
67 CLKOUT_PHASE_SHIFT => "NONE",
68 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
69 DFS_FREQUENCY_MODE => "LOW",
70 DLL_FREQUENCY_MODE => "LOW",
71 DUTY_CYCLE_CORRECTION => TRUE,
72 FACTORY_JF => x"C080",
73 PHASE_SHIFT => 0,
74 STARTUP_WAIT => FALSE)
75 port map (CLKFB=>CLKFB_IN,
76 CLKIN=>CLKIN_IN,
77 DSSEN=>GND_BIT,
78 PSCLK=>GND_BIT,
79 PSEN=>GND_BIT,
80 PSINCDEC=>GND_BIT,
81 RST=>RST_IN,
82 CLKDV=>open,
83 CLKFX=>CLKFX_BUF,
84 CLKFX180=>CLKFX180_BUF,
85 CLK0=>CLK0_BUF,
86 CLK2X=>open,
87 CLK2X180=>open,
88 CLK90=>open,
89 CLK180=>open,
90 CLK270=>open,
91 LOCKED=>LOCKED_OUT,
92 PSDONE=>open,
93 STATUS=>open);
94
95end BEHAVIORAL;
96
97
Note: See TracBrowser for help on using the repository browser.