source: firmware/FTM/clock/FTM_dcm_50M_to_250M_2_arwz.ucf@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 711 bytes
Line 
1# Generated by Xilinx Architecture Wizard
2# --- UCF Template Only ---
3# Cut and paste these attributes into the project's UCF file, if desired
4INST DCM_SP_INST CLK_FEEDBACK = 1X;
5INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
6INST DCM_SP_INST CLKFX_DIVIDE = 1;
7INST DCM_SP_INST CLKFX_MULTIPLY = 5;
8INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
9INST DCM_SP_INST CLKIN_PERIOD = 20.000;
10INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
11INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
12INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
13INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
14INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
15INST DCM_SP_INST FACTORY_JF = C080;
16INST DCM_SP_INST PHASE_SHIFT = 0;
17INST DCM_SP_INST STARTUP_WAIT = FALSE;
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