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1\documentclass[a4paper,11pt]{report}
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3\usepackage{float}
4\usepackage{graphicx}
5\usepackage{url}
6\usepackage[T1]{fontenc}
7\usepackage{amsmath}
8\usepackage{longtable}
9\usepackage{parskip}
10\usepackage{pifont}
11\usepackage{array}
12
13\setlength{\oddsidemargin}{0cm}
14\setlength{\evensidemargin}{0cm}
15\setlength{\topmargin}{0cm}
16
17\textwidth 6.2in
18\textheight 9in
19\columnsep 0.25in
20
21\pagestyle{plain}
22\setcounter{tocdepth}{1}
23
24\title{\vspace*{-7cm} \Huge \bf FTM Firmware Specifications}
25\author{\Large Patrick Vogler\footnote{Contact for questions and suggestions concerning this
26    document: {\tt patrick.vogler@phys.ethz.ch}}, Quirin Weitzel}
27\date{\vspace*{0.5cm} \Large v3.1~~~-~~~February 2011}
28
29\begin{document}
30
31\maketitle
32
33\newpage
34
35\tableofcontents
36
37%---------------------------------------------------------------------------------
38
39\chapter{Introduction}
40\label{cha:Introduction}
41
42The FTM (FACT Trigger Master) board collects the trigger primitives from all
4340 FTU boards (FACT Trigger Unit) and generates the trigger signal for the
44FACT camera. The trigger logic is a 'n-out-of-40' majority coincidence of all
45trigger primitives. Beside the trigger, the FTM board also generates a
46trigger-ID (see chapter \ref{cha:Trigger-ID}). It is controlled by the main
47control software via ethernet. Two auxiliary RS-485 interfaces are also
48available.
49
50In addition to the trigger, the FTM board also generates the other fast
51control signals: Time-Marker (TIM), DRS \cite{DRS4} reference clock (CLD) and
52reset. These four fast control signals are distributed to the FAD (FACT Analog
53to Digital) boards via the two FFC (FACT Fast Control) boards. The FTM board
54also provides via the TIM line the signal for the DRS timing calibration. In
55order to generate the CLD DRS reference clock, as well as the time-marker
56signal for DRS timing calibration, the FTM board uses a clock conditioner
57\cite{LMK03000}.
58
59The FTM board has two counters, the 'timestamp counter' and the 'on-time
60counter'. While the 'timestamp counter' runs continously (counting up,
61resetted by e.g. a 'start run'), the 'on-time counter' only counts when the
62camera trigger is enabled.
63
64The FTM board further serves as slow control master for the 40 FTU boards. The
65slow control of the FTU boards and the distribution of the trigger-ID to the
66FAD boards are performed via dedicated RS-485 buses. Because the FAD as well
67as the FTU boards are arranged in crates of 10 boards each, the FTM board has
68four connectors, one for each crate. Running over these connectors there are
69two RS-485 buses (one for FTU slow control and one for the trigger-ID) besides
70the busy signal from the FAD boards and the crate reset.
71
72In addition, the FTM board controls the two FLPs (FACT Light Pulser) via four
73LVDS signals each. Light pulser~1 is located in the mirror dish, light
74pulser~2 inside the camera shutter. There are also digital auxiliary in- and
75outputs according to the NIM (Nuclear Instrumentation Module) standard, for
76example for external triggers and veto, and to have the signals accessible.
77
78The main component of the FTM board is a FPGA (Xilinx Spartan
79XC3SD3400A-4FGG676C), fulfilling the main functions within the board. The
80purpose of this document is to provide specifications needed for the
81development of the firmware of this FPGA and the software (called 'main
82control' in the following) controlling the FTM board. For further information
83about the FTM board hardware please refer to \cite{FTM-Schematics}.
84
85\chapter{Trigger-ID}
86\label{cha:Trigger-ID}
87
88For each processed trigger the FTM board generates a unique trigger-ID to be
89broadcasted to all FAD boards and added to the event data. This trigger-ID
90consists of a 32 bit trigger number, a two byte trigger type indicator and a
91checksum. The transmission protocol for the trigger-ID broadcast is shown in
92table \ref{tab:Trigger-ID broadcast}.
93
94\begin{table}[htbp]
95\centering
96\begin{tabular}{|l|l|}\hline
97byte no & content\\\hline\hline
980 & Trigger-No first byte (least significant byte) \\\hline
991 & Trigger-No second byte\\\hline
1002 & Trigger-No third byte\\\hline
1013 & Trigger-No forth byte (most significant byte)\\\hline
1024 & Trigger-Type 1\\\hline
1035 & Trigger-Type 2\\\hline
1046 & CRC-8-CCITT (checksum)\\\hline
105\end{tabular}
106\caption{The transmission protocol to broadcast the trigger-ID to the FAD boards}
107\label{tab:Trigger-ID broadcast}
108\end{table}
109
110A Cyclic Redundancy Check (CRC) over byte 0 - 5 is used to evaluate the
111integrity of the trigger-ID. An 8-CCITT CRC has been chosen which is based on
112the polynomial $x^8 + x^2 + x + 1$ (00000111, omitting the most significant
113bit). The resulting 1-byte checksum comprises the last byte of the trigger-ID.
114The transmission of the trigger-ID to the FAD boards is done by means of
115dedicated RS-485 buses (one per crate).
116
117In the first byte of the trigger type indicator (see table
118\ref{tab:Trigger-Type 1}) n0 - n5 indicate the number of trigger primitives
119required for a trigger, thus the 'n' of the 'n-out-of-40' majority
120coincidence. The two flags 'external trigger 1' and 'external trigger 2',
121when set, indicate a trigger from the corresponding NIM inputs. See also
122section \ref{sec:Static-data-block} and table \ref{tab:FTM-majority} for
123further information.
124
125\begin{table}[htbp]
126\centering
127%\begin{small}
128\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
129  Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
130  n5 & n4 & n3 & n2 & n1 & n0 & external trigger 2 & external trigger 1\\\hline
131\end{tabular}
132%\end{small}
133\caption{Trigger-Type 1}
134\label{tab:Trigger-Type 1}
135\end{table}
136
137\begin{table}[htbp]
138\centering
139\begin{small}
140\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
141Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
142TIM source & LP\_set\_3 & LP\_set\_2 & LP\_set\_1 & LP\_set\_0 & pedestal & LP\_2 & LP\_1\\\hline
143\end{tabular}
144\end{small}
145\caption{Trigger-Type 2}
146\label{tab:Trigger-Type 2}
147\end{table}
148
149The 'TIM source' bit in 'Trigger-Type 2' (see table \ref{tab:Trigger-Type 2})
150indicates the source of the timemarker signal: a '0' indicates the timemarker
151being produced in the FPGA while a '1' indicates the timemarker coming from
152the clock conditioner. The flags 'LP\_1' and 'LP\_2' are set when the
153corresponding lightpulser has flashed while the 'pedestal' flag is set in case
154of a pedestal (random) trigger. An event having none of these flags set
155indicates a physics event. The bits 'LP\_set\_0' to 'LP\_set\_3' are used to
156code information about the light pulser settings. They only have a meaning in
157case of calibration events.
158
159\chapter{FTM Commands}
160\label{cha:FTM-Commands}
161
162The communication between the FTM board and the main control, including the
163corresponding commands, protocols and data, is based on 16-bit words and
164big-endian. This is to facilitate the data-transmission over the Wiznet W5300
165ethernet interface \cite{W5300}.
166
167The basic structure of all commands is the same and given in table
168\ref{tab:FTM-command-structure}. After a start delimiter, the second word
169identifies the command. Next there is a parameter further refining the
170command, e.g. what to read. The fourth and fifth words are spares and should
171contain zeros. Starting from the sixth word, an optional data block of
172variable size is following. This data block differs in length and content
173depending on command and parameter. In case of 'read' instructions, the
174corresponding data block is sent back.
175
176%The FTM board must answer every command by sending back the appropriate data
177%block or by simply sending back the instruction where there is no datablock to
178%be sent back.  All 'read' commands to the FTM board do not contain any data
179%blocks, but the FTM boards response does.  In case of 'read' and 'write'
180%instructions, the datablock is to be sent back. When 'start run' or 'stop run'
181%commands are used, the FTM board 'mirrors' them, i.e. sends them back for
182%confirmation.
183
184\begin{table}[p]
185\centering
186\begin{tabular}{|l|l|}\hline
187  word no & content\\\hline\hline
188  0 & start delimiter (e.g. '@') \\\hline
189  1 & command ID \\\hline
190  2 & command parameter \\\hline
191  3 & spare: containing 0x0000\\\hline
192  4 & spare: containing 0x0000 \\\hline
193  5 & data block (optional and of variable size)\\\hline
194  ... & ...\\\hline
195  X & data block\\\hline
196\end{tabular}
197\caption{FTM command structure}
198\label{tab:FTM-command-structure}
199\end{table}
200
201So far six different commands are foreseen: 'read', 'write', 'start run',
202'stop run', 'ping FTUs' and 'crate reset' (see table
203\ref{tab:FTM-command-ID}). The command parameters of the 'read' command are
204shown in table~\ref{tab:FTM-read-command-param}. For the 'write' command there
205is no option because the static data block is the only data that can be
206written to the FTM board.
207
208\begin{table}[p]
209\centering
210\begin{tabular}{|r|r|}\hline
211  command-ID: bits & \\\cline{1-1}
212  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command\\\hline\hline
213  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read \\\hline
214  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & write \\\hline
215  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start run / take X events\\\hline
216  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & stop run \\\hline
217  0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 & ping all FTUs \\\hline
218  0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & crate reset \\\hline
219\end{tabular}
220\caption{FTM command ID listing}
221\label{tab:FTM-command-ID}
222\end{table}
223
224\begin{table}[p]
225\centering
226\begin{tabular}{|r|r|r|}\hline
227  command parameter: bits & & \\\cline{1-1}
228  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
229  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read static data block & no\\\hline
230  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & read dynamic data block & no\\\hline
231  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & read trigger list & no\\\hline
232\end{tabular}
233\caption{Command parameters for the 'read' command}
234\label{tab:FTM-read-command-param}
235\end{table}
236
237%\begin{table}[htbp]
238%\centering
239%\begin{tabular}{|r|r|r|}\hline
240%  command parameter: bits & & \\\cline{1-1}
241%  15 ... 8  \vline 7  \vline 6  \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
242%  0 \vline 0 \vline 0 \vline 0 \vline 0  \vline0 \vline 0  \vline0  \vline1 & write static data & static data block\\\hline
243%\end{tabular}
244%\caption{Command parameters for the 'write' command}
245%\label{tab:FTM-write-command-param}
246%\end{table}
247
248In table \ref{tab:FTM-start-command-param} the parameters to start a run are
249listed. The type of the run is fully described in the FTM configuration
250(static data block, see section~\ref{sec:Static-data-block}), which always has
251to be sent by the main control before starting a run. Therefore the only
252option is to start an "endless" run or to take X events instead. In the latter
253case X is defined by a two words (32 bit) long unsigned integer, making up the
254command data block. The 'start run' command enables the transmission of
255trigger signals (physics, calibration or pedestal) to the FAD boards and
256resets the trigger and time counters. There is no parameter for stopping a
257run. If a number of events has been specified ('take X events'), the run will
258terminate if either the 'stop run' command is received or the requested number
259of events is reached.
260
261When a run is stopped, either by the 'stop run' command or when the specified number
262of events is taken, the trigger and time counters are reset, too.
263
264
265
266\begin{table}[p]
267\centering
268\begin{tabular}{|r|r|r|}\hline
269  command parameter: bits & & \\\cline{1-1}
270  15 ... 8  \vline\vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
271  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & start run & no \\\hline
272  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & take X events & number of events X \\\hline
273  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start taking pedestals & no \\\hline
274  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 1 & take X pedestals events & number of events X \\\hline
275  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & start calibration run & no \\\hline
276  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 1 & take X calibration events & number of events X \\\hline
277\end{tabular}
278\caption{Command parameters for the 'start run' command: "start run" means an "endless" run, i.e. no prespecified number of events.}
279\label{tab:FTM-start-command-param}
280\end{table}
281
282%\begin{table}[htbp]
283%\centering
284%\begin{tabular}{|r|r|r|}\hline
285%  command parameter: bits & & \\\cline{1-1}
286%  15 ... 8  \vline 7 \vline 6 \vline 5 \vline 4  \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
287%  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & stop run & no\\\hline
288%\end{tabular}
289%\caption{Command parameter for the 'stop run' command}
290%\label{tab:FTM-stop-command-param}
291%\end{table}
292
293In case of a 'ping FTUs' command the FTM will address the FTUs one by one and
294readout their DNA. The results are collected in the FTU list (see section
295\ref{sec:FTU-List}), which is sent back to the main control. There are no
296parameters for this command. With the 'crate reset' command the boards of a
297particular crate can be rebooted, where the command parameter defines the
298crate number (see table \ref{tab:FTM-reset-command-param}). Only one crate
299reset at a time is possible, i.e. the FTM firmware does not allow to reset
300multiple crates in one command.
301
302\begin{table}[p]
303\centering
304\begin{tabular}{|r|r|r|}\hline
305  command parameter: bits & & \\\cline{1-1}
306  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
307  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reset crate 0 & no\\\hline
308  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & reset crate 1 & no\\\hline
309  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & reset crate 2 & no\\\hline
310  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & reset crate 3 & no\\\hline
311\end{tabular}
312\caption{Command parameters for the 'crate reset' command: the command parameter may only contain a single "1"
313         corresponding to only one crate reset at a time.}
314\label{tab:FTM-reset-command-param}
315\end{table}
316
317\chapter{FTM data blocks}
318\label{cha:FTM-data-block}
319
320The trigger master features two main data blocks, named 'static data block'
321and 'dynamic data block' in the following. They are implemented in the
322firmware as block-RAM. In addition, there is the so-called 'FTU list', which
323is generated only on request ('ping FTUs' command). If any of these blocks is
324sent to the main control (either automatically or on demand), a header with a
325size of eleven words is added. This header is identical for all data blocks
326and contains solely read-only information: the FTM board ID (57-bit Xilinx
327device DNA \cite{ds557, ds610, wp267, wp266}), a firmware ID and the readings
328of the trigger counter and time stamp counter. The header structure is
329summarized in table~\ref{tab:FTM-header}.
330
331\begin{table}[h]
332\centering
333\begin{tabular}{|l|l|}\hline
334  word no & content\\\hline\hline
335  0x000 & board ID bits 63...48 \\\hline
336  0x001 & board ID bits 47...32\\\hline
337  0x002 & board ID bits 31...16\\\hline
338  0x003 & board ID bits 15...0\\\hline
339  0x004 & firmware ID \\\hline
340  0x005 & Trigger counter at read-out time bits 31...16 \\\hline
341  0x006 & Trigger counter at read-out time bits 15...0\\\hline
342  0x007 & Time stamp counter at read-out time bits 47...32 \\\hline
343  0x008 & Time stamp counter at read-out time bits 31...16 \\\hline
344  0x009 & Time stamp counter at read-out time bits 15...0 \\\hline
345  0x00A & spare \\\hline
346\end{tabular}
347\caption{Header structure for sending a data block}
348\label{tab:FTM-header}
349\end{table}
350
351\section{Static data block}
352\label{sec:Static-data-block}
353
354The static data block contains all the settings needed to configure and
355operate the FTM. It has to be written by the main control each time before a
356run is started or, in general, some component has to be reprogrammed. Single
357register access is not foreseen for the moment. In addition, whenever the FTM
358board receives a new static data block, it performs a complete reconfiguration
359including a reprogramming of the
360FTUs. Table~\ref{tab:FTM-trigger-master-static-data-block} summarizes the
361static data block. More details about the individual registers can be found in
362the subsequent tables.
363
364%These settings are readable and writable by the main control using the
365%corresponding commands 'read static data block' or 'write static data block',
366%respectively.  There is one exception from writability: In case the static
367%data block is read back, the first eleven words (address 0..A) are identical
368%with the dynamic data block and the trigger list shown in
369%\ref{tab:FTM-trigger-master-dynamic-data-block} and
370%\ref{tab:FTM-trigger-list}.  These first eleven words can only be read and not
371%written.  The board ID is supposed to be the Xilinx device DNA \cite{ds557,
372%  ds610, wp267, wp266}, the 57 bit device ID of the FPGA.  When using the
373%'write static data block' command, the static data block must start with the
374%'general settings register' at address 0x00B. So there is an offset in the
375%addresses of 0x00B between the 'read-out-version' and the 'write-version' of
376%the static data block.
377
378\begin{longtable}[h]{|l|l|}\hline
379\centering
380word no & content\\\hline\hline
381%0x000 & board ID bit 63 - 48 \\\hline
382%0x001 & board ID bit 47 - 32\\\hline
383%0x002 & board ID bit 31 - 16\\\hline
384%0x003 & board ID bit 15 - 0\\\hline
385%0x004 & firmware ID \\\hline
386%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
387%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
388%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
389%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
390%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
391%0x00A & spare \\\hline
3920x000 & general settings\\\hline
3930x001 & on-board status LEDs\\\hline
3940x002 & light pulser and pedestal trigger frequency\\\hline
3950x003 & ratio between LP1, LP2 and pedestal triggers\\\hline
3960x004 & light pulser 1 amplitude\\\hline
3970x005 & light pulser 2 amplitude\\\hline
3980x006 & light pulser 1 delay\\\hline
3990x007 & light pulser 2 delay\\\hline
4000x008 & majority coincidence n (for physics)\\\hline
4010x009 & majority coincidence n (for calibration)\\\hline
4020x00A & trigger delay\\\hline
4030x00B & timemarker delay\\\hline
4040x00C & dead time\\\hline
4050x00D & clock conditioner R0 bits 31...16 \\\hline
4060x00E & clock conditioner R0 bits 15...0 \\\hline
4070x00F & clock conditioner R1 bits 31...16 \\\hline
4080x010 & clock conditioner R1 bits 15...0 \\\hline
4090x011 & clock conditioner R8 bits 31...16 \\\hline
4100x012 & clock conditioner R8 bits 15...0 \\\hline
4110x013 & clock conditioner R9 bits 31...16 \\\hline
4120x014 & clock conditioner R9 bits 15...0 \\\hline
4130x015 & clock conditioner R11 bits 31...16 \\\hline
4140x016 & clock conditioner R11 bits 15...0 \\\hline
4150x017 & clock conditioner R13 bits 31...16 \\\hline
4160x018 & clock conditioner R13 bits 15...0 \\\hline
4170x019 & clock conditioner R14 bits 31...16 \\\hline
4180x01A & clock conditioner R14 bits 15...0 \\\hline
4190x01B & clock conditioner R15 bits 31...16 \\\hline
4200x01C & clock conditioner R15 bits 15...0 \\\hline
4210x01D & spare \\\hline
4220x01E & spare \\\hline
4230x01F & spare \\\hline
4240x020 & enables patch 0 board 0 crate 0 \\\hline
4250x021 & enables patch 1 board 0 crate 0 \\\hline
4260x022 & enables patch 2 board 0 crate 0 \\\hline
4270x023 & enables patch 3 board 0 crate 0 \\\hline
4280x024 & DAC$\_$A board 0 crate 0 \\\hline
4290x025 & DAC$\_$B board 0 crate 0 \\\hline
4300x026 & DAC$\_$C board 0 crate 0 \\\hline
4310x027 & DAC$\_$D board 0 crate 0 \\\hline
4320x028 & DAC$\_$H board 0 crate 0 \\\hline
4330x029 & Prescaling board 0 crate 0 \\\hline
4340x02A & enables patch 0 board 1 crate 0 \\\hline
4350x02B & enables patch 1 board 1 crate 0 \\\hline
4360x02C & enables patch 2 board 1 crate 0 \\\hline
4370x02D & enables patch 3 board 1 crate 0 \\\hline
4380x02E & DAC$\_$A board 1 crate 0 \\\hline
4390x02F & DAC$\_$B board 1 crate 0 \\\hline
4400x030 & DAC$\_$C board 1 crate 0 \\\hline
4410x031 & DAC$\_$D board 1 crate 0 \\\hline
4420x032 & DAC$\_$H board 1 crate 0 \\\hline
4430x033 & Prescaling board 1 crate 0 \\\hline
444... & ... \\\hline
4450x1A6 & enables patch 0 board 9 crate 3 \\\hline
4460x1A7 & enables patch 1 board 9 crate 3 \\\hline
4470x1A8 & enables patch 2 board 9 crate 3 \\\hline
4480x1A9 & enables patch 3 board 9 crate 3 \\\hline
4490x1AA & DAC$\_$A board 9 crate 3 \\\hline
4500x1AB & DAC$\_$B board 9 crate 3 \\\hline
4510x1AC & DAC$\_$C board 9 crate 3 \\\hline
4520x1AD & DAC$\_$D board 9 crate 3 \\\hline
4530x1AE & DAC$\_$H board 9 crate 3 \\\hline
4540x1AF & Prescaling board 9 crate 3 \\\hline
4550x1B0 & active FTU list crate 0 \\\hline
4560x1B1 & active FTU list crate 1 \\\hline
4570x1B2 & active FTU list crate 2 \\\hline
4580x1B3 & active FTU list crate 3 \\\hline 
459\caption{Overview of the FTM static data block}
460\label{tab:FTM-trigger-master-static-data-block}
461\end{longtable}
462
463The FTM general settings register is detailed in table
464\ref{tab:FTM-general-settings-register}. The 'TIM\_CLK' bit defines whether
465the time marker is generated by the FPGA ('TIM\_CLK' = 0, default for physics
466data taking), or whether it is generated by the clock conditioner ('TIM\_CLK'
467= 1, e.g. for DRS timing calibration). The 'ext\_veto', 'ext\_trig\_1' and
468'ext\_trig\_2' bits enable (1) or disable (0) the NIM inputs for the external
469veto and trigger signals, respectively. In order to select which trigger
470sources are active during a run, the bits 'LP1', 'LP2', 'ped' and 'trigger'
471are foreseen (0 disabled, 1 enabled). During a physics run, for example,
472'LP1', 'ped' and 'trigger' should all be set to generate interleaved
473calibration and pedestal events as well as activate the 'n-out-of-40' trigger
474input. For a didicated pedestal run only 'ped' should be set, since in this
475case the FTM sends directly a trigger to the FADs. For calibration runs it
476depends on whether the external (LP1) or internal (LP2) light pulser is used:
477For the first case 'LP1' and 'trigger' have to be set, since here the full
478trigger chain is involved and the camera triggers based on G-APD signals. For
479the second case only 'LP2' is needed, because the shutter is closed and the
480FTM sends directly the trigger signal to the FADs (like for pedestal
481events). Bits 8 to 15 of the general settings register are not used up to now.
482
483\begin{table}[h]
484\centering
485\begin{small}
486\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
487Bit & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
488Content & x & trigger & ped & LP2 & LP1 & ext\_trig\_2 & ext\_trig\_1& ext\_veto & TIM\_CLK \\\hline
489\end{tabular}
490\end{small}
491\caption{FTM general settings register}
492\label{tab:FTM-general-settings-register}
493\end{table}
494
495%\begin{table}[!h]
496%\centering
497%\begin{tabular}{|l|l|}\hline
498%TIM\_CClk & description \\\hline\hline
499%0 & Time marker generated in the FPGA \\\hline
500%1 & Time marker generated by the clock conditioner \\\hline
501%\end{tabular}
502%\caption{FTM Time marker indication}
503%\label{tab:FTM-Time-marker-indication}
504%\end{table}
505
506%\begin{table}[!h]
507%\centering
508%\begin{tabular}{|l|l|}\hline
509%ena$\_$ext$\_$Veto  & description \\\hline\hline
510%0 & disable external trigger veto\\\hline
511%1 & enable external trigger veto \\\hline
512%\end{tabular}
513%\caption{FTM external trigger}
514%\label{tab:FTM-external-trigger}
515%\end{table}
516
517%\begin{table}[!h]
518%\centering
519%\begin{tabular}{|l||l|}\hline
520%ena\_LP1  & description \\\hline\hline
521%0 & disable light pulser 1 \\\hline
522%1 & enable light pulser 1\\\hline
523%\end{tabular}
524%\caption{FTM light pulser 1}
525%\label{tab:FTM-light-pulser-1}
526%\end{table}
527
528%\begin{table}[!h]
529%\centering
530%\begin{tabular}{|l||l|}\hline
531%ena\_LP2  & description \\\hline\hline
532%0 & disable light pulser 2 \\\hline
533%1 & enable light pulser 2 \\\hline
534%\end{tabular}
535%\caption{FTM light pulser 2}
536%\label{tab:FTM-light-pulser-2}
537%\end{table}
538
539%\begin{table}[!h]
540%\centering
541%\begin{tabular}{|l||l|}\hline
542%ena\_Ped  & description \\\hline\hline
543%0 & disable interleaved pedestal trigger \\\hline
544%1 & enable interleaved pedestal trigger \\\hline
545%\end{tabular}
546%\caption{FTM interleaved pedestals}
547%\label{tab:FTM-interleaved-pedestals}
548%\end{table}
549
550%\begin{table}[!h]
551%\centering
552%\begin{small}
553%\begin{tabular}{|l||l|}\hline
554%ena\_LLC  & description \\\hline\hline
555%0 & disable low level calibration pulses \\\hline
556%1 & enable low level calibration pulses \\\hline
557%\end{tabular}
558%\end{small}
559%\caption{FTM low level calibration pulses}
560%\label{tab:FTM-low-level-calibration-pulses}
561%\end{table}
562
563The 'on-board status LEDs' register shown in table \ref{tab:FTM-LED-register}
564allows to switch a total of eight LEDs on the FTM board for debugging purposes
565by setting the corresponding bit high.
566
567\begin{table}[h]
568\centering
569\begin{small}
570\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
571Bit      & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
572Content &  x & red$\_$3 & red$\_$2 & gn$\_$1 & ye$\_$1 & red$\_$1 & gn$\_$0 & ye$\_$0 & red$\_$0 \\\hline
573\end{tabular}
574\end{small}
575\caption{'on-board status LEDs' register}
576\label{tab:FTM-LED-register}
577\end{table}
578
579The frequency, with which light pulser and pedestal triggers are sent, is
580stored in the register at address 0x002 (see table
581\ref{tab:FTM-frequency-register}). It is given in Hz and adjustable up to
582about 1\,kHz (10 bit). The next register defines the ratio of LP1, LP2 and
583pedestal events (see table \ref{tab:FTM-ratio-register}).
584 
585\begin{table}[h]
586\centering
587\begin{small}
588\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
589Bit      & 15 - 10 & 9 & 8 & ... & 2 & 1 & 0 \\\hline
590Content &  x  & FREQ\_9 & FREQ\_8 & ... & FREQ\_2 & FREQ\_1 & FREQ\_0 \\\hline
591\end{tabular}
592\end{small}
593\caption{Register for the frequency of calibration and pedestal events}
594\label{tab:FTM-frequency-register}
595\end{table}
596
597\begin{table}[h]
598\centering
599\begin{small}
600\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|}\hline
601Bit      & 15 - 12 & 11 & ... & 8 & 7 & ... & 4 & 3 & ... & 0 \\\hline
602Content & x & ped\_R3 & ... & ped\_R0 & LP2\_R3 & ... & LP2\_R0 & LP1\_R3 & ... & LP1\_R0 \\\hline
603\end{tabular}
604\end{small}
605\caption{Register defining the ratio between pedestal, LP1 and LP2 events}
606\label{tab:FTM-ratio-register}
607\end{table}
608
609%\begin{table}[!h]
610%\centering
611%\begin{tiny}
612%\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
613%Bit      & 15 - 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
614%Function &  x  & LPR2\_9 & LPR2\_8 & LPR2\_7 & LPR2\_6 & LPR2\_5 & LPR2\_4 & LPR2\_3 & LPR2\_2 & LPR2\_1 & LPR2\_0 \\\hline
615%\end{tabular}
616%\end{tiny}
617%\caption{Light pulser 2 frequency register at address 0x00E: This register contains the pulse rate of the light
618%               pulser 2 in Hz.}
619%\label{tab:Light-pulser-2-frequancy-register}
620%\end{table}
621
622In order to define the amplitude and characteristics of the light pulses that
623are generated by the LP1 and the LP2 system, the registers 'LP1 amplitude' and
624'LP2 amplitude' are used, respectively. These registers are presented in
625table~\ref{tab:LP1-amplitude-register} and
626table~\ref{tab:LP2-amplitude-register}. In general the light pulser systems
627are controlled from the FTM by means of four control lines: The first line
628defines the amplitude of the calibration events by sending a gate/pulse with
629an adjustable length (bits 0 to 3 in the amplitude registers). With the second
630and third line additional LEDs can be switched on in the calibration systems
631(bits 13 and 14). The fourth line is used to overdrive the LP systems and to
632generate a very fast timing pulse. To do so, bit 15 has to be set to 1.
633
634\begin{table}[!h]
635\centering
636\begin{small}
637\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
638Bit      & 15 & 14 & 13 & 12...4 & 3 & ... & 0 \\\hline
639Content & FCP1 &  add\_LEDs1\_1& add\_LEDs1\_0 & x & LP1A\_3 & ... & LP1A\_0 \\\hline
640\end{tabular}
641\end{small}
642\caption{Light pulser 1 amplitude register}
643\label{tab:LP1-amplitude-register}
644\end{table}
645
646\begin{table}[!h]
647\centering
648\begin{small}
649\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
650Bit      & 15 & 14 & 13 & 12...4 & 3 & ... & 0 \\\hline
651Content & FCP2 & add\_LEDs2\_1 & add\_LEDs2\_0 & x & LP2A\_3 & ... & LP2A\_0 \\\hline
652\end{tabular}
653\end{small}
654\caption{Light pulser 2 amplitude register}
655\label{tab:LP2-amplitude-register}
656\end{table}
657
658The different settings of the 'n-out-of-40' logic (physics or calibration
659events) are stored in two separate registers, which both have a structure
660according to table~\ref{tab:FTM-majority}.
661
662\begin{table}[!h]
663\centering
664\begin{small}
665\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
666Bit      & 15...6 & 5 & 4 & 3 & 2 &1 & 0 \\\hline
667Content & x & n5 & n4 & n3 & n2 & n1 & n0 \\\hline
668\end{tabular}
669\end{small}
670\caption{Structure of the two majority coincidence (n-out-of-40) registers; the binary value
671                in these registers is the number n of FTU trigger primitives required to trigger an event (physics or calibration)}
672\label{tab:FTM-majority}
673\end{table}
674
675In addtion, there are several registers in the static data block to define
676delays (e.g. for the trigger). Also a general dead time to be applied after
677each trigger can be set (to compensate for the delay of the busy line). The
678clock conditioner settings are specified at address 0x00D to 0x01C (LMK03000
679from National Semiconductor, for more details see \cite{LMK03000}). Starting
680at address 0x020, the FTU settings are stored. The FTM always holds the
681complete FTU parameters in the static data block. For the meaning of these
682registers, please refer to the FTU firmware specifications document
683\cite{FTUspecs}.
684In case not all FTUs are connected during e.g. the testing
685phase, or a FTU is broken, the 'active FTU list' registers can be used to
686disable certain boards.
687
688The bits 9 ... 0 of the active FTU list (address 0x1B0 to 0x1B3, corresponding
689to crate 0 to 3) contain the "active" flag for every FTU board. Setting a
690bit activates the corresponding FTU board while a "0" deactivates it.
691
692
693
694
695
696
697
698\section{Dynamic data block}
699\label{sec:Dynamic-data-block}
700The dynamic data block shown in table \ref{tab:FTM-dynamic-data-block}
701contains permanently updated data stored inside the FTM FPGA. It contains the
702actual on-time counter reading, the board temperatures and the trigger rates
703measured by the FTUs. This data block is updated and sent periodically by the
704FTM. Thus the main control software receives periodically a corresponding data
705package via ethernet.
706The counting interval of the FTU board 0 on crate 0
707('prescaling' register) defines the period. The on-board 12-bit temperature
708sensors are MAX6662 chips from Maxim Products. For more information about
709these components and their data see \cite{MAX6662}. When sending the dynamic
710data block, the header defined in table~\ref{tab:FTM-header} is added at the
711beginning.
712
713% \begin{table}[h]
714%  \centering
715\begin{longtable}[h]{|l|l|}\hline
716word no & content\\\hline\hline
717%0x000 & board ID bit 63 - 48 \\\hline
718%0x001 & board ID bit 47 - 32\\\hline
719%0x002 & board ID bit 31 - 16\\\hline
720%0x003 & board ID bit 15 - 0\\\hline
721%0x004 & firmware ID \\\hline
722%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
723%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
724%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
725%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
726%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
727%0x00A & spare \\\hline
728
7290x000 & on-time counter at read-out time bits 47...32 \\\hline
7300x001 & on-time counter at read-out time bits 31...16 \\\hline
7310x002 & on-time counter at read-out time bits 15...0 \\\hline
7320x003 & temperature sensor 0: component U45 on the FTM schematics \cite{FTM-Schematics}\\\hline
7330x004 & temperature sensor 1: U46 \\\hline
7340x005 & temperature sensor 2: U48 \\\hline
7350x006 & temperature sensor 3: U49 \\\hline
7360x007 & rate counter bit 29...16 patch 0 board 0 crate 0 \\\hline
7370x008 & rate counter bit 15...0 patch 0 board 0 crate 0 \\\hline
7380x009 & rate counter bit 29...16 patch 1 board 0 crate 0 \\\hline
7390x00A & rate counter bit 15...0 patch 1 board 0 crate 0 \\\hline
7400x00B & rate counter bit 29...16 patch 2 board 0 crate 0 \\\hline
7410x00C & rate counter bit 15...0 patch 2 board 0 crate 0 \\\hline
7420x00D & rate counter bit 29...16 patch 3 board 0 crate 0 \\\hline
7430x00E & rate counter bit 15...0 patch 3 board 0 crate 0 \\\hline
7440x00F & rate counter bit 29...16 total board 0 crate 0 \\\hline
7450x010 & rate counter bit 15...0 total board 0 crate 0\\\hline
7460x011 & Overflow register board 0 crate 0 \\\hline
7470x012 & CRC-error register board 0 crate 0 \\\hline
7480x013 & rate counter bit 29...16 patch 0 board 1 crate 0 \\\hline
7490x014 & rate counter bit 15...0 patch 0 board 1 crate 0 \\\hline
7500x015 & rate counter bit 29...16 patch 1 board 1 crate 0 \\\hline
7510x016 & rate counter bit 15...0 patch 1 board 1 crate 0 \\\hline
7520x017 & rate counter bit 29...16 patch 2 board 1 crate 0 \\\hline
7530x018 & rate counter bit 15...0 patch 2 board 1 crate 0 \\\hline
7540x019 & rate counter bit 29...16 patch 3 board 1 crate 0 \\\hline
7550x01A & rate counter bit 15...0 patch 3 board 1 crate 0 \\\hline
7560x01B & rate counter bit 29...16 total board 1 crate 0 \\\hline
7570x01C & rate counter bit 15...0 total board 1 crate 0  \\\hline
7580x01D & Overflow register board 1 crate 0 \\\hline
7590x01E & CRC-error register board 1 crate 0 \\\hline
760... & ... \\\hline   %%%
761% \end{longtable}
762\caption{FTM dynamic data block}
763\label{tab:FTM-dynamic-data-block}
764\end{longtable}
765
766%\section{Trigger-list}
767%\label{sec:trigger-list}
768%The FTM board records all triggers in a list, the so-called trigger-list.
769%This trigger-list comprises a maximum of 50 triggers.  The first eleven words
770%are the same as in the static- and dynamic data block.  During data-taking-,
771%calibration- and trigger runs, the Trigger-list is automatically sent to the
772%main control each time the 50 triggers are reached or the run is finished. In
773%addition, the Trigger-list can also be read-out by the main control with the
774%according command.  In case the run finishes or is terminated, as well as when
775%read out manually, the trigger list might be shorter than 50 events.
776
777%% \begin{table}[h]
778%% \centering
779%\begin{longtable}[h]{|l|l|}\hline
780%address & content\\\hline\hline
781%0x000 & board ID bit 63 - 48 \\\hline
782%0x001 & board ID bit 47 - 32\\\hline
783%0x002 & board ID bit 31 - 16\\\hline
784%0x003 & board ID bit 15 - 0\\\hline
785%0x004 & firmware ID \\\hline
786%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
787%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
788%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
789%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
790%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
791%0x00A & spare \\\hline
792
793%0x00B & on-time counter at read-out time bits 47 .. 32 \\\hline
794%0x00C & on-time counter at read-out time bits 31 .. 16 \\\hline
795%0x00D & on-time counter at read-out time bits 15 .. 0 \\\hline
796
797%0x00E & 1st event Trigger-ID \\\hline
798%0x00F & 1st event Trigger-ID \\\hline
799%0x010 & 1st event Trigger-ID \\\hline
800%0x011 & 1st event Trigger primitives crate 0 \\\hline
801%0x012 & 1st event Trigger primitives crate 1 \\\hline
802%0x013 & 1st event Trigger primitives crate 2 \\\hline
803%0x014 & 1st event Trigger primitives crate 3 \\\hline
804%0x015 & 1st event Time stamp counter at trigger time bits 47 .. 32 \\\hline
805%0x016 & 1st event Time stamp counter at trigger time bits 31 .. 16 \\\hline
806%0x017 & 1st event Time stamp counter at trigger time bits 15 .. 0 \\\hline
807
808%0x018 & 2nd event Trigger-ID \\\hline
809%0x019 & 2nd event Trigger-ID \\\hline
810%0x01A & 2nd event Trigger-ID \\\hline
811%0x01B & 2nd event Trigger primitives crate 0 \\\hline
812%0x01C & 2nd event Trigger primitives crate 1 \\\hline
813%0x01D & 2nd event Trigger primitives crate 2 \\\hline
814%0x01E & 2nd event Trigger primitives crate 3 \\\hline
815%0x01F & 2nd event Time stamp counter at trigger time bits 47 .. 32 \\\hline
816%0x020 & 2nd event Time stamp counter at trigger time bits 31 .. 16 \\\hline
817%0x021 & 2nd event Time stamp counter at trigger bits 15 .. 0 \\\hline
818%... & ...\\\hline
819%0x1F8 & 50th event Trigger-ID \\\hline
820%0x1F9 & 50th event Trigger-ID \\\hline
821%0x1FA & 50th event Trigger-ID \\\hline
822%0x1FB & 50th event Trigger primitives crate 0 \\\hline
823%0x1FC & 50th event Trigger primitives crate 1 \\\hline
824%0x1FD & 50th event Trigger primitives crate 2 \\\hline
825%0x1FE & 50th event Trigger primitives crate 3 \\\hline
826%0x1FF & 50th event Time stamp counter at trigger time bits 47 .. 32 \\\hline
827%0x200 & 50th event Time stamp counter at trigger time bits 31 .. 16 \\\hline
828%0x201 & 50th event Time stamp counter at trigger bits 15 .. 0 \\\hline
829
830%% \end{longtable}
831%\caption{FTM trigger list}
832%\label{tab:FTM-trigger-list}
833%\end{longtable}
834
835\section{FTU list}
836\label{sec:FTU-List}
837When the FTM board receives the 'ping all FTUs' instruction, it sends a ping
838command to all FTU boards and gathers the FTU boards responses to a list. This
839list is called 'FTU list' and shown in table \ref{tab:FTU-list}. The FTM only
840accepts a ping when no run is ongoing (defined by the 'start run' and 'stop
841run' commands). When the FTU list is complete, it is sent back via ethernet
842with the header defined in table~\ref{tab:FTM-header}.
843
844\begin{longtable}[h]{|l|l|}\hline
845address & content\\\hline\hline
846
8470x000 & total number of responding FTU boards\\\hline
8480x001 & number of responding FTU boards belonging to crate 0 \\\hline
8490x002 & number of responding FTU boards belonging to crate 1 \\\hline
8500x003 & number of responding FTU boards belonging to crate 2 \\\hline
8510x004 & number of responding FTU boards belonging to crate 3 \\\hline
852
8530x005 & active FTU list crate 0 \\\hline
8540x006 & active FTU list crate 1 \\\hline
8550x007 & active FTU list crate 2 \\\hline
8560x008 & active FTU list crate 3 \\\hline 
857
8580x009 & address of first  FTU board and number of sent pings\\\hline
859
8600x00A & DNA of first FTU board bit 63 ... 48\\\hline
8610x00B & DNA of first FTU board bit 47 ... 32\\\hline
8620x00C & DNA of first FTU board bit 31 ... 16\\\hline
8630x00D & DNA of first FTU board bit 15 ... 0\\\hline
864
8650x00E & address of second FTU board and number of sent pings\\\hline
866
8670x00F & DNA of second FTU board bit 63 ... 48\\\hline
8680x010 & DNA of second FTU board bit 47 ... 32\\\hline
8690x011 & DNA of second FTU board bit 31 ... 16\\\hline
8700x012 & DNA of second FTU board bit 15 ... 0\\\hline
871... & ...\\\hline
872\caption{FTU list}
873\label{tab:FTU-list}
874\end{longtable}
875
876
877
878Because there are four connectors for the RS-485 buses, one for each crate,
879there will be a full scan for all addresses on every connector.  In case there
880is no response to a 'ping' on a certain address, there will be up to two
881repetitions. A responding FTU board will get an entry into the FTU list (table
882\ref{tab:FTU-list}) including the number of 'ping' sent until response.
883The number of pings is coded together with the FTU board address as shown in table
884\ref{tab:FTU-crate-number-and-address}.
885The two bits 'pings\_0' and 'pings\_1' contain the number
886of 'pings' until response of an FTU board coded in binary.
887The 'DNA' of the FTU board is the device DNA \cite{ds557, ds610, wp267, wp266} 
888of the FPGA on the responding FTU board. This is a unique 57 bit serial number
889unambiguously identifying every Xilinx FPGA. In the most significant word (bit
89063 ... 48) bits 63 down to 57 are filled with zeros.
891
892
893\begin{table}[h]
894\centering
895\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
896Bit      & 15 ... 10 & 9 & 8 & 7 & 6 & 5 & ... & 0 \\\hline
897
898Content & x ... x & pings\_1 & pings\_0 & x & x & A5 & ... & A0 \\\hline
899\end{tabular}
900\caption{Crate number and address of first responding FTU board}
901\label{tab:FTU-crate-number-and-address}
902\end{table}
903
904\chapter{FTU communication error handling}
905\label{cha:Error-handling}
906
907When the FTM board is communicating with a FTU board via RS-485, the FTU board
908has to respond within 5 ms. If this timeout expires, or the response sent back
909by the FTU board is incorrect, the FTM resends the datapacket after the
910timeout. If this second attempt is still unsuccessful, a third and last
911attempt will be made by the FTM board. An error message will be sent to the
912central control whenever a FTU board does not send a correct answer after the
913first call by the FTM board. This message (see table~\ref{tab:error-message})
914contains, after the standard header (see table~\ref{tab:FTM-header}), the
915number of unsuccessful calls and the data packet sent to the FTU board in
916these unsuccessful calls. In order to avoid massive error messages for
917e.g. test setups with single FTUs, the 'active FTU list' can be employed to
918disable FTUs from the bus. In that case the FTM will not try to contact the
919corresponding boards.
920
921\begin{table}[h]
922  \centering
923  \begin{tabular}{|l|l|}\hline
924    word no & content\\\hline\hline
925    0x000 & board ID bits 63...48 \\\hline
926    0x001 & board ID bits 47...32\\\hline
927    0x002 & board ID bits 31...16\\\hline
928    0x003 & board ID bits 15...0\\\hline
929    0x004 & firmware ID \\\hline
930    0x005 & Trigger counter at read-out time bits 31...16 \\\hline
931    0x006 & Trigger counter at read-out time bits 15...0\\\hline
932    0x007 & Time stamp counter at read-out time bits 47...32 \\\hline
933    0x008 & Time stamp counter at read-out time bits 31...16 \\\hline
934    0x009 & Time stamp counter at read-out time bits 15...0 \\\hline
935    0x00A & spare \\\hline
936    0x00B & number of unsuccessful calls\\\hline
937    0x00C ... 0x027 & slow control data packet sent to FTU (28 byte)\\\hline
938  \end{tabular}
939  \caption{FTU communication error message}
940  \label{tab:error-message}
941\end{table}
942
943%---------------------------------------------------------------------------------
944
945\bibliographystyle{unsrt}
946%\bibliography{FTM-Com}
947
948\begin{thebibliography}{1}
949
950\bibitem{DRS4}
951Paul Scherrer Institut PSI.
952\newblock {\em DRS4 9 Channel, 5 GSPS Switched Capacitor Array}.
953\newblock datasheet.
954
955\bibitem{LMK03000}
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958  VCO}, 2008.
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965\bibitem{W5300}
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988\bibitem{MAX6662}
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998\end{thebibliography}
999
1000\end{document}
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