source: firmware/FTM/doc/v3.1/FTM_firmware_specs_v3-1.tex@ 14751

\documentclass[a4paper,11pt]{report}

\usepackage{float}
\usepackage{graphicx}
\usepackage{url}
\usepackage[T1]{fontenc}
\usepackage{amsmath}
\usepackage{longtable}
\usepackage{parskip}
\usepackage{pifont}
\usepackage{array}

\setlength{\oddsidemargin}{0cm}
\setlength{\evensidemargin}{0cm}
\setlength{\topmargin}{0cm}

\textwidth 6.2in
\textheight 9in
\columnsep 0.25in

\pagestyle{plain}
\setcounter{tocdepth}{1}

\title{\vspace*{-7cm} \Huge \bf FTM Firmware Specifications}
\author{\Large Patrick Vogler\footnote{Contact for questions and suggestions concerning this
    document: {\tt patrick.vogler@phys.ethz.ch}}, Quirin Weitzel}
\date{\vspace*{0.5cm} \Large v3.1~~~-~~~February 2011}

\begin{document}

\maketitle

\newpage

\tableofcontents

%---------------------------------------------------------------------------------

\chapter{Introduction}
\label{cha:Introduction}

The FTM (FACT Trigger Master) board collects the trigger primitives from all
40 FTU boards (FACT Trigger Unit) and generates the trigger signal for the
FACT camera. The trigger logic is a 'n-out-of-40' majority coincidence of all
trigger primitives. Beside the trigger, the FTM board also generates a
trigger-ID (see chapter \ref{cha:Trigger-ID}). It is controlled by the main
control software via ethernet. Two auxiliary RS-485 interfaces are also
available.

In addition to the trigger, the FTM board also generates the other fast
control signals: Time-Marker (TIM), DRS \cite{DRS4} reference clock (CLD) and
reset. These four fast control signals are distributed to the FAD (FACT Analog
to Digital) boards via the two FFC (FACT Fast Control) boards. The FTM board
also provides via the TIM line the signal for the DRS timing calibration. In
order to generate the CLD DRS reference clock, as well as the time-marker
signal for DRS timing calibration, the FTM board uses a clock conditioner
\cite{LMK03000}.

The FTM board has two counters, the 'timestamp counter' and the 'on-time
counter'. While the 'timestamp counter' runs continously (counting up,
resetted by e.g. a 'start run'), the 'on-time counter' only counts when the
camera trigger is enabled.

The FTM board further serves as slow control master for the 40 FTU boards. The
slow control of the FTU boards and the distribution of the trigger-ID to the
FAD boards are performed via dedicated RS-485 buses. Because the FAD as well
as the FTU boards are arranged in crates of 10 boards each, the FTM board has
four connectors, one for each crate. Running over these connectors there are
two RS-485 buses (one for FTU slow control and one for the trigger-ID) besides
the busy signal from the FAD boards and the crate reset.

In addition, the FTM board controls the two FLPs (FACT Light Pulser) via four
LVDS signals each. Light pulser~1 is located in the mirror dish, light
pulser~2 inside the camera shutter. There are also digital auxiliary in- and
outputs according to the NIM (Nuclear Instrumentation Module) standard, for
example for external triggers and veto, and to have the signals accessible.

The main component of the FTM board is a FPGA (Xilinx Spartan
XC3SD3400A-4FGG676C), fulfilling the main functions within the board. The
purpose of this document is to provide specifications needed for the
development of the firmware of this FPGA and the software (called 'main
control' in the following) controlling the FTM board. For further information
about the FTM board hardware please refer to \cite{FTM-Schematics}.

\chapter{Trigger-ID}
\label{cha:Trigger-ID}

For each processed trigger the FTM board generates a unique trigger-ID to be
broadcasted to all FAD boards and added to the event data. This trigger-ID
consists of a 32 bit trigger number, a two byte trigger type indicator and a
checksum. The transmission protocol for the trigger-ID broadcast is shown in
table \ref{tab:Trigger-ID broadcast}.

\begin{table}[htbp]
\centering
\begin{tabular}{|l|l|}\hline
byte no & content\\\hline\hline
0 & Trigger-No first byte (least significant byte) \\\hline
1 & Trigger-No second byte\\\hline
2 & Trigger-No third byte\\\hline
3 & Trigger-No forth byte (most significant byte)\\\hline
4 & Trigger-Type 1\\\hline
5 & Trigger-Type 2\\\hline
6 & CRC-8-CCITT (checksum)\\\hline
\end{tabular}
\caption{The transmission protocol to broadcast the trigger-ID to the FAD boards}
\label{tab:Trigger-ID broadcast}
\end{table}

A Cyclic Redundancy Check (CRC) over byte 0 - 5 is used to evaluate the
integrity of the trigger-ID. An 8-CCITT CRC has been chosen which is based on
the polynomial $x^8 + x^2 + x + 1$ (00000111, omitting the most significant
bit). The resulting 1-byte checksum comprises the last byte of the trigger-ID.
The transmission of the trigger-ID to the FAD boards is done by means of
dedicated RS-485 buses (one per crate).

In the first byte of the trigger type indicator (see table
\ref{tab:Trigger-Type 1}) n0 - n5 indicate the number of trigger primitives
required for a trigger, thus the 'n' of the 'n-out-of-40' majority
coincidence. The two flags 'external trigger 1' and 'external trigger 2',
when set, indicate a trigger from the corresponding NIM inputs. See also
section \ref{sec:Static-data-block} and table \ref{tab:FTM-majority} for
further information.

\begin{table}[htbp]
\centering
%\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
  Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
  n5 & n4 & n3 & n2 & n1 & n0 & external trigger 2 & external trigger 1\\\hline
\end{tabular}
%\end{small}
\caption{Trigger-Type 1}
\label{tab:Trigger-Type 1}
\end{table}

\begin{table}[htbp]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
TIM source & LP\_set\_3 & LP\_set\_2 & LP\_set\_1 & LP\_set\_0 & pedestal & LP\_2 & LP\_1\\\hline
\end{tabular}
\end{small}
\caption{Trigger-Type 2}
\label{tab:Trigger-Type 2}
\end{table}

The 'TIM source' bit in 'Trigger-Type 2' (see table \ref{tab:Trigger-Type 2})
indicates the source of the timemarker signal: a '0' indicates the timemarker
being produced in the FPGA while a '1' indicates the timemarker coming from
the clock conditioner. The flags 'LP\_1' and 'LP\_2' are set when the
corresponding lightpulser has flashed while the 'pedestal' flag is set in case
of a pedestal (random) trigger. An event having none of these flags set
indicates a physics event. The bits 'LP\_set\_0' to 'LP\_set\_3' are used to
code information about the light pulser settings. They only have a meaning in
case of calibration events.

\chapter{FTM Commands}
\label{cha:FTM-Commands}

The communication between the FTM board and the main control, including the
corresponding commands, protocols and data, is based on 16-bit words and
big-endian. This is to facilitate the data-transmission over the Wiznet W5300
ethernet interface \cite{W5300}.

The basic structure of all commands is the same and given in table
\ref{tab:FTM-command-structure}. After a start delimiter, the second word
identifies the command. Next there is a parameter further refining the
command, e.g. what to read. The fourth and fifth words are spares and should
contain zeros. Starting from the sixth word, an optional data block of
variable size is following. This data block differs in length and content
depending on command and parameter. In case of 'read' instructions, the
corresponding data block is sent back.

%The FTM board must answer every command by sending back the appropriate data
%block or by simply sending back the instruction where there is no datablock to
%be sent back.  All 'read' commands to the FTM board do not contain any data
%blocks, but the FTM boards response does.  In case of 'read' and 'write'
%instructions, the datablock is to be sent back. When 'start run' or 'stop run'
%commands are used, the FTM board 'mirrors' them, i.e. sends them back for
%confirmation.

\begin{table}[p]
\centering
\begin{tabular}{|l|l|}\hline
  word no & content\\\hline\hline
  0 & start delimiter (e.g. '@') \\\hline
  1 & command ID \\\hline
  2 & command parameter \\\hline
  3 & spare: containing 0x0000\\\hline
  4 & spare: containing 0x0000 \\\hline
  5 & data block (optional and of variable size)\\\hline
  ... & ...\\\hline
  X & data block\\\hline
\end{tabular}
\caption{FTM command structure}
\label{tab:FTM-command-structure}
\end{table}

So far six different commands are foreseen: 'read', 'write', 'start run',
'stop run', 'ping FTUs' and 'crate reset' (see table
\ref{tab:FTM-command-ID}). The command parameters of the 'read' command are
shown in table~\ref{tab:FTM-read-command-param}. For the 'write' command there
is no option because the static data block is the only data that can be
written to the FTM board.

\begin{table}[p]
\centering
\begin{tabular}{|r|r|}\hline
  command-ID: bits & \\\cline{1-1}
  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command\\\hline\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read \\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & write \\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start run / take X events\\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & stop run \\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 & ping all FTUs \\\hline
  0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & crate reset \\\hline
\end{tabular}
\caption{FTM command ID listing}
\label{tab:FTM-command-ID}
\end{table}

\begin{table}[p]
\centering
\begin{tabular}{|r|r|r|}\hline
  command parameter: bits & & \\\cline{1-1}
  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read static data block & no\\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & read dynamic data block & no\\\hline
  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & read trigger list & no\\\hline
\end{tabular}
\caption{Command parameters for the 'read' command}
\label{tab:FTM-read-command-param}
\end{table}

%\begin{table}[htbp]
%\centering
%\begin{tabular}{|r|r|r|}\hline
%  command parameter: bits & & \\\cline{1-1}
%  15 ... 8  \vline 7  \vline 6  \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
%  0 \vline 0 \vline 0 \vline 0 \vline 0  \vline0 \vline 0  \vline0  \vline1 & write static data & static data block\\\hline
%\end{tabular}
%\caption{Command parameters for the 'write' command}
%\label{tab:FTM-write-command-param}
%\end{table}

In table \ref{tab:FTM-start-command-param} the parameters to start a run are
listed. The type of the run is fully described in the FTM configuration
(static data block, see section~\ref{sec:Static-data-block}), which always has
to be sent by the main control before starting a run. Therefore the only
option is to start an "endless" run or to take X events instead. In the latter
case X is defined by a two words (32 bit) long unsigned integer, making up the
command data block. The 'start run' command enables the transmission of
trigger signals (physics, calibration or pedestal) to the FAD boards and
resets the trigger and time counters. There is no parameter for stopping a
run. If a number of events has been specified ('take X events'), the run will
terminate if either the 'stop run' command is received or the requested number
of events is reached.

When a run is stopped, either by the 'stop run' command or when the specified number
of events is taken, the trigger and time counters are reset, too.



\begin{table}[p]
\centering
\begin{tabular}{|r|r|r|}\hline
  command parameter: bits & & \\\cline{1-1}
  15 ... 8  \vline7  \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & start run & no \\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & take X events & number of events X \\\hline
  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start taking pedestals & no \\\hline
  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 1 & take X pedestals events & number of events X \\\hline
  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & start calibration run & no \\\hline
  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 1 & take X calibration events & number of events X \\\hline
\end{tabular}
\caption{Command parameters for the 'start run' command: "start run" means an "endless" run, i.e. no prespecified number of events.}
\label{tab:FTM-start-command-param}
\end{table}

%\begin{table}[htbp]
%\centering
%\begin{tabular}{|r|r|r|}\hline
%  command parameter: bits & & \\\cline{1-1}
%  15 ... 8  \vline 7 \vline 6 \vline 5 \vline 4  \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
%  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & stop run & no\\\hline
%\end{tabular}
%\caption{Command parameter for the 'stop run' command}
%\label{tab:FTM-stop-command-param}
%\end{table}

In case of a 'ping FTUs' command the FTM will address the FTUs one by one and
readout their DNA. The results are collected in the FTU list (see section
\ref{sec:FTU-List}), which is sent back to the main control. There are no
parameters for this command. With the 'crate reset' command the boards of a
particular crate can be rebooted, where the command parameter defines the
crate number (see table \ref{tab:FTM-reset-command-param}). Only one crate
reset at a time is possible, i.e. the FTM firmware does not allow to reset
multiple crates in one command.

\begin{table}[p]
\centering
\begin{tabular}{|r|r|r|}\hline
  command parameter: bits & & \\\cline{1-1}
  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reset crate 0 & no\\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & reset crate 1 & no\\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & reset crate 2 & no\\\hline
  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & reset crate 3 & no\\\hline
\end{tabular}
\caption{Command parameters for the 'crate reset' command: the command parameter may only contain a single "1"
         corresponding to only one crate reset at a time.}
\label{tab:FTM-reset-command-param}
\end{table}

\chapter{FTM data blocks}
\label{cha:FTM-data-block}

The trigger master features two main data blocks, named 'static data block'
and 'dynamic data block' in the following. They are implemented in the
firmware as block-RAM. In addition, there is the so-called 'FTU list', which
is generated only on request ('ping FTUs' command). If any of these blocks is
sent to the main control (either automatically or on demand), a header with a
size of eleven words is added. This header is identical for all data blocks
and contains solely read-only information: the FTM board ID (57-bit Xilinx
device DNA \cite{ds557, ds610, wp267, wp266}), a firmware ID and the readings
of the trigger counter and time stamp counter. The header structure is
summarized in table~\ref{tab:FTM-header}.

\begin{table}[h]
\centering
\begin{tabular}{|l|l|}\hline
  word no & content\\\hline\hline
  0x000 & board ID bits 63...48 \\\hline
  0x001 & board ID bits 47...32\\\hline
  0x002 & board ID bits 31...16\\\hline
  0x003 & board ID bits 15...0\\\hline
  0x004 & firmware ID \\\hline
  0x005 & Trigger counter at read-out time bits 31...16 \\\hline
  0x006 & Trigger counter at read-out time bits 15...0\\\hline
  0x007 & Time stamp counter at read-out time bits 47...32 \\\hline
  0x008 & Time stamp counter at read-out time bits 31...16 \\\hline
  0x009 & Time stamp counter at read-out time bits 15...0 \\\hline
  0x00A & spare \\\hline
\end{tabular}
\caption{Header structure for sending a data block}
\label{tab:FTM-header}
\end{table}

\section{Static data block}
\label{sec:Static-data-block}

The static data block contains all the settings needed to configure and
operate the FTM. It has to be written by the main control each time before a
run is started or, in general, some component has to be reprogrammed. Single
register access is not foreseen for the moment. In addition, whenever the FTM
board receives a new static data block, it performs a complete reconfiguration
including a reprogramming of the
FTUs. Table~\ref{tab:FTM-trigger-master-static-data-block} summarizes the
static data block. More details about the individual registers can be found in
the subsequent tables.

%These settings are readable and writable by the main control using the
%corresponding commands 'read static data block' or 'write static data block',
%respectively.  There is one exception from writability: In case the static
%data block is read back, the first eleven words (address 0..A) are identical
%with the dynamic data block and the trigger list shown in
%\ref{tab:FTM-trigger-master-dynamic-data-block} and
%\ref{tab:FTM-trigger-list}.  These first eleven words can only be read and not
%written.  The board ID is supposed to be the Xilinx device DNA \cite{ds557,
%  ds610, wp267, wp266}, the 57 bit device ID of the FPGA.  When using the
%'write static data block' command, the static data block must start with the
%'general settings register' at address 0x00B. So there is an offset in the
%addresses of 0x00B between the 'read-out-version' and the 'write-version' of
%the static data block.

\begin{longtable}[h]{|l|l|}\hline
\centering
word no & content\\\hline\hline
%0x000 & board ID bit 63 - 48 \\\hline
%0x001 & board ID bit 47 - 32\\\hline
%0x002 & board ID bit 31 - 16\\\hline
%0x003 & board ID bit 15 - 0\\\hline
%0x004 & firmware ID \\\hline
%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
%0x00A & spare \\\hline
0x000 & general settings\\\hline
0x001 & on-board status LEDs\\\hline
0x002 & light pulser and pedestal trigger frequency\\\hline
0x003 & ratio between LP1, LP2 and pedestal triggers\\\hline
0x004 & light pulser 1 amplitude\\\hline
0x005 & light pulser 2 amplitude\\\hline
0x006 & light pulser 1 delay\\\hline
0x007 & light pulser 2 delay\\\hline
0x008 & majority coincidence n (for physics)\\\hline
0x009 & majority coincidence n (for calibration)\\\hline
0x00A & trigger delay\\\hline
0x00B & timemarker delay\\\hline
0x00C & dead time\\\hline
0x00D & clock conditioner R0 bits 31...16 \\\hline
0x00E & clock conditioner R0 bits 15...0 \\\hline
0x00F & clock conditioner R1 bits 31...16 \\\hline
0x010 & clock conditioner R1 bits 15...0 \\\hline
0x011 & clock conditioner R8 bits 31...16 \\\hline
0x012 & clock conditioner R8 bits 15...0 \\\hline
0x013 & clock conditioner R9 bits 31...16 \\\hline
0x014 & clock conditioner R9 bits 15...0 \\\hline
0x015 & clock conditioner R11 bits 31...16 \\\hline
0x016 & clock conditioner R11 bits 15...0 \\\hline
0x017 & clock conditioner R13 bits 31...16 \\\hline
0x018 & clock conditioner R13 bits 15...0 \\\hline
0x019 & clock conditioner R14 bits 31...16 \\\hline
0x01A & clock conditioner R14 bits 15...0 \\\hline
0x01B & clock conditioner R15 bits 31...16 \\\hline
0x01C & clock conditioner R15 bits 15...0 \\\hline
0x01D & spare \\\hline
0x01E & spare \\\hline
0x01F & spare \\\hline
0x020 & enables patch 0 board 0 crate 0 \\\hline
0x021 & enables patch 1 board 0 crate 0 \\\hline
0x022 & enables patch 2 board 0 crate 0 \\\hline
0x023 & enables patch 3 board 0 crate 0 \\\hline
0x024 & DAC$\_$A board 0 crate 0 \\\hline
0x025 & DAC$\_$B board 0 crate 0 \\\hline
0x026 & DAC$\_$C board 0 crate 0 \\\hline
0x027 & DAC$\_$D board 0 crate 0 \\\hline
0x028 & DAC$\_$H board 0 crate 0 \\\hline
0x029 & Prescaling board 0 crate 0 \\\hline
0x02A & enables patch 0 board 1 crate 0 \\\hline
0x02B & enables patch 1 board 1 crate 0 \\\hline
0x02C & enables patch 2 board 1 crate 0 \\\hline
0x02D & enables patch 3 board 1 crate 0 \\\hline
0x02E & DAC$\_$A board 1 crate 0 \\\hline
0x02F & DAC$\_$B board 1 crate 0 \\\hline
0x030 & DAC$\_$C board 1 crate 0 \\\hline
0x031 & DAC$\_$D board 1 crate 0 \\\hline
0x032 & DAC$\_$H board 1 crate 0 \\\hline
0x033 & Prescaling board 1 crate 0 \\\hline
... & ... \\\hline
0x1A6 & enables patch 0 board 9 crate 3 \\\hline
0x1A7 & enables patch 1 board 9 crate 3 \\\hline
0x1A8 & enables patch 2 board 9 crate 3 \\\hline
0x1A9 & enables patch 3 board 9 crate 3 \\\hline
0x1AA & DAC$\_$A board 9 crate 3 \\\hline
0x1AB & DAC$\_$B board 9 crate 3 \\\hline
0x1AC & DAC$\_$C board 9 crate 3 \\\hline
0x1AD & DAC$\_$D board 9 crate 3 \\\hline
0x1AE & DAC$\_$H board 9 crate 3 \\\hline
0x1AF & Prescaling board 9 crate 3 \\\hline
0x1B0 & active FTU list crate 0 \\\hline
0x1B1 & active FTU list crate 1 \\\hline
0x1B2 & active FTU list crate 2 \\\hline
0x1B3 & active FTU list crate 3 \\\hline 
\caption{Overview of the FTM static data block}
\label{tab:FTM-trigger-master-static-data-block}
\end{longtable}

The FTM general settings register is detailed in table
\ref{tab:FTM-general-settings-register}. The 'TIM\_CLK' bit defines whether
the time marker is generated by the FPGA ('TIM\_CLK' = 0, default for physics
data taking), or whether it is generated by the clock conditioner ('TIM\_CLK'
= 1, e.g. for DRS timing calibration). The 'ext\_veto', 'ext\_trig\_1' and
'ext\_trig\_2' bits enable (1) or disable (0) the NIM inputs for the external
veto and trigger signals, respectively. In order to select which trigger
sources are active during a run, the bits 'LP1', 'LP2', 'ped' and 'trigger'
are foreseen (0 disabled, 1 enabled). During a physics run, for example,
'LP1', 'ped' and 'trigger' should all be set to generate interleaved
calibration and pedestal events as well as activate the 'n-out-of-40' trigger
input. For a didicated pedestal run only 'ped' should be set, since in this
case the FTM sends directly a trigger to the FADs. For calibration runs it
depends on whether the external (LP1) or internal (LP2) light pulser is used:
For the first case 'LP1' and 'trigger' have to be set, since here the full
trigger chain is involved and the camera triggers based on G-APD signals. For
the second case only 'LP2' is needed, because the shutter is closed and the
FTM sends directly the trigger signal to the FADs (like for pedestal
events). Bits 8 to 15 of the general settings register are not used up to now.

\begin{table}[h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
Bit & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
Content & x & trigger & ped & LP2 & LP1 & ext\_trig\_2 & ext\_trig\_1& ext\_veto & TIM\_CLK \\\hline
\end{tabular}
\end{small}
\caption{FTM general settings register}
\label{tab:FTM-general-settings-register}
\end{table}

%\begin{table}[!h]
%\centering
%\begin{tabular}{|l|l|}\hline
%TIM\_CClk & description \\\hline\hline
%0 & Time marker generated in the FPGA \\\hline
%1 & Time marker generated by the clock conditioner \\\hline
%\end{tabular}
%\caption{FTM Time marker indication}
%\label{tab:FTM-Time-marker-indication}
%\end{table}

%\begin{table}[!h]
%\centering
%\begin{tabular}{|l|l|}\hline
%ena$\_$ext$\_$Veto  & description \\\hline\hline
%0 & disable external trigger veto\\\hline
%1 & enable external trigger veto \\\hline
%\end{tabular}
%\caption{FTM external trigger}
%\label{tab:FTM-external-trigger}
%\end{table}

%\begin{table}[!h]
%\centering
%\begin{tabular}{|l||l|}\hline
%ena\_LP1  & description \\\hline\hline
%0 & disable light pulser 1 \\\hline
%1 & enable light pulser 1\\\hline
%\end{tabular}
%\caption{FTM light pulser 1}
%\label{tab:FTM-light-pulser-1}
%\end{table}

%\begin{table}[!h]
%\centering
%\begin{tabular}{|l||l|}\hline
%ena\_LP2  & description \\\hline\hline
%0 & disable light pulser 2 \\\hline
%1 & enable light pulser 2 \\\hline
%\end{tabular}
%\caption{FTM light pulser 2}
%\label{tab:FTM-light-pulser-2}
%\end{table}

%\begin{table}[!h]
%\centering
%\begin{tabular}{|l||l|}\hline
%ena\_Ped  & description \\\hline\hline
%0 & disable interleaved pedestal trigger \\\hline
%1 & enable interleaved pedestal trigger \\\hline
%\end{tabular}
%\caption{FTM interleaved pedestals}
%\label{tab:FTM-interleaved-pedestals}
%\end{table}

%\begin{table}[!h]
%\centering
%\begin{small}
%\begin{tabular}{|l||l|}\hline
%ena\_LLC  & description \\\hline\hline
%0 & disable low level calibration pulses \\\hline
%1 & enable low level calibration pulses \\\hline
%\end{tabular}
%\end{small}
%\caption{FTM low level calibration pulses}
%\label{tab:FTM-low-level-calibration-pulses}
%\end{table}

The 'on-board status LEDs' register shown in table \ref{tab:FTM-LED-register}
allows to switch a total of eight LEDs on the FTM board for debugging purposes
by setting the corresponding bit high.

\begin{table}[h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
Bit      & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
Content &  x & red$\_$3 & red$\_$2 & gn$\_$1 & ye$\_$1 & red$\_$1 & gn$\_$0 & ye$\_$0 & red$\_$0 \\\hline
\end{tabular}
\end{small}
\caption{'on-board status LEDs' register}
\label{tab:FTM-LED-register}
\end{table}

The frequency, with which light pulser and pedestal triggers are sent, is
stored in the register at address 0x002 (see table
\ref{tab:FTM-frequency-register}). It is given in Hz and adjustable up to
about 1\,kHz (10 bit). The next register defines the ratio of LP1, LP2 and
pedestal events (see table \ref{tab:FTM-ratio-register}).
 
\begin{table}[h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
Bit      & 15 - 10 & 9 & 8 & ... & 2 & 1 & 0 \\\hline
Content &  x  & FREQ\_9 & FREQ\_8 & ... & FREQ\_2 & FREQ\_1 & FREQ\_0 \\\hline
\end{tabular}
\end{small}
\caption{Register for the frequency of calibration and pedestal events}
\label{tab:FTM-frequency-register}
\end{table}

\begin{table}[h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|}\hline
Bit      & 15 - 12 & 11 & ... & 8 & 7 & ... & 4 & 3 & ... & 0 \\\hline
Content & x & ped\_R3 & ... & ped\_R0 & LP2\_R3 & ... & LP2\_R0 & LP1\_R3 & ... & LP1\_R0 \\\hline
\end{tabular}
\end{small}
\caption{Register defining the ratio between pedestal, LP1 and LP2 events}
\label{tab:FTM-ratio-register}
\end{table}

%\begin{table}[!h]
%\centering
%\begin{tiny}
%\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
%Bit      & 15 - 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
%Function &  x  & LPR2\_9 & LPR2\_8 & LPR2\_7 & LPR2\_6 & LPR2\_5 & LPR2\_4 & LPR2\_3 & LPR2\_2 & LPR2\_1 & LPR2\_0 \\\hline
%\end{tabular}
%\end{tiny}
%\caption{Light pulser 2 frequency register at address 0x00E: This register contains the pulse rate of the light
%               pulser 2 in Hz.}
%\label{tab:Light-pulser-2-frequancy-register}
%\end{table}

In order to define the amplitude and characteristics of the light pulses that
are generated by the LP1 and the LP2 system, the registers 'LP1 amplitude' and
'LP2 amplitude' are used, respectively. These registers are presented in
table~\ref{tab:LP1-amplitude-register} and
table~\ref{tab:LP2-amplitude-register}. In general the light pulser systems
are controlled from the FTM by means of four control lines: The first line
defines the amplitude of the calibration events by sending a gate/pulse with
an adjustable length (bits 0 to 3 in the amplitude registers). With the second
and third line additional LEDs can be switched on in the calibration systems
(bits 13 and 14). The fourth line is used to overdrive the LP systems and to
generate a very fast timing pulse. To do so, bit 15 has to be set to 1.

\begin{table}[!h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
Bit      & 15 & 14 & 13 & 12...4 & 3 & ... & 0 \\\hline
Content & FCP1 &  add\_LEDs1\_1& add\_LEDs1\_0 & x & LP1A\_3 & ... & LP1A\_0 \\\hline
\end{tabular}
\end{small}
\caption{Light pulser 1 amplitude register}
\label{tab:LP1-amplitude-register}
\end{table}

\begin{table}[!h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
Bit      & 15 & 14 & 13 & 12...4 & 3 & ... & 0 \\\hline
Content & FCP2 & add\_LEDs2\_1 & add\_LEDs2\_0 & x & LP2A\_3 & ... & LP2A\_0 \\\hline
\end{tabular}
\end{small}
\caption{Light pulser 2 amplitude register}
\label{tab:LP2-amplitude-register}
\end{table}

The different settings of the 'n-out-of-40' logic (physics or calibration
events) are stored in two separate registers, which both have a structure
according to table~\ref{tab:FTM-majority}.

\begin{table}[!h]
\centering
\begin{small}
\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
Bit      & 15...6 & 5 & 4 & 3 & 2 &1 & 0 \\\hline
Content & x & n5 & n4 & n3 & n2 & n1 & n0 \\\hline
\end{tabular}
\end{small}
\caption{Structure of the two majority coincidence (n-out-of-40) registers; the binary value
                in these registers is the number n of FTU trigger primitives required to trigger an event (physics or calibration)}
\label{tab:FTM-majority}
\end{table}

In addtion, there are several registers in the static data block to define
delays (e.g. for the trigger). Also a general dead time to be applied after
each trigger can be set (to compensate for the delay of the busy line). The
clock conditioner settings are specified at address 0x00D to 0x01C (LMK03000
from National Semiconductor, for more details see \cite{LMK03000}). Starting
at address 0x020, the FTU settings are stored. The FTM always holds the
complete FTU parameters in the static data block. For the meaning of these
registers, please refer to the FTU firmware specifications document
\cite{FTUspecs}.
In case not all FTUs are connected during e.g. the testing
phase, or a FTU is broken, the 'active FTU list' registers can be used to
disable certain boards.

The bits 9 ... 0 of the active FTU list (address 0x1B0 to 0x1B3, corresponding 
to crate 0 to 3) contain the "active" flag for every FTU board. Setting a
bit activates the corresponding FTU board while a "0" deactivates it.







\section{Dynamic data block}
\label{sec:Dynamic-data-block}
The dynamic data block shown in table \ref{tab:FTM-dynamic-data-block}
contains permanently updated data stored inside the FTM FPGA. It contains the
actual on-time counter reading, the board temperatures and the trigger rates
measured by the FTUs. This data block is updated and sent periodically by the
FTM. Thus the main control software receives periodically a corresponding data
package via ethernet.
The counting interval of the FTU board 0 on crate 0
('prescaling' register) defines the period. The on-board 12-bit temperature
sensors are MAX6662 chips from Maxim Products. For more information about
these components and their data see \cite{MAX6662}. When sending the dynamic
data block, the header defined in table~\ref{tab:FTM-header} is added at the
beginning.

% \begin{table}[h]
%  \centering
\begin{longtable}[h]{|l|l|}\hline
word no & content\\\hline\hline
%0x000 & board ID bit 63 - 48 \\\hline
%0x001 & board ID bit 47 - 32\\\hline
%0x002 & board ID bit 31 - 16\\\hline
%0x003 & board ID bit 15 - 0\\\hline
%0x004 & firmware ID \\\hline
%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
%0x00A & spare \\\hline

0x000 & on-time counter at read-out time bits 47...32 \\\hline
0x001 & on-time counter at read-out time bits 31...16 \\\hline
0x002 & on-time counter at read-out time bits 15...0 \\\hline
0x003 & temperature sensor 0: component U45 on the FTM schematics \cite{FTM-Schematics}\\\hline
0x004 & temperature sensor 1: U46 \\\hline
0x005 & temperature sensor 2: U48 \\\hline
0x006 & temperature sensor 3: U49 \\\hline
0x007 & rate counter bit 29...16 patch 0 board 0 crate 0 \\\hline
0x008 & rate counter bit 15...0 patch 0 board 0 crate 0 \\\hline
0x009 & rate counter bit 29...16 patch 1 board 0 crate 0 \\\hline
0x00A & rate counter bit 15...0 patch 1 board 0 crate 0 \\\hline
0x00B & rate counter bit 29...16 patch 2 board 0 crate 0 \\\hline
0x00C & rate counter bit 15...0 patch 2 board 0 crate 0 \\\hline
0x00D & rate counter bit 29...16 patch 3 board 0 crate 0 \\\hline
0x00E & rate counter bit 15...0 patch 3 board 0 crate 0 \\\hline
0x00F & rate counter bit 29...16 total board 0 crate 0 \\\hline
0x010 & rate counter bit 15...0 total board 0 crate 0\\\hline
0x011 & Overflow register board 0 crate 0 \\\hline
0x012 & CRC-error register board 0 crate 0 \\\hline
0x013 & rate counter bit 29...16 patch 0 board 1 crate 0 \\\hline
0x014 & rate counter bit 15...0 patch 0 board 1 crate 0 \\\hline
0x015 & rate counter bit 29...16 patch 1 board 1 crate 0 \\\hline
0x016 & rate counter bit 15...0 patch 1 board 1 crate 0 \\\hline
0x017 & rate counter bit 29...16 patch 2 board 1 crate 0 \\\hline
0x018 & rate counter bit 15...0 patch 2 board 1 crate 0 \\\hline
0x019 & rate counter bit 29...16 patch 3 board 1 crate 0 \\\hline
0x01A & rate counter bit 15...0 patch 3 board 1 crate 0 \\\hline
0x01B & rate counter bit 29...16 total board 1 crate 0 \\\hline
0x01C & rate counter bit 15...0 total board 1 crate 0  \\\hline
0x01D & Overflow register board 1 crate 0 \\\hline
0x01E & CRC-error register board 1 crate 0 \\\hline
... & ... \\\hline   %%%
% \end{longtable}
\caption{FTM dynamic data block}
\label{tab:FTM-dynamic-data-block}
\end{longtable}

%\section{Trigger-list}
%\label{sec:trigger-list}
%The FTM board records all triggers in a list, the so-called trigger-list.
%This trigger-list comprises a maximum of 50 triggers.  The first eleven words
%are the same as in the static- and dynamic data block.  During data-taking-,
%calibration- and trigger runs, the Trigger-list is automatically sent to the
%main control each time the 50 triggers are reached or the run is finished. In
%addition, the Trigger-list can also be read-out by the main control with the
%according command.  In case the run finishes or is terminated, as well as when
%read out manually, the trigger list might be shorter than 50 events.

%% \begin{table}[h]
%% \centering
%\begin{longtable}[h]{|l|l|}\hline
%address & content\\\hline\hline
%0x000 & board ID bit 63 - 48 \\\hline
%0x001 & board ID bit 47 - 32\\\hline
%0x002 & board ID bit 31 - 16\\\hline
%0x003 & board ID bit 15 - 0\\\hline
%0x004 & firmware ID \\\hline
%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
%0x00A & spare \\\hline

%0x00B & on-time counter at read-out time bits 47 .. 32 \\\hline
%0x00C & on-time counter at read-out time bits 31 .. 16 \\\hline
%0x00D & on-time counter at read-out time bits 15 .. 0 \\\hline

%0x00E & 1st event Trigger-ID \\\hline
%0x00F & 1st event Trigger-ID \\\hline
%0x010 & 1st event Trigger-ID \\\hline
%0x011 & 1st event Trigger primitives crate 0 \\\hline
%0x012 & 1st event Trigger primitives crate 1 \\\hline
%0x013 & 1st event Trigger primitives crate 2 \\\hline
%0x014 & 1st event Trigger primitives crate 3 \\\hline
%0x015 & 1st event Time stamp counter at trigger time bits 47 .. 32 \\\hline
%0x016 & 1st event Time stamp counter at trigger time bits 31 .. 16 \\\hline
%0x017 & 1st event Time stamp counter at trigger time bits 15 .. 0 \\\hline

%0x018 & 2nd event Trigger-ID \\\hline
%0x019 & 2nd event Trigger-ID \\\hline
%0x01A & 2nd event Trigger-ID \\\hline
%0x01B & 2nd event Trigger primitives crate 0 \\\hline
%0x01C & 2nd event Trigger primitives crate 1 \\\hline
%0x01D & 2nd event Trigger primitives crate 2 \\\hline
%0x01E & 2nd event Trigger primitives crate 3 \\\hline
%0x01F & 2nd event Time stamp counter at trigger time bits 47 .. 32 \\\hline
%0x020 & 2nd event Time stamp counter at trigger time bits 31 .. 16 \\\hline
%0x021 & 2nd event Time stamp counter at trigger bits 15 .. 0 \\\hline
%... & ...\\\hline
%0x1F8 & 50th event Trigger-ID \\\hline
%0x1F9 & 50th event Trigger-ID \\\hline
%0x1FA & 50th event Trigger-ID \\\hline
%0x1FB & 50th event Trigger primitives crate 0 \\\hline
%0x1FC & 50th event Trigger primitives crate 1 \\\hline
%0x1FD & 50th event Trigger primitives crate 2 \\\hline
%0x1FE & 50th event Trigger primitives crate 3 \\\hline
%0x1FF & 50th event Time stamp counter at trigger time bits 47 .. 32 \\\hline
%0x200 & 50th event Time stamp counter at trigger time bits 31 .. 16 \\\hline
%0x201 & 50th event Time stamp counter at trigger bits 15 .. 0 \\\hline

%% \end{longtable}
%\caption{FTM trigger list}
%\label{tab:FTM-trigger-list}
%\end{longtable}

\section{FTU list}
\label{sec:FTU-List}
When the FTM board receives the 'ping all FTUs' instruction, it sends a ping
command to all FTU boards and gathers the FTU boards responses to a list. This
list is called 'FTU list' and shown in table \ref{tab:FTU-list}. The FTM only
accepts a ping when no run is ongoing (defined by the 'start run' and 'stop
run' commands). When the FTU list is complete, it is sent back via ethernet
with the header defined in table~\ref{tab:FTM-header}.

\begin{longtable}[h]{|l|l|}\hline
address & content\\\hline\hline

0x000 & total number of responding FTU boards\\\hline
0x001 & number of responding FTU boards belonging to crate 0 \\\hline
0x002 & number of responding FTU boards belonging to crate 1 \\\hline
0x003 & number of responding FTU boards belonging to crate 2 \\\hline
0x004 & number of responding FTU boards belonging to crate 3 \\\hline

0x005 & active FTU list crate 0 \\\hline
0x006 & active FTU list crate 1 \\\hline
0x007 & active FTU list crate 2 \\\hline
0x008 & active FTU list crate 3 \\\hline 

0x009 & address of first  FTU board and number of sent pings\\\hline

0x00A & DNA of first FTU board bit 63 ... 48\\\hline
0x00B & DNA of first FTU board bit 47 ... 32\\\hline
0x00C & DNA of first FTU board bit 31 ... 16\\\hline
0x00D & DNA of first FTU board bit 15 ... 0\\\hline

0x00E & address of second FTU board and number of sent pings\\\hline

0x00F & DNA of second FTU board bit 63 ... 48\\\hline
0x010 & DNA of second FTU board bit 47 ... 32\\\hline
0x011 & DNA of second FTU board bit 31 ... 16\\\hline
0x012 & DNA of second FTU board bit 15 ... 0\\\hline
... & ...\\\hline
\caption{FTU list}
\label{tab:FTU-list}
\end{longtable}



Because there are four connectors for the RS-485 buses, one for each crate,
there will be a full scan for all addresses on every connector.  In case there
is no response to a 'ping' on a certain address, there will be up to two
repetitions. A responding FTU board will get an entry into the FTU list (table
\ref{tab:FTU-list}) including the number of 'ping' sent until response.
The number of pings is coded together with the FTU board address as shown in table
\ref{tab:FTU-crate-number-and-address}.
The two bits 'pings\_0' and 'pings\_1' contain the number
of 'pings' until response of an FTU board coded in binary.
The 'DNA' of the FTU board is the device DNA \cite{ds557, ds610, wp267, wp266} 
of the FPGA on the responding FTU board. This is a unique 57 bit serial number
unambiguously identifying every Xilinx FPGA. In the most significant word (bit
63 ... 48) bits 63 down to 57 are filled with zeros.


\begin{table}[h]
\centering
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
Bit      & 15 ... 10 & 9 & 8 & 7 & 6 & 5 & ... & 0 \\\hline

Content & x ... x & pings\_1 & pings\_0 & x & x & A5 & ... & A0 \\\hline
\end{tabular}
\caption{Crate number and address of first responding FTU board}
\label{tab:FTU-crate-number-and-address}
\end{table}

\chapter{FTU communication error handling}
\label{cha:Error-handling}

When the FTM board is communicating with a FTU board via RS-485, the FTU board
has to respond within 5 ms. If this timeout expires, or the response sent back
by the FTU board is incorrect, the FTM resends the datapacket after the
timeout. If this second attempt is still unsuccessful, a third and last
attempt will be made by the FTM board. An error message will be sent to the
central control whenever a FTU board does not send a correct answer after the
first call by the FTM board. This message (see table~\ref{tab:error-message})
contains, after the standard header (see table~\ref{tab:FTM-header}), the
number of unsuccessful calls and the data packet sent to the FTU board in
these unsuccessful calls. In order to avoid massive error messages for
e.g. test setups with single FTUs, the 'active FTU list' can be employed to
disable FTUs from the bus. In that case the FTM will not try to contact the
corresponding boards.

\begin{table}[h]
  \centering
  \begin{tabular}{|l|l|}\hline
    word no & content\\\hline\hline
    0x000 & board ID bits 63...48 \\\hline
    0x001 & board ID bits 47...32\\\hline
    0x002 & board ID bits 31...16\\\hline
    0x003 & board ID bits 15...0\\\hline
    0x004 & firmware ID \\\hline
    0x005 & Trigger counter at read-out time bits 31...16 \\\hline
    0x006 & Trigger counter at read-out time bits 15...0\\\hline
    0x007 & Time stamp counter at read-out time bits 47...32 \\\hline
    0x008 & Time stamp counter at read-out time bits 31...16 \\\hline
    0x009 & Time stamp counter at read-out time bits 15...0 \\\hline
    0x00A & spare \\\hline
    0x00B & number of unsuccessful calls\\\hline
    0x00C ... 0x027 & slow control data packet sent to FTU (28 byte)\\\hline
  \end{tabular}
  \caption{FTU communication error message}
  \label{tab:error-message}
\end{table}

%---------------------------------------------------------------------------------

\bibliographystyle{unsrt}
%\bibliography{FTM-Com}

\begin{thebibliography}{1}

\bibitem{DRS4}
Paul Scherrer Institut PSI.
\newblock {\em DRS4 9 Channel, 5 GSPS Switched Capacitor Array}.
\newblock datasheet.

\bibitem{LMK03000}
National Semiconductor Corporation.
\newblock {\em LMK03000 Family Precision Clock Conditioner with integrated
  VCO}, 2008.
\newblock datasheet.

\bibitem{FTM-Schematics}
ETH Z{\"u}rich, IPP.
\newblock {\em FTM Schematics}, 2010.

\bibitem{W5300}
WIZnet Co.Ltd.
\newblock {\em W5300 Fully Hardwired Network protocol Embedded Ethernet
  Controller}, 2008.
\newblock datasheet.

\bibitem{ds557}
Xilinx.
\newblock {\em Spartan-3AN FPGA Family Data Sheet}, 2009.

\bibitem{ds610}
Xilinx.
\newblock {\em Spartan-3A DSP FPGA Family: Data Sheet}, 2009.

\bibitem{wp267}
Xilinx.
\newblock {\em Advanced Security Schemes for Spartan-3A/3AN/3A DSP FPGAs},
  2007.

\bibitem{wp266}
Xilinx.
\newblock {\em Security Solutions Using Spartan-3 Generation FPGAs}, 2008.

\bibitem{MAX6662}
Maxim Integrated Products.
\newblock {\em 12-Bit plus Sign Temperature Sensor with SPI-Compatible Serial
  Interface MAX6662}, 2001.
\newblock datasheet.

\bibitem{FTUspecs}
ETH Z{\"u}rich, IPP.
\newblock {\em FTU Firmware Specifications v3}, 2010.

\end{thebibliography}

\end{document}