source: firmware/FTM/doc/v4.1/FTM_firmware_specs_v4-2.tex @ 10787

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1\documentclass[a4paper,11pt]{report}
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3\usepackage{float}
4\usepackage{graphicx}
5\usepackage{url}
6\usepackage[T1]{fontenc}
7\usepackage{amsmath}
8\usepackage{longtable}
9\usepackage{parskip}
10\usepackage{pifont}
11\usepackage{array}
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17\textwidth 6.2in
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21\pagestyle{plain}
22\setcounter{tocdepth}{1}
23
24\title{\vspace*{-7cm} \Huge \bf FTM Firmware Specifications}
25\author{\Large Patrick Vogler\footnote{Contact for questions and suggestions concerning this
26    document: {\tt patrick.vogler@phys.ethz.ch}}, Quirin Weitzel}
27\date{\vspace*{0.5cm} \Large v4.2~~~-~~~May 2011}
28
29\begin{document}
30
31\maketitle
32
33\newpage
34
35\tableofcontents
36
37%---------------------------------------------------------------------------------
38
39\chapter{Introduction}
40\label{cha:Introduction}
41
42The FTM (FACT Trigger Master) board collects the trigger primitives from all
4340 FTU boards (FACT Trigger Unit) and generates the trigger signal for the
44FACT camera. The trigger logic is a 'n-out-of-40' majority coincidence of all
45trigger primitives. Beside the trigger, the FTM board also generates a
46trigger-ID (see chapter \ref{cha:Trigger-ID}). It is controlled from outside
47via ethernet. Two auxiliary RS-485 interfaces are also available.
48
49In addition to the trigger, the FTM board also generates other fast control
50signals: Time-Marker (TIM), DRS \cite{DRS4} reference clock (CLD) and
51reset. These four fast control signals are distributed to the FAD (FACT Analog
52to Digital) boards via two FFC (FACT Fast Control) boards. The FTM board also
53provides via the TIM line the signal for the DRS timing calibration. In order
54to generate the CLD DRS reference clock, as well as the time-marker signal for
55DRS timing calibration, the FTM board uses a clock conditioner
56\cite{LMK03000}.
57
58The FTM board has two time counters, the 'timestamp counter' and the 'on-time
59counter'. While the 'timestamp counter' runs continuously, the 'on-time
60counter' only counts when the camera trigger is enabled.
61
62The FTM board further serves as slow control master for the 40 FTU boards. The
63slow control of the FTU boards and the distribution of the trigger-ID to the
64FAD boards are performed via dedicated RS-485 buses. Because the FAD as well
65as the FTU boards are arranged in crates of 10 boards each, the FTM board has
66four connectors, one for each crate. Running over these connectors there are
67two RS-485 buses (one for FTU slow control and one for the trigger-ID) besides
68the busy signal from the FAD boards and the crate reset.
69
70In addition, the FTM board controls the two FLPs (FACT Light Pulser) via four
71LVDS signals each. Light pulser~1 is located in the mirror dish, light
72pulser~2 inside the camera shutter. There are also digital auxiliary in- and
73outputs according to the NIM (Nuclear Instrumentation Module) standard, for
74example for external triggers and veto, and to have the signals accessible.
75
76The main component of the FTM board is a FPGA (Xilinx Spartan
77XC3SD3400A-4FGG676C), fulfilling the main functions within the board. The
78purpose of this document is to provide specifications needed for the
79development of the firmware of this FPGA and the software (called 'FTMcontrol'
80in the following) controlling the FTM board. For further information about the
81FTM board hardware please refer to \cite{FTM-Schematics}.
82
83\chapter{Trigger-ID}
84\label{cha:Trigger-ID}
85
86For each processed trigger the FTM board generates a unique trigger-ID to be
87broadcasted to all FAD boards and added to the event data. This trigger-ID
88consists of a 32 bit trigger number, a two byte trigger type indicator and a
89checksum. The transmission protocol for the trigger-ID broadcast is shown in
90table \ref{tab:Trigger-ID broadcast}.
91
92\begin{table}[htbp]
93\centering
94\begin{tabular}{|l|l|}\hline
95byte no & content\\\hline\hline
960 & Trigger-No first byte (least significant byte) \\\hline
971 & Trigger-No second byte\\\hline
982 & Trigger-No third byte\\\hline
993 & Trigger-No forth byte (most significant byte)\\\hline
1004 & Trigger-Type 1\\\hline
1015 & Trigger-Type 2\\\hline
1026 & CRC-8-CCITT (checksum)\\\hline
103\end{tabular}
104\caption{The transmission protocol to broadcast the trigger-ID to the FAD boards}
105\label{tab:Trigger-ID broadcast}
106\end{table}
107
108A Cyclic Redundancy Check (CRC) over byte 0 - 5 is used to evaluate the
109integrity of the trigger-ID. An 8-CCITT CRC has been chosen which is based on
110the polynomial $x^8 + x^2 + x + 1$ (00000111, omitting the most significant
111bit). The resulting 1-byte checksum comprises the last byte of the trigger-ID.
112The transmission of the trigger-ID to the FAD boards is done by means of
113dedicated RS-485 buses (one per crate).
114
115In the first byte of the trigger type indicator (see table
116\ref{tab:Trigger-Type 1}) n0 - n5 indicate the number of trigger primitives
117required for a trigger, thus the 'n' of the 'n-out-of-40' majority
118coincidence. The two flags 'external trigger 1' and 'external trigger 2',
119when set, indicate a trigger from the corresponding NIM inputs. See also
120section \ref{sec:Static-data-block} and table \ref{tab:FTM-majority} for
121further information.
122
123\begin{table}[htbp]
124\centering
125%\begin{small}
126\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
127  Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
128  n5 & n4 & n3 & n2 & n1 & n0 & external trigger 2 & external trigger 1\\\hline
129\end{tabular}
130%\end{small}
131\caption{Trigger-Type 1}
132\label{tab:Trigger-Type 1}
133\end{table}
134
135\begin{table}[htbp]
136\centering
137\begin{small}
138\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
139Bit7 & Bit6 & Bit5 & Bit4 & Bit3 & Bit2 & Bit1 & Bit0\\\hline\hline 
140TIM source & LP\_set\_3 & LP\_set\_2 & LP\_set\_1 & LP\_set\_0 & pedestal & LP\_2 & LP\_1\\\hline
141\end{tabular}
142\end{small}
143\caption{Trigger-Type 2}
144\label{tab:Trigger-Type 2}
145\end{table}
146
147The 'TIM source' bit in 'Trigger-Type 2' (see table \ref{tab:Trigger-Type 2})
148indicates the source of the timemarker signal: a '0' indicates the timemarker
149being produced in the FPGA while a '1' indicates the timemarker coming from
150the clock conditioner. The flags 'LP\_1' and 'LP\_2' are set when the
151corresponding lightpulser has flashed while the 'pedestal' flag is set in case
152of a pedestal (random) trigger. An event having none of these flags set
153indicates a physics event. The bits 'LP\_set\_0' to 'LP\_set\_3' are used to
154code information about the light pulser settings. They only have a meaning in
155case of calibration events.
156
157\chapter{FTM Commands}
158\label{cha:FTM-Commands}
159
160The communication between the FTM board and the FTMcontrol software, including
161the corresponding commands, protocols and data, is based on 16-bit words and
162big-endian. This is to facilitate the data-transmission over the Wiznet W5300
163ethernet interface \cite{W5300}.
164
165The basic structure of all commands is the same and given in table
166\ref{tab:FTM-command-structure}. After a start delimiter, the second word
167identifies the command. Next there is a parameter further refining the
168command, e.g. what to read. The fourth and fifth words are spares and should
169contain zeros. Starting from the sixth word, an optional data block of
170variable size is following. This data block differs in length and content
171depending on command and parameter. In case of 'read' instructions, the
172corresponding data block is sent back.
173
174%The FTM board must answer every command by sending back the appropriate data
175%block or by simply sending back the instruction where there is no datablock to
176%be sent back.  All 'read' commands to the FTM board do not contain any data
177%blocks, but the FTM boards response does.  In case of 'read' and 'write'
178%instructions, the datablock is to be sent back. When 'start run' or 'stop run'
179%commands are used, the FTM board 'mirrors' them, i.e. sends them back for
180%confirmation.
181
182\begin{table}[p]
183\centering
184\begin{tabular}{|l|l|}\hline
185  word no & content\\\hline\hline
186  0 & start delimiter (e.g. '@') \\\hline
187  1 & command ID \\\hline
188  2 & command parameter \\\hline
189  3 & spare: containing 0x0000\\\hline
190  4 & spare: containing 0x0000 \\\hline
191  5 & data block (optional and of variable size)\\\hline
192  ... & ...\\\hline
193  X & data block\\\hline
194\end{tabular}
195\caption{FTM command structure}
196\label{tab:FTM-command-structure}
197\end{table}
198
199So far seven different commands are foreseen: 'read', 'write', 'start run',
200'stop run', 'ping FTUs', 'crate reset' and 'autosend on/off' (see table
201\ref{tab:FTM-command-ID}). The command parameters of the 'read' and write
202commands are shown in table~\ref{tab:FTM-read-command-param} and
203table~\ref{tab:FTM-write-command-param}, respectively. With the 'autosend
204on/off' command it is possible to switch off the automatic sending of trigger
205rates and error messages (see table~\ref{tab:FTM-as-command-param}).
206
207\begin{table}[p]
208\centering
209\begin{tabular}{|r|r|}\hline
210  command-ID: bits & \\\cline{1-1}
211  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command\\\hline\hline
212  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read \\\hline
213  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & write \\\hline
214  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start run / take X events\\\hline
215  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & stop run \\\hline
216  0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 & ping all FTUs \\\hline
217  0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & crate reset \\\hline
218  0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & autosend on/off \\\hline
219\end{tabular}
220\caption{FTM command ID listing}
221\label{tab:FTM-command-ID}
222\end{table}
223
224\begin{table}[p]
225\centering
226\begin{tabular}{|r|r|r|}\hline
227  command parameter: bits & & \\\cline{1-1}
228  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
229  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & read complete static data block & no\\\hline
230  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & read complete dynamic data block & no\\\hline
231  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 &
232  read single address of static data block & address\\\hline
233  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & read trigger list & no\\\hline
234\end{tabular}
235\caption{Command parameters for the 'read' command; only for the static data
236  block single addresses can be read.}
237\label{tab:FTM-read-command-param}
238\end{table}
239
240\begin{table}[p]
241\centering
242\begin{tabular}{|r|r|r|}\hline
243  command parameter: bits & & \\\cline{1-1}
244  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
245  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & write complete static data block & all configuration data\\\hline
246  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 &
247  write single address of static data block & address + data\\\hline
248\end{tabular}
249\caption{Command parameters for the 'write' command; only the static data
250  block can be written, therefore parameter value 0x2 is not used.}
251\label{tab:FTM-write-command-param}
252\end{table}
253
254\begin{table}[p]
255\centering
256\begin{tabular}{|r|r|r|}\hline
257  command parameter: bits & & \\\cline{1-1}
258  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
259  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 & reports disabled & no\\\hline
260  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reports enabled & no\\\hline
261\end{tabular}
262\caption{Command parameters for the 'autosend on/off' command}
263\label{tab:FTM-as-command-param}
264\end{table}
265
266%\begin{table}[htbp]
267%\centering
268%\begin{tabular}{|r|r|r|}\hline
269%  command parameter: bits & & \\\cline{1-1}
270%  15 ... 8  \vline 7  \vline 6  \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
271%  0 \vline 0 \vline 0 \vline 0 \vline 0  \vline0 \vline 0  \vline0  \vline1 & write static data & static data block\\\hline
272%\end{tabular}
273%\caption{Command parameters for the 'write' command}
274%\label{tab:FTM-write-command-param}
275%\end{table}
276
277In table \ref{tab:FTM-start-command-param} the parameters to start a run are
278listed. The type of the run is fully described in the FTM configuration
279(static data block, see section~\ref{sec:Static-data-block}), which always has
280to be sent by the FTMcontrol before starting a run. Therefore the only
281option is to start an "endless" run or to take X events instead. In the latter
282case X is defined by a two words (32 bit) long unsigned integer, making up the
283command data block. The 'start run' command enables the transmission of
284trigger signals (physics, calibration or pedestal) to the FAD boards and
285resets the trigger and time counters. There is no parameter for stopping a
286run. If a number of events has been specified ('take X events'), the run will
287terminate if either the 'stop run' command is received or the requested number
288of events is reached. In any case the trigger and time counters are reset,
289too.
290
291\begin{table}[p]
292\centering
293\begin{tabular}{|r|r|r|}\hline
294  command parameter: bits & & \\\cline{1-1}
295  15 ... 8  \vline\vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
296  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & start run & no \\\hline
297  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & take X events & number of events X \\\hline
298  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & start taking pedestals & no \\\hline
299  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 1 & take X pedestals events & number of events X \\\hline
300  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & start calibration run & no \\\hline
301  %0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 1 & take X calibration events & number of events X \\\hline
302\end{tabular}
303\caption{Command parameters for the 'start run' command: "start run" means an
304  "endless" run, i.e. no pre-defined number of events; if a number of events X
305  is specified, this is done with a 32-bit unsigned long integer (big endian).}
306\label{tab:FTM-start-command-param}
307\end{table}
308
309%\begin{table}[htbp]
310%\centering
311%\begin{tabular}{|r|r|r|}\hline
312%  command parameter: bits & & \\\cline{1-1}
313%  15 ... 8  \vline 7 \vline 6 \vline 5 \vline 4  \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
314%  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & stop run & no\\\hline
315%\end{tabular}
316%\caption{Command parameter for the 'stop run' command}
317%\label{tab:FTM-stop-command-param}
318%\end{table}
319
320In case of a 'ping FTUs' command the FTM will address the FTUs one by one and
321readout their DNA. The results are collected in the FTU list (see section
322\ref{sec:FTU-List}), which is sent back to the FTMcontrol. There are no
323parameters for this command. With the 'crate reset' command the boards of a
324particular crate can be rebooted, where the command parameter defines the
325crate number (see table \ref{tab:FTM-reset-command-param}). Only one crate
326reset at a time is possible, i.e. the FTM firmware does not allow to reset
327multiple crates in one command.
328
329\begin{table}[p]
330\centering
331\begin{tabular}{|r|r|r|}\hline
332  command parameter: bits & & \\\cline{1-1}
333  15 ... 8 \vline 7 \vline 6 \vline 5 \vline 4 \vline 3 \vline 2 \vline 1 \vline 0 & command & data block\\\hline\hline
334  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 & reset crate 0 & no\\\hline
335  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 & reset crate 1 & no\\\hline
336  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 & reset crate 2 & no\\\hline
337  0 \vline 0 \vline 0 \vline 0 \vline 0 \vline 1 \vline 0 \vline 0 \vline 0 & reset crate 3 & no\\\hline
338\end{tabular}
339\caption{Command parameters for the 'crate reset' command: the command parameter may only contain a single "1"
340         corresponding to only one crate reset at a time.}
341\label{tab:FTM-reset-command-param}
342\end{table}
343
344\chapter{FTM data blocks}
345\label{cha:FTM-data-block}
346
347The trigger master features two main data blocks, named 'static data block'
348and 'dynamic data block' in the following. They are implemented in the
349firmware as block-RAM. In addition, there is the so-called 'FTU list', which
350is filled only on request ('ping FTUs' command). If any of these blocks is
351sent to the FTMcontrol (either automatically or on demand), a header with a
352size of 14 words is added, and the whole data package is put between a start
353and an end delimiter (see table~\ref{tab:FTM-package}). The header is
354identical for all data blocks and contains solely read-only information: the
355type and length of the package, the FTM status, the FTM board ID (57-bit
356Xilinx device DNA \cite{ds557, ds610, wp267, wp266}), a firmware ID and the
357readings of the trigger counter and time stamp counter (see
358table~\ref{tab:FTM-header}).
359
360\begin{table}[h]
361\centering
362\begin{tabular}{|c|c|c|c|}\hline
363  start delimiter & header & data block & end delimiter \\\hline
364  0xFB01 & 14 words & optional size & 0x04FE\\\hline
365\end{tabular}
366\caption{Structure of a data package as sent by the FTM to the FTMcontrol
367  software. The start and end delimiters are the same as used for the FAD boards.}
368\label{tab:FTM-package}
369\end{table}
370
371\begin{table}[h]
372\centering
373\begin{tabular}{|l|l|c|}\hline
374  word no & content & description\\\hline\hline
375  0x000 & type of data package & 1: SD, 2: DD, 3: FTU-list, 4: error, 5: single SD-word\\\hline
376  0x001 & length of data package & after header, including end delimiter\\\hline
377  0x002 & status of FTM & 1: IDLE, 2: CONFIG, 3: RUNNING, 4: CALIB\\\hline
378  0x003 & board ID bits 63...48 & FPGA device DNA\\\hline
379  0x004 & board ID bits 47...32 & FPGA device DNA\\\hline
380  0x005 & board ID bits 31...16 & FPGA device DNA\\\hline
381  0x006 & board ID bits 15... 0 & FPGA device DNA\\\hline
382  0x007 & firmware ID & defined as a VHDL constant\\\hline
383  0x008 & trigger counter bits 31...16 & at read-out time\\\hline
384  0x009 & trigger counter bits 15... 0 & at read-out time\\\hline
385  0x00A & time stamp bits 63...48 & filled up with zeros\\\hline
386  0x00B & time stamp bits 47...32 & at read-out time\\\hline
387  0x00C & time stamp bits 31...16 & at read-out time\\\hline
388  0x00D & time stamp bits 15... 0 & at read-out time\\\hline
389\end{tabular}
390\caption{Header structure for sending a data block or error message}
391\label{tab:FTM-header}
392\end{table}
393
394\section{Static data block}
395\label{sec:Static-data-block}
396
397The static data block contains all the settings needed to configure and
398operate the FTM. It has to be written by the FTMcontrol each time before a run
399is started or, in general, some component has to be reprogrammed. Single
400register access is possible, but not foreseen for the standard data taking. In
401addition, whenever the FTM board receives a new static data block, it performs
402a complete reconfiguration including a reprogramming of the
403FTUs. Table~\ref{tab:FTM-trigger-master-static-data-block} summarizes the
404static data block. More details about the individual registers can be found in
405the subsequent tables.
406
407%These settings are readable and writable by the main control using the
408%corresponding commands 'read static data block' or 'write static data block',
409%respectively.  There is one exception from writability: In case the static
410%data block is read back, the first eleven words (address 0..A) are identical
411%with the dynamic data block and the trigger list shown in
412%\ref{tab:FTM-trigger-master-dynamic-data-block} and
413%\ref{tab:FTM-trigger-list}.  These first eleven words can only be read and not
414%written.  The board ID is supposed to be the Xilinx device DNA \cite{ds557,
415%  ds610, wp267, wp266}, the 57 bit device ID of the FPGA.  When using the
416%'write static data block' command, the static data block must start with the
417%'general settings register' at address 0x00B. So there is an offset in the
418%addresses of 0x00B between the 'read-out-version' and the 'write-version' of
419%the static data block.
420
421\begin{longtable}[h]{|l|l|c|}\hline
422\centering
423word no & content & description\\\hline\hline
4240x000 & general settings & see table~\ref{tab:FTM-general-settings-register} and text\\\hline
4250x001 & on-board status LEDs & see table~\ref{tab:FTM-LED-register}\\\hline
4260x002 & light pulser and pedestal trigger period & see table~\ref{tab:FTM-frequency-register} and text\\\hline
4270x003 & sequence of LP1, LP2 and PED triggers & see table~\ref{tab:FTM-ratio-register} and text\\\hline
428
4290x004 & light pulser 1 amplitude & see table~\ref{tab:LP1-amplitude-register} and text\\\hline
4300x005 & light pulser 2 amplitude & see table~\ref{tab:LP2-amplitude-register} and text\\\hline
4310x006 & light pulser 1 delay & 8ns + delay value*4ns\\\hline
4320x007 & light pulser 2 delay & 8ns + delay value*4ns\\\hline
433
4340x008 & majority coincidence n (for physics) & see table~\ref{tab:FTM-majority} and text\\\hline
4350x009 & majority coincidence n (for calibration) & see table~\ref{tab:FTM-majority} and text\\\hline
4360x00A & trigger delay & 8ns + delay value*4ns, 10 bits used\\\hline
4370x00B & timemarker delay & 8ns + delay value*4ns, 10 bits used\\\hline
4380x00C & dead time & 8ns + value*4ns, 16 bits used\\\hline
4390x00D & clock conditioner R0 bits 31...16 & \\\hline
4400x00E & clock conditioner R0 bits 15...0 & \\\hline
4410x00F & clock conditioner R1 bits 31...16 & \\\hline
4420x010 & clock conditioner R1 bits 15...0 & \\\hline
4430x011 & clock conditioner R8 bits 31...16 & \\\hline
4440x012 & clock conditioner R8 bits 15...0 & \\\hline
4450x013 & clock conditioner R9 bits 31...16 & \\\hline
4460x014 & clock conditioner R9 bits 15...0 & \\\hline
4470x015 & clock conditioner R11 bits 31...16 & \\\hline
4480x016 & clock conditioner R11 bits 15...0 & \\\hline
4490x017 & clock conditioner R13 bits 31...16 & \\\hline
4500x018 & clock conditioner R13 bits 15...0 & \\\hline
4510x019 & clock conditioner R14 bits 31...16 & \\\hline
4520x01A & clock conditioner R14 bits 15...0 & \\\hline
4530x01B & clock conditioner R15 bits 31...16 & \\\hline
4540x01C & clock conditioner R15 bits 15...0 & \\\hline
4550x01D & maj. coinc. window (for physics) & 8ns + value*4ns, 4 bits used\\\hline
4560x01E & maj. coinc. window (for calibration) & 8ns + value*4ns, 4 bits used \\\hline
4570x01F & spare & \\\hline
4580x020 & enables patch 0 board 0 crate 0 & see FTU documentation\\\hline
4590x021 & enables patch 1 board 0 crate 0 & see FTU documentation\\\hline
4600x022 & enables patch 2 board 0 crate 0 & see FTU documentation\\\hline
4610x023 & enables patch 3 board 0 crate 0 & see FTU documentation\\\hline
4620x024 & DAC$\_$A board 0 crate 0 & see FTU documentation \\\hline
4630x025 & DAC$\_$B board 0 crate 0 & see FTU documentation \\\hline
4640x026 & DAC$\_$C board 0 crate 0 & see FTU documentation \\\hline
4650x027 & DAC$\_$D board 0 crate 0 & see FTU documentation \\\hline
4660x028 & DAC$\_$H board 0 crate 0 & see FTU documentation \\\hline
4670x029 & Prescaling board 0 crate 0 & (value+1)/2~[s], also autosend period \\\hline
4680x02A & enables patch 0 board 1 crate 0 & see FTU documentation  \\\hline
4690x02B & enables patch 1 board 1 crate 0 & see FTU documentation  \\\hline
4700x02C & enables patch 2 board 1 crate 0 & see FTU documentation  \\\hline
4710x02D & enables patch 3 board 1 crate 0 & see FTU documentation  \\\hline
4720x02E & DAC$\_$A board 1 crate 0 & see FTU documentation \\\hline
4730x02F & DAC$\_$B board 1 crate 0 & see FTU documentation \\\hline
4740x030 & DAC$\_$C board 1 crate 0 & see FTU documentation \\\hline
4750x031 & DAC$\_$D board 1 crate 0 & see FTU documentation \\\hline
4760x032 & DAC$\_$H board 1 crate 0 & see FTU documentation \\\hline
4770x033 & Prescaling board 1 crate 0 & see FTU documentation \\\hline
478... & ... & \\\hline
4790x1A6 & enables patch 0 board 9 crate 3 & see FTU documentation \\\hline
4800x1A7 & enables patch 1 board 9 crate 3 & see FTU documentation \\\hline
4810x1A8 & enables patch 2 board 9 crate 3 & see FTU documentation \\\hline
4820x1A9 & enables patch 3 board 9 crate 3 & see FTU documentation \\\hline
4830x1AA & DAC$\_$A board 9 crate 3 & see FTU documentation \\\hline
4840x1AB & DAC$\_$B board 9 crate 3 & see FTU documentation \\\hline
4850x1AC & DAC$\_$C board 9 crate 3 & see FTU documentation \\\hline
4860x1AD & DAC$\_$D board 9 crate 3 & see FTU documentation \\\hline
4870x1AE & DAC$\_$H board 9 crate 3 & see FTU documentation \\\hline
4880x1AF & Prescaling board 9 crate 3 & see FTU documentation \\\hline
4890x1B0 & active FTU list crate 0 & see FTU documentation \\\hline
4900x1B1 & active FTU list crate 1 & see FTU documentation \\\hline
4910x1B2 & active FTU list crate 2 & see FTU documentation \\\hline
4920x1B3 & active FTU list crate 3 & see FTU documentation \\\hline 
493\caption{Overview of the FTM static data block}
494\label{tab:FTM-trigger-master-static-data-block}
495\end{longtable}
496
497The FTM general settings register is detailed in table
498\ref{tab:FTM-general-settings-register}. The 'TIM\_CLK' bit defines whether
499the time marker is generated by the FPGA ('TIM\_CLK' = 0, default for physics
500data taking), or whether it is generated by the clock conditioner ('TIM\_CLK'
501= 1, e.g. for DRS timing calibration). The 'ext\_veto', 'ext\_trig\_1' and
502'ext\_trig\_2' bits enable (1) or disable (0) the NIM inputs for the external
503veto and trigger signals, respectively. In order to select which trigger
504sources are active during a run, the bits 'LP1', 'LP2', 'ped' and 'trigger'
505are foreseen (0 disabled, 1 enabled). During a physics run, for example,
506'LP1', 'ped' and 'trigger' should all be set to generate interleaved
507calibration and pedestal events as well as activate the 'n-out-of-40' trigger
508input. For a didicated pedestal run only 'ped' should be set, since in this
509case the FTM sends directly a trigger to the FADs. For calibration runs it
510depends on whether the external (LP1) or internal (LP2) light pulser is used:
511For the first case 'LP1' and 'trigger' have to be set, since here the full
512trigger chain is involved and the camera triggers based on G-APD signals. For
513the second case only 'LP2' is needed, because the shutter is closed and the
514FTM sends directly the trigger signal to the FADs (like for pedestal
515events). Bits 8 to 15 of the general settings register are not used up to now.
516
517\begin{table}[h]
518\centering
519\begin{small}
520\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
521Bit & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
522Content & x & trigger & ped & LP2 & LP1 & ext\_trig\_2 & ext\_trig\_1& ext\_veto & TIM\_CLK \\\hline
523\end{tabular}
524\end{small}
525\caption{FTM general settings register}
526\label{tab:FTM-general-settings-register}
527\end{table}
528
529%\begin{table}[!h]
530%\centering
531%\begin{tabular}{|l|l|}\hline
532%TIM\_CClk & description \\\hline\hline
533%0 & Time marker generated in the FPGA \\\hline
534%1 & Time marker generated by the clock conditioner \\\hline
535%\end{tabular}
536%\caption{FTM Time marker indication}
537%\label{tab:FTM-Time-marker-indication}
538%\end{table}
539
540%\begin{table}[!h]
541%\centering
542%\begin{tabular}{|l|l|}\hline
543%ena$\_$ext$\_$Veto  & description \\\hline\hline
544%0 & disable external trigger veto\\\hline
545%1 & enable external trigger veto \\\hline
546%\end{tabular}
547%\caption{FTM external trigger}
548%\label{tab:FTM-external-trigger}
549%\end{table}
550
551%\begin{table}[!h]
552%\centering
553%\begin{tabular}{|l||l|}\hline
554%ena\_LP1  & description \\\hline\hline
555%0 & disable light pulser 1 \\\hline
556%1 & enable light pulser 1\\\hline
557%\end{tabular}
558%\caption{FTM light pulser 1}
559%\label{tab:FTM-light-pulser-1}
560%\end{table}
561
562%\begin{table}[!h]
563%\centering
564%\begin{tabular}{|l||l|}\hline
565%ena\_LP2  & description \\\hline\hline
566%0 & disable light pulser 2 \\\hline
567%1 & enable light pulser 2 \\\hline
568%\end{tabular}
569%\caption{FTM light pulser 2}
570%\label{tab:FTM-light-pulser-2}
571%\end{table}
572
573%\begin{table}[!h]
574%\centering
575%\begin{tabular}{|l||l|}\hline
576%ena\_Ped  & description \\\hline\hline
577%0 & disable interleaved pedestal trigger \\\hline
578%1 & enable interleaved pedestal trigger \\\hline
579%\end{tabular}
580%\caption{FTM interleaved pedestals}
581%\label{tab:FTM-interleaved-pedestals}
582%\end{table}
583
584%\begin{table}[!h]
585%\centering
586%\begin{small}
587%\begin{tabular}{|l||l|}\hline
588%ena\_LLC  & description \\\hline\hline
589%0 & disable low level calibration pulses \\\hline
590%1 & enable low level calibration pulses \\\hline
591%\end{tabular}
592%\end{small}
593%\caption{FTM low level calibration pulses}
594%\label{tab:FTM-low-level-calibration-pulses}
595%\end{table}
596
597The 'on-board status LEDs' register shown in table \ref{tab:FTM-LED-register}
598allows to switch a total of eight LEDs on the FTM board for debugging purposes
599by setting the corresponding bit high.
600
601\begin{table}[h]
602\centering
603\begin{small}
604\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|}\hline
605Bit      & 15...8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
606Content &  x & red$\_$3 & red$\_$2 & gn$\_$1 & ye$\_$1 & red$\_$1 & gn$\_$0 & ye$\_$0 & red$\_$0 \\\hline
607\end{tabular}
608\end{small}
609\caption{'on-board status LEDs' register}
610\label{tab:FTM-LED-register}
611\end{table}
612
613The period (time distance, see table \ref{tab:FTM-frequency-register}), with
614which light pulser and pedestal triggers are sent, is stored in the register
615at address 0x002. It is given in [ms] and adjustable between 1\,ms and
6161023\,ms (10 bits used). The next register defines the sequence of LP1, LP2
617and pedestal events (see table \ref{tab:FTM-ratio-register}).
618 
619\begin{table}[h]
620\centering
621\begin{small}
622\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
623Bit      & 15 - 10 & 9 & 8 & ... & 2 & 1 & 0 \\\hline
624Content &  x  & PERIOD\_9 & PERIOD\_8 & ... & PERIOD\_2 & PERIOD\_1 & PERIOD\_0 \\\hline
625\end{tabular}
626\end{small}
627\caption{Register for the period [ms] of calibration and pedestal events}
628\label{tab:FTM-frequency-register}
629\end{table}
630
631\begin{table}[h]
632\centering
633\begin{small}
634\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|}\hline
635Bit      & 15 & 14 & ... & 10 & 9 & ... & 5 & 4 & ... & 0 \\\hline
636Content & x & ped\_S4 & ... & ped\_S0 & LP2\_S4 & ... & LP2\_S0 & LP1\_S4 & ... & LP1\_S0 \\\hline
637\end{tabular}
638\end{small}
639\caption{Register defining the sequence of LP1, LP2 and pedestal events; 5
640  bits used per value. By setting e.g. LP1/LP2/PED = 3/2/1, the systems
641  generates 3 LP1 triggers, followed by 2 LP2 triggers, followed by 1 PED
642  trigger (if they are also activated in the 'general settings' register).
643  The distance between the triggers is defined with another register
644  (table~\ref{tab:FTM-frequency-register}).}
645\label{tab:FTM-ratio-register}
646\end{table}
647
648%\begin{table}[!h]
649%\centering
650%\begin{tiny}
651%\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
652%Bit      & 15 - 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\\hline
653%Function &  x  & LPR2\_9 & LPR2\_8 & LPR2\_7 & LPR2\_6 & LPR2\_5 & LPR2\_4 & LPR2\_3 & LPR2\_2 & LPR2\_1 & LPR2\_0 \\\hline
654%\end{tabular}
655%\end{tiny}
656%\caption{Light pulser 2 frequency register at address 0x00E: This register contains the pulse rate of the light
657%               pulser 2 in Hz.}
658%\label{tab:Light-pulser-2-frequancy-register}
659%\end{table}
660
661
662
663
664
665
666
667
668
669
670
671In order to define the amplitude and characteristics of the light pulses that
672are generated by the LP1 and the LP2 system, the registers 'LP1 amplitude' and
673'LP2 amplitude' are used, respectively. These registers are presented in
674table~\ref{tab:LP1-amplitude-register} and table~\ref{tab:LP2-amplitude-register}.
675The two most significant bit allow to switch on additional LEDs, while the six
676least significant bits are used for the PWM (pulse width modulation) on the
677light pulser board. This pulse width signal is used for stabilizing the amplitude
678of the light pulses, see the schematics \cite{FLD-Schematics}.
679
680The light pulser systems are controlled from the FTM by means of four LVDS control lines:
681The first line goes directly to the LED driver circuit and triggers a lightpulse.
682The PWM signal is on the second line.
683The third and forth line allow to switch on additional LEDs.
684
685
686
687
688
689
690
691
692\begin{table}[!h]
693\centering
694\begin{small}
695\begin{tabular}{|l|l|l|l|l|}\hline
696Bit      & 15 & 14 & 13 ... 6 & 5 ... 0 \\\hline
697Content &  add\_LEDs1\_1& add\_LEDs1\_0 & x & PWM1\_5 ... PWM1\_0 \\\hline
698\end{tabular}
699\end{small}
700\caption{Light pulser 1 amplitude register}
701\label{tab:LP1-amplitude-register}
702\end{table}
703
704
705
706
707\begin{table}[!h]
708\centering
709\begin{small}
710\begin{tabular}{|l|l|l|l|l|}\hline
711Bit      & 15 & 14 & 13 ... 6 & 5 ... 0 \\\hline
712Content &  add\_LEDs2\_1& add\_LEDs2\_0 & x & PWM2\_5 ... PWM2\_0 \\\hline
713\end{tabular}
714\end{small}
715\caption{Light pulser 2 amplitude register}
716\label{tab:LP2-amplitude-register}
717\end{table}
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735The different settings of the 'n-out-of-40' logic (physics or calibration
736events) are stored in two separate registers, which both have a structure
737according to table~\ref{tab:FTM-majority}.
738
739\begin{table}[!h]
740\centering
741\begin{small}
742\begin{tabular}{|l|l|l|l|l|l|l|l|}\hline
743Bit      & 15...6 & 5 & 4 & 3 & 2 &1 & 0 \\\hline
744Content & x & n5 & n4 & n3 & n2 & n1 & n0 \\\hline
745\end{tabular}
746\end{small}
747\caption{Structure of the two majority coincidence (n-out-of-40) registers; the binary value
748  in these registers is the minimum number n of FTU trigger primitives required to trigger an event (physics or calibration)}
749\label{tab:FTM-majority}
750\end{table}
751
752In addition, there are several registers in the static data block to define
753delays (e.g. for the trigger). Also a general dead time to be applied after
754each trigger can be set (to compensate for the delay of the busy line). The
755clock conditioner settings are specified at address 0x00D to 0x01C (LMK03000
756from National Semiconductor, for more details see \cite{LMK03000}).
757
758Starting at address 0x020, the FTU settings are stored. The FTM always holds
759the complete FTU parameters in the static data block. For the meaning of these
760registers, please refer to the FTU firmware specifications document
761\cite{FTUspecs}. The register at address 0x029 is special in the sense that,
762in addition to its normal meaning, it also defines the time period with which
763the FTU rates are sent automatically to the FTMcontrol software. In case not
764all FTUs are connected during e.g. the testing phase, or a FTU is broken, the
765'active FTU list' registers can be used to disable certain boards. Bits 9...0
766of one of the active FTU lists (address 0x1B0 to 0x1B3, corresponding to crate
7670 to 3) contain the "active" flag for every FTU board. Setting a bit activates
768the corresponding FTU board while a "0" deactivates it.
769
770\section{Dynamic data block}
771\label{sec:Dynamic-data-block}
772The dynamic data block shown in table \ref{tab:FTM-dynamic-data-block}
773contains permanently updated data stored inside the FTM FPGA. It contains the
774actual on-time counter reading, the board temperatures and the trigger rates
775measured by the FTUs. This data block is updated and sent periodically by the
776FTM. Thus the FTMcontrol software receives periodically a corresponding data
777package via ethernet. The counting interval of the FTU board 0 on crate 0
778('prescaling' register) defines the period. The on-board 12-bit temperature
779sensors are MAX6662 chips from Maxim Products. For more information about
780these components and their data see \cite{MAX6662}. When sending the dynamic
781data block, the header defined in table~\ref{tab:FTM-header} is added at the
782beginning.
783
784\newpage
785
786% \begin{table}[h]
787%  \centering
788\begin{longtable}[h]{|l|l|}\hline
789word no & content\\\hline\hline
7900x000 & on-time counter at read-out time bits 63...48, filled up with zeros \\\hline
7910x001 & on-time counter at read-out time bits 47...32 \\\hline
7920x002 & on-time counter at read-out time bits 31...16 \\\hline
7930x003 & on-time counter at read-out time bits 15...0 \\\hline
7940x004 & temperature sensor 0: component U45 on the FTM schematics \cite{FTM-Schematics}\\\hline
7950x005 & temperature sensor 1: U46 \\\hline
7960x006 & temperature sensor 2: U48 \\\hline
7970x007 & temperature sensor 3: U49 \\\hline
7980x008 & rate counter bit 29...16 patch 0 board 0 crate 0 \\\hline
7990x009 & rate counter bit 15...0 patch 0 board 0 crate 0 \\\hline
8000x00A & rate counter bit 29...16 patch 1 board 0 crate 0 \\\hline
8010x00B & rate counter bit 15...0 patch 1 board 0 crate 0 \\\hline
8020x00C & rate counter bit 29...16 patch 2 board 0 crate 0 \\\hline
8030x00D & rate counter bit 15...0 patch 2 board 0 crate 0 \\\hline
8040x00E & rate counter bit 29...16 patch 3 board 0 crate 0 \\\hline
8050x00F & rate counter bit 15...0 patch 3 board 0 crate 0 \\\hline
8060x010 & rate counter bit 29...16 total board 0 crate 0 \\\hline
8070x011 & rate counter bit 15...0 total board 0 crate 0\\\hline
8080x012 & Overflow register board 0 crate 0 \\\hline
8090x013 & CRC-error register board 0 crate 0 \\\hline
8100x014 & rate counter bit 29...16 patch 0 board 1 crate 0 \\\hline
8110x015 & rate counter bit 15...0 patch 0 board 1 crate 0 \\\hline
8120x016 & rate counter bit 29...16 patch 1 board 1 crate 0 \\\hline
8130x017 & rate counter bit 15...0 patch 1 board 1 crate 0 \\\hline
8140x018 & rate counter bit 29...16 patch 2 board 1 crate 0 \\\hline
8150x019 & rate counter bit 15...0 patch 2 board 1 crate 0 \\\hline
8160x01A & rate counter bit 29...16 patch 3 board 1 crate 0 \\\hline
8170x01B & rate counter bit 15...0 patch 3 board 1 crate 0 \\\hline
8180x01C & rate counter bit 29...16 total board 1 crate 0 \\\hline
8190x01D & rate counter bit 15...0 total board 1 crate 0  \\\hline
8200x01E & Overflow register board 1 crate 0 \\\hline
8210x01F & CRC-error register board 1 crate 0 \\\hline
822... & ... \\\hline
8230x1E7 & CRC-error register board 9 crate 3 \\\hline
824% \end{longtable}
825\caption{FTM dynamic data block}
826\label{tab:FTM-dynamic-data-block}
827\end{longtable}
828
829%\section{Trigger-list}
830%\label{sec:trigger-list}
831%The FTM board records all triggers in a list, the so-called trigger-list.
832%This trigger-list comprises a maximum of 50 triggers.  The first eleven words
833%are the same as in the static- and dynamic data block.  During data-taking-,
834%calibration- and trigger runs, the Trigger-list is automatically sent to the
835%main control each time the 50 triggers are reached or the run is finished. In
836%addition, the Trigger-list can also be read-out by the main control with the
837%according command.  In case the run finishes or is terminated, as well as when
838%read out manually, the trigger list might be shorter than 50 events.
839
840%% \begin{table}[h]
841%% \centering
842%\begin{longtable}[h]{|l|l|}\hline
843%address & content\\\hline\hline
844%0x000 & board ID bit 63 - 48 \\\hline
845%0x001 & board ID bit 47 - 32\\\hline
846%0x002 & board ID bit 31 - 16\\\hline
847%0x003 & board ID bit 15 - 0\\\hline
848%0x004 & firmware ID \\\hline
849%0x005 & Trigger counter at read-out time bits 31 .. 16 \\\hline
850%0x006 & Trigger counter at read-out time bits 15 .. 0\\\hline
851%0x007 & Time stamp counter at read-out time bits 47 .. 32 \\\hline
852%0x008 & Time stamp counter at read-out time bits 31 .. 16 \\\hline
853%0x009 & Time stamp counter at read-out time bits 15 .. 0 \\\hline
854%0x00A & spare \\\hline
855
856%0x00B & on-time counter at read-out time bits 47 .. 32 \\\hline
857%0x00C & on-time counter at read-out time bits 31 .. 16 \\\hline
858%0x00D & on-time counter at read-out time bits 15 .. 0 \\\hline
859
860%0x00E & 1st event Trigger-ID \\\hline
861%0x00F & 1st event Trigger-ID \\\hline
862%0x010 & 1st event Trigger-ID \\\hline
863%0x011 & 1st event Trigger primitives crate 0 \\\hline
864%0x012 & 1st event Trigger primitives crate 1 \\\hline
865%0x013 & 1st event Trigger primitives crate 2 \\\hline
866%0x014 & 1st event Trigger primitives crate 3 \\\hline
867%0x015 & 1st event Time stamp counter at trigger time bits 47 .. 32 \\\hline
868%0x016 & 1st event Time stamp counter at trigger time bits 31 .. 16 \\\hline
869%0x017 & 1st event Time stamp counter at trigger time bits 15 .. 0 \\\hline
870
871%0x018 & 2nd event Trigger-ID \\\hline
872%0x019 & 2nd event Trigger-ID \\\hline
873%0x01A & 2nd event Trigger-ID \\\hline
874%0x01B & 2nd event Trigger primitives crate 0 \\\hline
875%0x01C & 2nd event Trigger primitives crate 1 \\\hline
876%0x01D & 2nd event Trigger primitives crate 2 \\\hline
877%0x01E & 2nd event Trigger primitives crate 3 \\\hline
878%0x01F & 2nd event Time stamp counter at trigger time bits 47 .. 32 \\\hline
879%0x020 & 2nd event Time stamp counter at trigger time bits 31 .. 16 \\\hline
880%0x021 & 2nd event Time stamp counter at trigger bits 15 .. 0 \\\hline
881%... & ...\\\hline
882%0x1F8 & 50th event Trigger-ID \\\hline
883%0x1F9 & 50th event Trigger-ID \\\hline
884%0x1FA & 50th event Trigger-ID \\\hline
885%0x1FB & 50th event Trigger primitives crate 0 \\\hline
886%0x1FC & 50th event Trigger primitives crate 1 \\\hline
887%0x1FD & 50th event Trigger primitives crate 2 \\\hline
888%0x1FE & 50th event Trigger primitives crate 3 \\\hline
889%0x1FF & 50th event Time stamp counter at trigger time bits 47 .. 32 \\\hline
890%0x200 & 50th event Time stamp counter at trigger time bits 31 .. 16 \\\hline
891%0x201 & 50th event Time stamp counter at trigger bits 15 .. 0 \\\hline
892
893%% \end{longtable}
894%\caption{FTM trigger list}
895%\label{tab:FTM-trigger-list}
896%\end{longtable}
897
898\section{FTU list}
899\label{sec:FTU-List}
900When the FTM board receives the 'ping all FTUs' instruction, it sends a ping
901command to all FTU boards and gathers the FTU boards responses to a list. This
902list is called 'FTU list' and shown in table \ref{tab:FTU-list}. When the FTU
903list is complete, it is sent back via ethernet with the header defined in
904table~\ref{tab:FTM-header}.
905
906\begin{longtable}[h]{|l|l|}\hline
907address & content\\\hline\hline
9080x000 & total number of responding FTU boards\\\hline
9090x001 & number of responding FTU boards belonging to crate 0 \\\hline
9100x002 & number of responding FTU boards belonging to crate 1 \\\hline
9110x003 & number of responding FTU boards belonging to crate 2 \\\hline
9120x004 & number of responding FTU boards belonging to crate 3 \\\hline
9130x005 & active FTU list crate 0 \\\hline
9140x006 & active FTU list crate 1 \\\hline
9150x007 & active FTU list crate 2 \\\hline
9160x008 & active FTU list crate 3 \\\hline 
9170x009 & address of first FTU board and number of sent pings until response\\\hline
9180x00A & DNA of first FTU board bit 63 ... 48\\\hline
9190x00B & DNA of first FTU board bit 47 ... 32\\\hline
9200x00C & DNA of first FTU board bit 31 ... 16\\\hline
9210x00D & DNA of first FTU board bit 15 ... 0\\\hline
9220x00E & CRC error counter reading of first FTU board\\\hline
9230x00F & address of second FTU board and number of sent pings until response\\\hline
9240x010 & DNA of second FTU board bit 63 ... 48\\\hline
9250x011 & DNA of second FTU board bit 47 ... 32\\\hline
9260x012 & DNA of second FTU board bit 31 ... 16\\\hline
9270x013 & DNA of second FTU board bit 15 ... 0\\\hline
9280x014 & CRC error counter reading of second FTU board\\\hline
929... & ...\\\hline
9300x0F8 & CRC error counter reading of last FTU board\\\hline
931\caption{FTU list}
932\label{tab:FTU-list}
933\end{longtable}
934
935In case there is no response to a 'ping' for a certain FTU address, there are
936up to two repetitions. If there is still no answer, only zeros are written
937into the FTU list for this particular board. A responding FTU board gets a
938regular entry, including the number of 'ping' sent until response. The number
939of pings is coded together with the FTU board address as shown in table
940\ref{tab:FTU-crate-number-and-address}. The two bits 'pings\_0' and 'pings\_1'
941contain the number of 'pings' until response of an FTU board (coded in
942binary). The 'DNA' of the FTU board is the device DNA \cite{ds557, ds610,
943  wp267, wp266} of the FPGA on the responding FTU board. This is a unique 57
944bit serial number unambiguously identifying every Xilinx FPGA. In the most
945significant word (bit 63 ... 48) bits 63 down to 57 are filled with zeros.
946
947\begin{table}[h]
948\centering
949\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|}\hline
950Bit      & 15 ... 10 & 9 & 8 & 7 & 6 & 5 & ... & 0 \\\hline
951Content & x ... x & pings\_1 & pings\_0 & x & x & A5 & ... & A0 \\\hline
952\end{tabular}
953\caption{Address of FTU board and number of pings until response. In case
954  there is no response at all, this number is set to 0.}
955\label{tab:FTU-crate-number-and-address}
956\end{table}
957
958\chapter{FTU communication error handling}
959\label{cha:Error-handling}
960
961When the FTM board is communicating with a FTU board via RS-485, the FTU board
962has to respond within 2\,ms (after the last byte was transmitted). If this
963timeout expires, or the response sent back by the FTU board is incorrect, the
964FTM resends the datapacket after the timeout. If this second attempt is still
965unsuccessful, a third and last attempt will be made by the FTM board. An error
966message will be sent to the FTMcontrol whenever a FTU board does not send a
967correct answer after the first call by the FTM board. This message (see
968table~\ref{tab:error-message}) contains, after the standard header (see
969table~\ref{tab:FTM-header}), the number of calls until response (0 if no
970response at all), and the corresponding data packet which was sent to the FTU
971board. In order to avoid massive error messages for e.g. test setups with
972single FTUs, the 'active FTU list' can be employed to disable FTUs from the
973bus. In that case the FTM will not try to contact the corresponding boards.
974
975\begin{table}[h]
976  \centering
977  \begin{tabular}{|l|l|}\hline
978    word no & content\\\hline\hline
979    0x000 & number of calls until response (0 if no response at all)\\\hline
980    0x001 ... 0x01C & slow control data packet sent to FTU (28 words/bytes)\\\hline
981  \end{tabular}
982  \caption{FTU communication error message (after standard header); for a
983    description of the FTU data package, see \cite{FTUspecs}.}
984  \label{tab:error-message}
985\end{table}
986
987%---------------------------------------------------------------------------------
988
989\bibliographystyle{unsrt}
990%\bibliography{FTM-Com}
991
992\begin{thebibliography}{1}
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994\bibitem{DRS4}
995Paul Scherrer Institut PSI.
996\newblock {\em DRS4 9 Channel, 5 GSPS Switched Capacitor Array}.
997\newblock datasheet.
998
999\bibitem{LMK03000}
1000National Semiconductor Corporation.
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1003\newblock datasheet.
1004
1005\bibitem{FTM-Schematics}
1006ETH Z{\"u}rich, IPP.
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1008
1009\bibitem{W5300}
1010WIZnet Co.Ltd.
1011\newblock {\em W5300 Fully Hardwired Network protocol Embedded Ethernet
1012  Controller}, 2008.
1013\newblock datasheet.
1014
1015\bibitem{ds557}
1016Xilinx.
1017\newblock {\em Spartan-3AN FPGA Family Data Sheet}, 2009.
1018
1019\bibitem{ds610}
1020Xilinx.
1021\newblock {\em Spartan-3A DSP FPGA Family: Data Sheet}, 2009.
1022
1023\bibitem{wp267}
1024Xilinx.
1025\newblock {\em Advanced Security Schemes for Spartan-3A/3AN/3A DSP FPGAs},
1026  2007.
1027
1028\bibitem{wp266}
1029Xilinx.
1030\newblock {\em Security Solutions Using Spartan-3 Generation FPGAs}, 2008.
1031
1032\bibitem{MAX6662}
1033Maxim Integrated Products.
1034\newblock {\em 12-Bit plus Sign Temperature Sensor with SPI-Compatible Serial
1035  Interface MAX6662}, 2001.
1036\newblock datasheet.
1037
1038\bibitem{FTUspecs}
1039ETH Z{\"u}rich, IPP.
1040\newblock {\em FTU Firmware Specifications v3}, 2010.
1041
1042
1043\bibitem{FLD-Schematics}
1044ETH Z{\"u}rich, IPP.
1045\newblock {\em FLD Schematics, FACT light driver}, 2010.
1046
1047
1048\end{thebibliography}
1049
1050\end{document}
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