source: firmware/FTM/ethernet/DRAM_4096_16b_DRAM_4096_16b_a.vhd@ 11485

Last change on this file since 11485 was 10227, checked in by weitzel, 15 years ago
first version of FTM firmware including ethernet and FTU interface; still some debugging needed
File size: 5.3 KB
Line 
1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- This file is owned and controlled by Xilinx and must be used --
5-- solely for design, simulation, implementation and creation of --
6-- design files limited to Xilinx devices or technologies. Use --
7-- with non-Xilinx devices or technologies is expressly prohibited --
8-- and immediately terminates your license. --
9-- --
10-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
11-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
12-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
13-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
14-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
15-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
16-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
17-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
18-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
19-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
20-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
21-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
22-- FOR A PARTICULAR PURPOSE. --
23-- --
24-- Xilinx products are not intended for use in life support --
25-- appliances, devices, or systems. Use in such applications are --
26-- expressly prohibited. --
27-- --
28-- (c) Copyright 1995-2007 Xilinx, Inc. --
29-- All rights reserved. --
30--------------------------------------------------------------------------------
31-- You must compile the wrapper file DRAM_4096_16b.vhd when simulating
32-- the core, DRAM_4096_16b. When compiling the wrapper file, be sure to
33-- reference the XilinxCoreLib VHDL simulation library. For detailed
34-- instructions, please refer to the "CORE Generator Help".
35
36-- The synthesis directives "translate_off/translate_on" specified
37-- below are supported by Xilinx, Mentor Graphics and Synplicity
38-- synthesis tools. Ensure they are correct for your synthesis tool(s).
39
40-- hds interface_start
41LIBRARY ieee;
42USE ieee.std_logic_1164.ALL;
43-- synthesis translate_off
44LIBRARY XilinxCoreLib;
45
46-- synthesis translate_on
47--
48ENTITY DRAM_4096_16b IS
49 PORT(
50 clka : IN std_logic;
51 dina : IN std_logic_VECTOR (15 DOWNTO 0);
52 addra : IN std_logic_VECTOR (11 DOWNTO 0);
53 wea : IN std_logic_VECTOR (0 DOWNTO 0);
54 clkb : IN std_logic;
55 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
56 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
57 );
58
59-- Declarations
60
61END DRAM_4096_16b ;
62-- hds interface_end
63
64ARCHITECTURE DRAM_4096_16b_a OF DRAM_4096_16b IS
65
66-- hds translate_off
67
68-- synthesis translate_off
69component wrapped_DRAM_4096_16b
70 port (
71 clka: IN std_logic;
72 dina: IN std_logic_VECTOR(15 downto 0);
73 addra: IN std_logic_VECTOR(11 downto 0);
74 wea: IN std_logic_VECTOR(0 downto 0);
75 clkb: IN std_logic;
76 addrb: IN std_logic_VECTOR(11 downto 0);
77 doutb: OUT std_logic_VECTOR(15 downto 0));
78end component;
79
80-- Configuration specification
81 for all : wrapped_DRAM_4096_16b use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral)
82 generic map(
83 c_has_regceb => 0,
84 c_has_regcea => 0,
85 c_mem_type => 1,
86 c_prim_type => 1,
87 c_sinita_val => "0",
88 c_read_width_b => 16,
89 c_family => "spartan3",
90 c_read_width_a => 16,
91 c_disable_warn_bhv_coll => 0,
92 c_write_mode_b => "READ_FIRST",
93 c_init_file_name => "no_coe_file_loaded",
94 c_write_mode_a => "READ_FIRST",
95 c_mux_pipeline_stages => 0,
96 c_has_mem_output_regs_b => 0,
97 c_load_init_file => 0,
98 c_xdevicefamily => "spartan3a",
99 c_has_mem_output_regs_a => 0,
100 c_write_depth_b => 4096,
101 c_write_depth_a => 4096,
102 c_has_ssrb => 0,
103 c_has_mux_output_regs_b => 0,
104 c_has_ssra => 0,
105 c_has_mux_output_regs_a => 0,
106 c_addra_width => 12,
107 c_addrb_width => 12,
108 c_default_data => "0",
109 c_use_ecc => 0,
110 c_algorithm => 1,
111 c_disable_warn_bhv_range => 0,
112 c_write_width_b => 16,
113 c_write_width_a => 16,
114 c_read_depth_b => 4096,
115 c_read_depth_a => 4096,
116 c_byte_size => 9,
117 c_sim_collision_check => "ALL",
118 c_use_ramb16bwer_rst_bhv => 0,
119 c_common_clk => 0,
120 c_wea_width => 1,
121 c_has_enb => 0,
122 c_web_width => 1,
123 c_has_ena => 0,
124 c_sinitb_val => "0",
125 c_use_byte_web => 0,
126 c_use_byte_wea => 0,
127 c_use_default_data => 1);
128-- synthesis translate_on
129
130-- hds translate_on
131
132BEGIN
133
134-- hds translate_off
135
136-- synthesis translate_off
137U0 : wrapped_DRAM_4096_16b
138 port map (
139 clka => clka,
140 dina => dina,
141 addra => addra,
142 wea => wea,
143 clkb => clkb,
144 addrb => addrb,
145 doutb => doutb);
146-- synthesis translate_on
147
148
149-- hds translate_on
150
151END DRAM_4096_16b_a;
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