source: firmware/FTM/ethernet/cram_control_beha.vhd@ 10256

Last change on this file since 10256 was 10256, checked in by weitzel, 11 years ago
new version of FTM ethernet module; first version of clock conditioner
File size: 13.6 KB
Line 
1--
2-- VHDL Architecture FACT_FTM_lib.cram_control.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 14:42:24 01.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10-- updated by Q. Weitzel, March 14, 2011
11--
12
13LIBRARY ieee;
14USE ieee.std_logic_1164.all;
15USE ieee.std_logic_arith.all;
16USE IEEE.STD_LOGIC_UNSIGNED.all;
17-- LIBRARY FACT_FTM_lib;
18-- USE FACT_FTM_lib.ftm_array_types.all;
19-- USE FACT_FTM_lib.ftm_constants.all;
20library ftm_definitions;
21USE ftm_definitions.ftm_array_types.all;
22USE ftm_definitions.ftm_constants.all;
23
24ENTITY cram_control IS
25 PORT(
26 clk : IN std_logic;
27 led : OUT std_logic_vector (7 downto 0) := X"00";
28 cram_data_in : OUT std_logic_vector (15 downto 0) := (others => '0');
29 cram_data_out : IN std_logic_vector (15 downto 0);
30 cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0) := (others => '0');
31 cram_we : OUT std_logic_vector (0 downto 0) := "0";
32 sd_write, sd_read, sd_read_ftu : IN std_logic;
33 sd_busy : OUT std_logic := '1';
34 sd_started, sd_started_ftu : OUT std_logic := '0';
35 sd_ready : OUT std_logic := '0';
36 sd_data_in : IN std_logic_vector (15 downto 0);
37 sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0');
38 sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0);
39
40 config_start_cc : IN std_logic;
41 config_started_cc : OUT std_logic := '0';
42 config_ready_cc : OUT std_logic := '0';
43
44 -- data from config ram
45 general_settings : OUT std_logic_vector (15 downto 0) := (others => '0');
46 lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0');
47 lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0');
48 lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0');
49 lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0');
50 lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
51 lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
52 coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0');
53 coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0');
54 trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
55 timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0');
56 dead_time : OUT std_logic_vector (15 downto 0) := (others => '0');
57 cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0');
58 cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0');
59 cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0');
60 cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0');
61 cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0');
62 cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0');
63 cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0');
64 cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0');
65 coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0');
66 coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0');
67 ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0');
68 ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0');
69 ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0');
70 ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0')
71 );
72END cram_control ;
73
74ARCHITECTURE beha OF cram_control IS
75
76 type state_cram_proc_type is (CR_INIT, CR_INIT_01, CR_INIT_02, CR_INIT_03,
77 CR_CONFIG, CR_CONFIG_START, CR_CONFIG_01,
78 CR_IDLE, CR_WRITE_START, CR_WRITE_END, CR_READ_START, CR_READ_WAIT, CR_READ_END,
79 CR_DOUT_WIZ_START, CR_DOUT_WIZ_END, CR_DOUT_FTU_START, CR_DOUT_FTU_END);
80 signal state_cram_proc : state_cram_proc_type := CR_INIT;
81 signal next_state : state_cram_proc_type := CR_IDLE;
82
83 signal local_sd_addr : std_logic_vector (11 downto 0) := X"000";
84 signal local_sd_data : std_logic_vector (15 downto 0);
85-- signal addr_cnt : integer range 0 to 4096 := 0;
86 signal addr_cnt : std_logic_vector (11 downto 0) := X"000";
87 signal ftu_cnt : integer range 0 to SD_FTU_NUM := 0;
88 signal ftu_active_cnt : integer range 0 to SD_FTU_ACTIVE_NUM := 0;
89
90BEGIN
91
92 cram_proc : process (clk)
93 begin
94 if rising_edge (clk) then
95 case state_cram_proc is
96
97 when CR_INIT =>
98 addr_cnt <= X"000";
99 state_cram_proc <= CR_INIT_01;
100
101 -- general part of static data block
102 when CR_INIT_01 =>
103 if (addr_cnt < SD_BLOCK_SIZE_GENERAL) then
104 local_sd_addr <= addr_cnt;
105 local_sd_data <= sd_block_default_array (conv_integer (addr_cnt));
106 addr_cnt <= addr_cnt + 1;
107 next_state <= CR_INIT_01;
108 state_cram_proc <= CR_WRITE_START;
109 else
110 addr_cnt <= X"000";
111 ftu_cnt <= 0;
112 state_cram_proc <= CR_INIT_02;
113 end if;
114
115 -- defaults for FTUs
116 when CR_INIT_02 =>
117 if (ftu_cnt < SD_FTU_NUM) then
118 if (addr_cnt < SD_FTU_DATA_SIZE) then
119 local_sd_addr <= SD_FTU_BASE_ADDR + (ftu_cnt * SD_FTU_DATA_SIZE) + addr_cnt;
120 -- only for testing
121 -- local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt)) OR (conv_std_logic_vector (ftu_cnt, 8) & X"00");
122 -- for FTM-Board
123 local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt));
124 -- --
125 addr_cnt <= addr_cnt + 1;
126 next_state <= CR_INIT_02;
127 state_cram_proc <= CR_WRITE_START;
128 else
129 addr_cnt <= X"000";
130 ftu_cnt <= ftu_cnt + 1;
131 end if;
132 else
133 addr_cnt <= X"000";
134 state_cram_proc <= CR_INIT_03;
135 end if;
136
137 -- defaults for active FTU lists
138 when CR_INIT_03 =>
139 if (ftu_active_cnt < SD_FTU_ACTIVE_NUM) then
140 local_sd_addr <= SD_FTU_ACTIVE_BASE_ADDR + conv_std_logic_vector (ftu_active_cnt, 12);
141 -- only for testing
142 -- local_sd_data <= conv_std_logic_vector (ftu_active_cnt, 16);
143 -- for FTM-Board
144 local_sd_data <= sd_block_default_ftu_active_list (ftu_active_cnt);
145 -- --
146 ftu_active_cnt <= ftu_active_cnt + 1;
147 next_state <= CR_INIT_03;
148 state_cram_proc <= CR_WRITE_START;
149 else
150 ftu_active_cnt <= 0;
151 state_cram_proc <= CR_CONFIG;
152 end if;
153
154
155 when CR_CONFIG =>
156 if (config_start_cc = '1') then
157 config_ready_cc <= '0';
158 config_started_cc <= '1';
159 state_cram_proc <= CR_CONFIG_START;
160 end if;
161
162 when CR_CONFIG_START =>
163 if (addr_cnt < SD_BLOCK_SIZE) then
164 if ((addr_cnt < SD_FTU_BASE_ADDR) OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)) then
165 local_sd_addr <= addr_cnt;
166 next_state <= CR_CONFIG_01;
167 state_cram_proc <= CR_READ_START;
168 elsif (addr_cnt = SD_FTU_BASE_ADDR) then
169 addr_cnt <= SD_FTU_ACTIVE_BASE_ADDR;
170 end if;
171 else
172 addr_cnt <= X"000";
173 config_started_cc <= '0';
174 config_ready_cc <= '1';
175 state_cram_proc <= CR_IDLE;
176 end if;
177
178 when CR_CONFIG_01 =>
179 state_cram_proc <= CR_CONFIG_START;
180 addr_cnt <= addr_cnt + 1;
181 case addr_cnt is
182 when SD_ADDR_general_settings =>
183 general_settings <= local_sd_data;
184 when SD_ADDR_led =>
185 led <= local_sd_data (7 downto 0);
186 when SD_ADDR_lp_pt_freq =>
187 lp_pt_freq <= local_sd_data;
188 when SD_ADDR_lp_pt_ratio =>
189 lp_pt_ratio <= local_sd_data;
190 when SD_ADDR_lp1_amplitude =>
191 lp1_amplitude <= local_sd_data;
192 when SD_ADDR_lp2_amplitude =>
193 lp2_amplitude <= local_sd_data;
194 when SD_ADDR_lp1_delay =>
195 lp1_delay <= local_sd_data;
196 when SD_ADDR_lp2_delay =>
197 lp2_delay <= local_sd_data;
198 when SD_ADDR_coin_n_p =>
199 coin_n_p <= local_sd_data;
200 when SD_ADDR_coin_n_c =>
201 coin_n_c <= local_sd_data;
202 when SD_ADDR_trigger_delay =>
203 trigger_delay <= local_sd_data;
204 when SD_ADDR_timemarker_delay =>
205 timemarker_delay <= local_sd_data;
206 when SD_ADDR_dead_time =>
207 dead_time <= local_sd_data;
208 when SD_ADDR_cc_R0_HI =>
209 cc_R0 (31 downto 16) <= local_sd_data;
210 when SD_ADDR_cc_R0_LO =>
211 cc_R0 (15 downto 0) <= local_sd_data;
212 when SD_ADDR_cc_R1_HI =>
213 cc_R1 (31 downto 16) <= local_sd_data;
214 when SD_ADDR_cc_R1_LO =>
215 cc_R1 (15 downto 0) <= local_sd_data;
216 when SD_ADDR_cc_R8_HI =>
217 cc_R8 (31 downto 16) <= local_sd_data;
218 when SD_ADDR_cc_R8_LO =>
219 cc_R8 (15 downto 0) <= local_sd_data;
220 when SD_ADDR_cc_R9_HI =>
221 cc_R9 (31 downto 16) <= local_sd_data;
222 when SD_ADDR_cc_R9_LO =>
223 cc_R9 (15 downto 0) <= local_sd_data;
224 when SD_ADDR_cc_R11_HI =>
225 cc_R11 (31 downto 16) <= local_sd_data;
226 when SD_ADDR_cc_R11_LO =>
227 cc_R11 (15 downto 0) <= local_sd_data;
228 when SD_ADDR_cc_R13_HI =>
229 cc_R13 (31 downto 16) <= local_sd_data;
230 when SD_ADDR_cc_R13_LO =>
231 cc_R13 (15 downto 0) <= local_sd_data;
232 when SD_ADDR_cc_R14_HI =>
233 cc_R14 (31 downto 16) <= local_sd_data;
234 when SD_ADDR_cc_R14_LO =>
235 cc_R14 (15 downto 0) <= local_sd_data;
236 when SD_ADDR_cc_R15_HI =>
237 cc_R15 (31 downto 16) <= local_sd_data;
238 when SD_ADDR_cc_R15_LO =>
239 cc_R15 (15 downto 0) <= local_sd_data;
240 when SD_ADDR_coin_win_p =>
241 coin_win_p <= local_sd_data;
242 when SD_ADDR_coin_win_c =>
243 coin_win_c <= local_sd_data;
244 when SD_ADDR_ftu_active_cr0 =>
245 ftu_active_cr0 <= local_sd_data;
246 when SD_ADDR_ftu_active_cr1 =>
247 ftu_active_cr1 <= local_sd_data;
248 when SD_ADDR_ftu_active_cr2 =>
249 ftu_active_cr2 <= local_sd_data;
250 when SD_ADDR_ftu_active_cr3 =>
251 ftu_active_cr3 <= local_sd_data;
252 when others =>
253 null;
254 end case;
255
256 when CR_IDLE =>
257 sd_busy <= '0';
258
259 if (config_start_cc = '1') then
260 sd_busy <= '1';
261 state_cram_proc <= CR_CONFIG;
262
263 elsif (sd_write = '1') then
264 sd_busy <= '1';
265 sd_started <= '1';
266 sd_ready <= '0';
267 local_sd_addr <= sd_addr;
268 local_sd_data <= sd_data_in;
269 next_state <= CR_IDLE;
270 state_cram_proc <= CR_WRITE_START;
271
272 elsif (sd_read = '1') then
273 sd_busy <= '1';
274 sd_started <= '1';
275 sd_ready <= '0';
276 local_sd_addr <= sd_addr;
277 next_state <= CR_DOUT_WIZ_START;
278 state_cram_proc <= CR_READ_START;
279
280 elsif (sd_read_ftu = '1') then
281 sd_busy <= '1';
282 sd_started_ftu <= '1';
283 sd_ready <= '0';
284 local_sd_addr <= sd_addr_ftu;
285 next_state <= CR_DOUT_FTU_START;
286 state_cram_proc <= CR_READ_START;
287 end if;
288
289
290 when CR_DOUT_FTU_START =>
291 sd_data_out_ftu <= local_sd_data;
292 sd_ready <= '1';
293 state_cram_proc <= CR_DOUT_FTU_END;
294
295 when CR_DOUT_FTU_END =>
296 if (sd_read_ftu <= '0') then
297 sd_started_ftu <= '0';
298 state_cram_proc <= CR_IDLE;
299 end if;
300
301 when CR_DOUT_WIZ_START =>
302 sd_data_out <= local_sd_data;
303 sd_ready <= '1';
304 state_cram_proc <= CR_DOUT_WIZ_END;
305
306 when CR_DOUT_WIZ_END =>
307 if (sd_read <= '0') then
308 sd_started <= '0';
309 state_cram_proc <= CR_IDLE;
310 end if;
311
312
313 -- --
314 -- write to config ram
315 -- --
316 when CR_WRITE_START =>
317 cram_addr_in <= local_sd_addr;
318 cram_data_in <= local_sd_data;
319 cram_we <= "1";
320 state_cram_proc <= CR_WRITE_END;
321
322 when CR_WRITE_END =>
323 cram_we <= "0";
324 if (sd_write = '0') then
325 sd_started <= '0';
326 sd_ready <= '1';
327 state_cram_proc <= next_state;
328 end if;
329
330 -- --
331 -- read from config ram
332 -- --
333 when CR_READ_START =>
334 cram_addr_out <= local_sd_addr;
335 state_cram_proc <= CR_READ_WAIT;
336
337 when CR_READ_WAIT =>
338 state_cram_proc <= CR_READ_END;
339
340 when CR_READ_END =>
341 local_sd_data <= cram_data_out;
342 state_cram_proc <= next_state;
343
344
345 end case;
346 end if; -- rising edge
347 end process cram_proc;
348
349END ARCHITECTURE beha;
350
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