source: firmware/FTM/ethernet/dd_write_general_modul_beha.vhd @ 10441

Last change on this file since 10441 was 10441, checked in by weitzel, 9 years ago
new FTM firmware featuring e.g. start/stop run commands and new header
  • Property svn:executable set to *
File size: 6.4 KB
Line 
1--
2-- VHDL Architecture FACT_FTM_lib.dd_write_general_modul.beha
3--
4-- Created:
5--          by - kai.UNKNOWN (E5PCXX)
6--          at - 11:27:33 02.03.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10LIBRARY ieee;
11USE ieee.std_logic_1164.all;
12USE ieee.std_logic_arith.all;
13USE IEEE.STD_LOGIC_UNSIGNED.all;
14
15library ftm_definitions;
16USE ftm_definitions.ftm_array_types.all;
17USE ftm_definitions.ftm_constants.all;
18
19ENTITY dd_write_general_modul IS
20PORT(
21  clk                       : IN std_logic;
22  dd_write_general          : IN std_logic;
23  dd_write_general_started  : OUT std_logic := '0';
24  dd_write_general_ready    : OUT std_logic := '0';
25  dd_busy                   : IN  std_logic;
26  dd_write                  : OUT std_logic := '0';
27  dd_started                : IN  std_logic;
28  dd_ready                  : IN  std_logic;
29  dd_addr                   : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
30  dd_data                   : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
31  get_ot_counter            : OUT std_logic := '0';
32  get_ot_counter_started    : IN std_logic;
33  get_ot_counter_ready      : IN std_logic;
34  on_time_counter           : IN std_logic_vector (47 DOWNTO 0);
35  temp_sensor_ready         : IN std_logic;
36  temp_sensor_array         : IN sensor_array_type
37  );
38END ENTITY dd_write_general_modul;
39
40--
41ARCHITECTURE beha OF dd_write_general_modul IS
42
43  type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE,
44                                         WGP_OT_CNT, WGP_OT_CNT_END,
45                                         WGP_WRITE_COUNTER_00, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03,
46                                         WGP_WRITE_TEMP_01, WGP_WRITE_TEMP_02, WGP_WRITE_TEMP_03, WGP_WRITE_TEMP_04, WGP_WRITE_READY, WRITE_TO_DD_ADDR);
47  type state_write_dd_type is (WRITE_DD_START, WRITE_DD_WAIT, WRITE_DD_END);
48
49  signal state_write_general_proc : state_write_general_proc_type := WGP_INIT;
50  signal next_state_dd : state_write_general_proc_type := WGP_INIT;
51  signal state_write_dd : state_write_dd_type := WRITE_DD_START;
52
53  signal local_dd_addr : std_logic_vector (11 DOWNTO 0) := (others => '0');
54  signal local_dd_data : std_logic_vector (15 DOWNTO 0) := (others => '0');
55
56
57BEGIN
58  write_general_proc : process (clk)
59  begin
60    if rising_edge (clk) then
61      case state_write_general_proc is
62     
63        when WGP_INIT =>
64          state_write_general_proc <= WGP_CONFIG;
65         
66        when WGP_CONFIG =>
67          state_write_general_proc <= WGP_IDLE;
68         
69        when WGP_IDLE =>
70          if (dd_write_general = '1') then
71            dd_write_general_started <= '1';
72            dd_write_general_ready <= '0';
73            get_ot_counter <= '1';
74            state_write_general_proc <= WGP_OT_CNT;
75          end if;
76         
77        when WGP_OT_CNT =>
78          if (get_ot_counter_started = '1') then
79            get_ot_counter <= '0';
80            state_write_general_proc <= WGP_OT_CNT_END;
81          end if;
82
83        when WGP_OT_CNT_END =>
84          if (get_ot_counter_ready = '1') then
85            state_write_general_proc <= WGP_WRITE_COUNTER_00;
86          end if;
87         
88        when WGP_WRITE_COUNTER_00 =>
89          local_dd_addr <= X"000";
90          local_dd_data <= X"0000";
91          next_state_dd <= WGP_WRITE_COUNTER_01;
92          state_write_general_proc <= WRITE_TO_DD_ADDR;
93       
94        when WGP_WRITE_COUNTER_01 =>
95          local_dd_addr <= X"001";
96          local_dd_data <= on_time_counter (47 DOWNTO 32);
97          next_state_dd <= WGP_WRITE_COUNTER_02;
98          state_write_general_proc <= WRITE_TO_DD_ADDR;
99       
100        when WGP_WRITE_COUNTER_02 =>
101          local_dd_addr <= X"002";
102          local_dd_data <= on_time_counter (31 DOWNTO 16);
103          next_state_dd <= WGP_WRITE_COUNTER_03;
104          state_write_general_proc <= WRITE_TO_DD_ADDR;
105       
106        when WGP_WRITE_COUNTER_03 =>
107          local_dd_addr <= X"003";
108          local_dd_data <= on_time_counter (15 DOWNTO 0);
109          next_state_dd <= WGP_WRITE_TEMP_01;
110          state_write_general_proc <= WRITE_TO_DD_ADDR;
111       
112        when WGP_WRITE_TEMP_01 =>
113          if (temp_sensor_ready = '1') then
114            local_dd_addr <= X"004";
115            local_dd_data <= conv_std_logic_vector (temp_sensor_array (0), 16);
116            next_state_dd <= WGP_WRITE_TEMP_02;
117            state_write_general_proc <= WRITE_TO_DD_ADDR;
118          end if;
119       
120        when WGP_WRITE_TEMP_02 =>
121          if (temp_sensor_ready = '1') then
122            local_dd_addr <= X"005";
123            local_dd_data <= conv_std_logic_vector (temp_sensor_array (1), 16);
124            next_state_dd <= WGP_WRITE_TEMP_03;
125            state_write_general_proc <= WRITE_TO_DD_ADDR;
126          end if;
127       
128        when WGP_WRITE_TEMP_03 =>
129          if (temp_sensor_ready = '1') then
130            local_dd_addr <= X"006";
131            local_dd_data <= conv_std_logic_vector (temp_sensor_array (2), 16);
132            next_state_dd <= WGP_WRITE_TEMP_04;
133            state_write_general_proc <= WRITE_TO_DD_ADDR;
134          end if;
135       
136        when WGP_WRITE_TEMP_04 =>
137          if (temp_sensor_ready = '1') then
138            local_dd_addr <= X"007";
139            local_dd_data <= conv_std_logic_vector (temp_sensor_array (3), 16);
140            next_state_dd <= WGP_WRITE_READY;
141            state_write_general_proc <= WRITE_TO_DD_ADDR;
142          end if;
143         
144        when WGP_WRITE_READY =>
145          if (dd_write_general = '0') then
146            dd_write_general_started <= '0';
147            dd_write_general_ready <= '1';
148            state_write_general_proc <= WGP_IDLE;
149          end if;
150       
151        -- write to dynamic data block
152        when WRITE_TO_DD_ADDR =>
153          case state_write_dd is
154            when WRITE_DD_START =>
155              if (dd_busy = '0') then
156                dd_addr <= local_dd_addr;
157                dd_data <= local_dd_data;
158                dd_write <= '1';
159                state_write_dd <= WRITE_DD_WAIT;
160              end if;
161            when WRITE_DD_WAIT =>
162              if (dd_started = '1') then
163                dd_write <= '0';
164                state_write_dd <= WRITE_DD_END;
165              end if;
166            when WRITE_DD_END =>
167              if (dd_ready = '1') then
168                state_write_dd <= WRITE_DD_START;
169                state_write_general_proc <= next_state_dd;
170              end if;
171          end case;
172       
173      end case;
174    end if;
175  end process write_general_proc;
176
177END ARCHITECTURE beha;
178
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