source: firmware/FTM/ethernet/dram_control_beha.vhd@ 10639

Last change on this file since 10639 was 10256, checked in by weitzel, 15 years ago
new version of FTM ethernet module; first version of clock conditioner
File size: 6.4 KB
Line 
1--
2-- VHDL Architecture FACT_FTM_lib.dram_control.beha
3--
4-- Created:
5-- by - kai.UNKNOWN (E5PCXX)
6-- at - 11:39:22 23.02.2011
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10
11LIBRARY ieee;
12USE ieee.std_logic_1164.all;
13USE ieee.std_logic_arith.all;
14USE IEEE.STD_LOGIC_UNSIGNED.all;
15-- LIBRARY FACT_FTM_lib;
16-- USE FACT_FTM_lib.ftm_array_types.all;
17-- USE FACT_FTM_lib.ftm_constants.all;
18library ftm_definitions;
19USE ftm_definitions.ftm_array_types.all;
20USE ftm_definitions.ftm_constants.all;
21
22ENTITY dram_control IS
23 PORT(
24 clk : IN std_logic;
25 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
26 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
27 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
28 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
29 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
30 dd_block_start : IN std_logic;
31 dd_block_start_ftu : IN std_logic;
32 dd_block_start_ack : OUT std_logic := '0';
33 dd_block_start_ack_ftu : OUT std_logic := '0';
34 dd_block_ready : IN std_logic;
35 dd_block_ready_ftu : IN std_logic;
36 dd_read : IN std_logic;
37 dd_write_ftu : IN std_logic;
38 dd_write_general : IN std_logic;
39 dd_busy : OUT std_logic := '1';
40 dd_started : OUT std_logic := '0';
41 dd_started_ftu : OUT std_logic := '0';
42 dd_started_general : OUT std_logic := '0';
43 dd_ready : OUT std_logic := '0';
44 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
45 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
46 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0);
47 dd_addr : IN std_logic_vector (11 DOWNTO 0);
48 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
49 dd_addr_general : IN std_logic_vector (11 DOWNTO 0)
50 );
51
52-- Declarations
53
54END dram_control ;
55
56--
57ARCHITECTURE beha OF dram_control IS
58
59 type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END_FTU, DR_WRITE_END_GENERAL,
60 DR_READ_START, DR_READ_WAIT, DR_READ_END);
61 type state_dd_block_proc_type is (DD_BLOCK_IDLE, DD_BLOCK_WAIT_WIZ, DD_BLOCK_WAIT_FTU);
62
63
64 signal state_dram_proc : state_dram_proc_type := DR_INIT;
65 signal next_state : state_dram_proc_type := DR_IDLE;
66 signal write_end_state : state_dram_proc_type := DR_WRITE_END_FTU;
67
68 signal state_dd_block_proc : state_dd_block_proc_type := DD_BLOCK_IDLE;
69
70 signal local_addr : std_logic_vector (11 downto 0) := X"000";
71 signal local_data : std_logic_vector (15 downto 0);
72
73BEGIN
74
75 dd_block_proc : process (clk)
76 begin
77 if rising_edge (clk) then
78 case state_dd_block_proc is
79
80 when DD_BLOCK_IDLE =>
81 if (dd_block_start = '1') then
82 dd_block_start_ack <= '1';
83 state_dd_block_proc <= DD_BLOCK_WAIT_WIZ;
84 elsif (dd_block_start_ftu = '1') then
85 dd_block_start_ack_ftu <= '1';
86 state_dd_block_proc <= DD_BLOCK_WAIT_FTU;
87 end if;
88
89 when DD_BLOCK_WAIT_WIZ =>
90 if (dd_block_ready = '1') then
91 dd_block_start_ack <= '0';
92 state_dd_block_proc <= DD_BLOCK_IDLE;
93 end if;
94
95 when DD_BLOCK_WAIT_FTU =>
96 if (dd_block_ready_ftu = '1') then
97 dd_block_start_ack_ftu <= '0';
98 state_dd_block_proc <= DD_BLOCK_IDLE;
99 end if;
100
101 end case;
102 end if;
103 end process dd_block_proc;
104
105 dram_proc : process (clk)
106 begin
107 if rising_edge (clk) then
108 case state_dram_proc is
109
110 when DR_INIT =>
111 state_dram_proc <= DR_CONFIG;
112
113 when DR_CONFIG =>
114 state_dram_proc <= DR_IDLE;
115
116 when DR_IDLE =>
117 dd_busy <= '0';
118
119 if (dd_read = '1') then
120 dd_busy <= '1';
121 dd_started <= '1';
122 dd_ready <= '0';
123 local_addr <= dd_addr;
124 next_state <= DR_DOUT_WIZ_START;
125 state_dram_proc <= DR_READ_START;
126
127 elsif (dd_write_ftu = '1') then
128 dd_busy <= '1';
129 dd_started_ftu <= '1';
130 dd_ready <= '0';
131 local_addr <= dd_addr_ftu;
132 local_data <= dd_data_in_ftu;
133 next_state <= DR_IDLE;
134 write_end_state <= DR_WRITE_END_FTU;
135 state_dram_proc <= DR_WRITE_START;
136
137 elsif (dd_write_general = '1') then
138 dd_busy <= '1';
139 dd_started_general <= '1';
140 dd_ready <= '0';
141 local_addr <= dd_addr_general;
142 local_data <= dd_data_in_general;
143 next_state <= DR_IDLE;
144 write_end_state <= DR_WRITE_END_GENERAL;
145 state_dram_proc <= DR_WRITE_START;
146 end if;
147
148
149 when DR_DOUT_WIZ_START =>
150 dd_data_out <= local_data;
151 dd_ready <= '1';
152 state_dram_proc <= DR_DOUT_WIZ_END;
153
154 when DR_DOUT_WIZ_END =>
155 if (dd_read <= '0') then
156 dd_started <= '0';
157 state_dram_proc <= DR_IDLE;
158 end if;
159
160 -- --
161 -- write to dynamic data ram
162 -- --
163 when DR_WRITE_START =>
164 dram_addr_in <= local_addr;
165 dram_data_in <= local_data;
166 dram_we <= "1";
167 state_dram_proc <= write_end_state;
168
169 when DR_WRITE_END_FTU =>
170 dram_we <= "0";
171 if (dd_write_ftu = '0') then
172 dd_started_ftu <= '0';
173 dd_ready <= '1';
174 state_dram_proc <= next_state;
175 end if;
176
177 when DR_WRITE_END_GENERAL =>
178 dram_we <= "0";
179 if (dd_write_general = '0') then
180 dd_started_general <= '0';
181 dd_ready <= '1';
182 state_dram_proc <= next_state;
183 end if;
184
185 -- --
186 -- read from dynamic data ram
187 -- --
188 when DR_READ_START =>
189 dram_addr_out <= local_addr;
190 state_dram_proc <= DR_READ_WAIT;
191
192 when DR_READ_WAIT =>
193 state_dram_proc <= DR_READ_END;
194
195 when DR_READ_END =>
196 local_data <= dram_data_out;
197 state_dram_proc <= next_state;
198
199
200 end case;
201 end if; -- rising edge
202 end process dram_proc;
203
204END ARCHITECTURE beha;
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