1 | --
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2 | -- VHDL Architecture FACT_FTM_lib.eth_config_modul.beha
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3 | --
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4 | -- Created:
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5 | -- by - kai.UNKNOWN (E5PCXX)
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6 | -- at - 14:52:32 15.02.2011
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7 | --
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8 | -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
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9 | --
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10 | LIBRARY ieee;
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11 | USE ieee.std_logic_1164.all;
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12 | USE ieee.std_logic_arith.all;
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13 | USE IEEE.STD_LOGIC_UNSIGNED.all;
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14 | -- LIBRARY FACT_FTM_lib;
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15 | -- USE FACT_FTM_lib.ftm_array_types.all;
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16 | -- USE FACT_FTM_lib.ftm_constants.all;
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17 | library ftm_definitions;
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18 | USE ftm_definitions.ftm_array_types.all;
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19 | USE ftm_definitions.ftm_constants.all;
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20 |
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21 | ENTITY eth_config_modul IS
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22 | PORT(
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23 | clk : IN std_logic;
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24 | config_start_eth : IN std_logic;
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25 | config_started_eth : OUT std_logic := '0';
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26 | config_ready_eth : OUT std_logic := '0';
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27 |
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28 | config_start_cc : OUT std_logic := '0';
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29 | config_started_cc : IN std_logic;
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30 | config_ready_cc : IN std_logic
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31 | );
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32 | END ENTITY eth_config_modul;
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33 |
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34 | --
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35 | ARCHITECTURE beha OF eth_config_modul IS
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36 |
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37 | type state_config_proc_type is (CP_IDLE, CP_CONFIG_START, CP_CONFIG_01, CP_CONFIG_END);
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38 | signal state_config_proc : state_config_proc_type := CP_IDLE;
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39 |
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40 | BEGIN
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41 |
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42 | config_proc : process (clk)
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43 | begin
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44 | if rising_edge (clk) then
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45 | case state_config_proc is
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46 |
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47 | when CP_IDLE =>
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48 | if (config_start_eth = '1') then
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49 | config_ready_eth <= '0';
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50 | config_started_eth <= '1';
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51 | state_config_proc <= CP_CONFIG_START;
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52 | end if;
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53 |
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54 | when CP_CONFIG_START =>
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55 | config_start_cc <= '1';
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56 | if (config_started_cc = '1') then
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57 | config_start_cc <= '0';
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58 | state_config_proc <= CP_CONFIG_01;
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59 | end if;
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60 |
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61 | when CP_CONFIG_01 =>
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62 | if (config_ready_cc = '1') then
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63 | state_config_proc <= CP_CONFIG_END;
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64 | end if;
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65 |
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66 | when CP_CONFIG_END =>
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67 | config_started_eth <= '0';
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68 | config_ready_eth <= '1';
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69 | state_config_proc <= CP_IDLE;
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70 |
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71 |
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72 | end case;
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73 | end if;
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74 | end process config_proc;
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75 |
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76 | END ARCHITECTURE beha;
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77 |
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