source: firmware/FTM/ethernet/ethernet_modul_beha.vhd@ 17826

Last change on this file since 17826 was 11485, checked in by weitzel, 14 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 37.7 KB
Line 
1-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 13:50:41 30.06.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12library ftm_definitions;
13USE ftm_definitions.ftm_array_types.all;
14USE ftm_definitions.ftm_constants.all;
15
16ENTITY ethernet_modul IS
17 PORT(
18 wiz_reset : OUT std_logic := '1';
19 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
20 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
21 wiz_cs : OUT std_logic := '1';
22 wiz_wr : OUT std_logic := '1';
23 wiz_rd : OUT std_logic := '1';
24 wiz_int : IN std_logic;
25 clk : IN std_logic;
26 sd_ready : OUT std_logic;
27 sd_busy : OUT std_logic;
28 led : OUT std_logic_vector (7 DOWNTO 0);
29 sd_read_ftu : IN std_logic;
30 sd_started_ftu : OUT std_logic := '0';
31 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
32 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
33 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
34 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
35 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
36 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
37 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
38 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
39 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
40 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
41 dead_time : OUT std_logic_vector (15 DOWNTO 0);
42 -- data from config ram
43 general_settings : OUT std_logic_vector (15 DOWNTO 0);
44 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
45 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
46 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
47 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
48 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
49 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
50 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
51 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
52 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
53 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
54 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
55 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
56 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
57 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
58 new_config : OUT std_logic := '0';
59 config_started : IN std_logic;
60 config_start_eth : IN std_logic;
61 config_started_eth : OUT std_logic := '0';
62 config_ready_eth : OUT std_logic := '0';
63 config_started_ack : OUT std_logic := '0';
64 fl_busy : OUT std_logic;
65 fl_ready : OUT std_logic;
66 fl_write_ftu : IN std_logic;
67 fl_started_ftu : OUT std_logic := '0';
68 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
69 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
70 --
71 ping_ftu_start : OUT std_logic := '0';
72 ping_ftu_started : IN std_logic;
73 ping_ftu_ready : IN std_logic;
74 dd_write_ftu : IN std_logic;
75 dd_started_ftu : OUT std_logic := '0';
76 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
77 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
78 dd_busy : OUT std_logic;
79 dd_ready : OUT std_logic;
80 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
81 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
82 dd_block_ready_ftu : IN std_logic;
83 dd_block_start_ack_ftu : OUT std_logic := '0';
84 dd_block_start_ftu : IN std_logic;
85 dd_send : IN std_logic;
86 dd_send_ack : OUT std_logic := '1';
87 dd_send_ready : OUT std_logic := '1';
88 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
89 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
90 --
91 ftu_error_send : IN std_logic;
92 ftu_error_send_ack : OUT std_logic := '1';
93 ftu_error_send_ready : OUT std_logic := '1';
94 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
95 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
96 trigger_counter_read : OUT std_logic := '0';
97 trigger_counter_valid : IN std_logic;
98 board_id : IN std_logic_vector (63 DOWNTO 0);
99 get_ts_counter : OUT std_logic := '0';
100 get_ts_counter_ready : IN std_logic;
101 get_ts_counter_started : IN std_logic;
102 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
103 get_ot_counter : OUT std_logic := '0';
104 get_ot_counter_ready : IN std_logic;
105 get_ot_counter_started : IN std_logic;
106 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
107 temp_sensor_array : IN sensor_array_type;
108 temp_sensor_ready : IN std_logic;
109 crate_reset : OUT std_logic := '0';
110 crate_reset_ack : IN std_logic;
111 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
112 --
113 start_run : OUT std_logic := '0';
114 start_run_ack : IN std_logic;
115 stop_run : OUT std_logic := '0';
116 stop_run_ack : IN std_logic;
117 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
118 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
119 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
120 new_config_ftu : OUT std_logic := '0';
121 new_config_ftu_ack : IN std_logic;
122 new_config_ftu_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
123 );
124
125END ethernet_modul ;
126
127ARCHITECTURE beha OF ethernet_modul IS
128
129 -- Architecture declarations
130
131 -- Internal signal declarations
132 SIGNAL busy : std_logic := '1';
133 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);
134 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);
135 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";
136 SIGNAL sd_write : std_logic := '0';
137 SIGNAL sd_read : std_logic;
138 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
139 SIGNAL sd_started : std_logic;
140 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);
141 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);
142 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);
143 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');
144 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);
145 SIGNAL config_ready_cc : std_logic := '0';
146 SIGNAL config_started_cc : std_logic := '0';
147 SIGNAL config_start_cc : std_logic;
148 SIGNAL fl_started : std_logic;
149 SIGNAL fl_read : std_logic := '0';
150 --
151 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0);
152 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0);
153 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0);
154 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0);
155 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0";
156 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0);
157 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0);
158 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0);
159 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0);
160 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0";
161 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0);
162 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0);
163 SIGNAL dd_read : std_logic;
164 SIGNAL dd_started : std_logic := '0';
165 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0');
166 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0);
167 SIGNAL dd_block_ready : std_logic := '0';
168 --
169 SIGNAL dd_block_start : std_logic := '0';
170 SIGNAL dd_block_start_ack : std_logic;
171 SIGNAL dd_write_general : std_logic := '0';
172 SIGNAL dd_write_general_ready : std_logic;
173 SIGNAL dd_write_general_started : std_logic;
174 SIGNAL dd_write : std_logic := '0';
175 SIGNAL dd_started_general : std_logic := '0';
176 SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0');
177 SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0');
178 SIGNAL get_header : std_logic;
179 SIGNAL get_header_started : std_logic := '0';
180 SIGNAL get_header_ready : std_logic := '0';
181 SIGNAL led2 : std_logic_vector(7 DOWNTO 0);
182 SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0);
183 SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0);
184 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0);
185 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0);
186 SIGNAL header_current_state : std_logic_vector(15 DOWNTO 0) := (others => '0');
187
188 -- Implicit buffer signal declarations
189 SIGNAL dd_busy_internal : std_logic;
190 SIGNAL dd_ready_internal : std_logic;
191 SIGNAL fl_busy_internal : std_logic;
192 SIGNAL fl_ready_internal : std_logic;
193 SIGNAL sd_busy_internal : std_logic;
194 SIGNAL sd_ready_internal : std_logic;
195
196
197 -- Component Declarations
198 COMPONENT CRAM_4096_16b
199 PORT (
200 clka : IN std_logic ;
201 dina : IN std_logic_VECTOR (15 DOWNTO 0);
202 addra : IN std_logic_VECTOR (11 DOWNTO 0);
203 wea : IN std_logic_VECTOR (0 DOWNTO 0);
204 clkb : IN std_logic ;
205 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
206 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
207 );
208 END COMPONENT;
209 COMPONENT DRAM_4096_16b
210 PORT (
211 clka : IN std_logic ;
212 dina : IN std_logic_VECTOR (15 DOWNTO 0);
213 addra : IN std_logic_VECTOR (11 DOWNTO 0);
214 wea : IN std_logic_VECTOR (0 DOWNTO 0);
215 clkb : IN std_logic ;
216 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
217 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
218 );
219 END COMPONENT;
220 COMPONENT FRAM_4096_16b
221 PORT (
222 clka : IN std_logic ;
223 dina : IN std_logic_VECTOR (15 DOWNTO 0);
224 addra : IN std_logic_VECTOR (11 DOWNTO 0);
225 wea : IN std_logic_VECTOR (0 DOWNTO 0);
226 clkb : IN std_logic ;
227 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
228 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
229 );
230 END COMPONENT;
231 COMPONENT cram_control
232 PORT (
233 clk : IN std_logic ;
234 led : OUT std_logic_vector (7 DOWNTO 0) := X"00";
235 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
236 cram_data_out : IN std_logic_vector (15 DOWNTO 0);
237 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
238 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
239 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
240 sd_write : IN std_logic ;
241 sd_read : IN std_logic ;
242 sd_read_ftu : IN std_logic ;
243 sd_busy : OUT std_logic := '1';
244 sd_started : OUT std_logic := '0';
245 sd_started_ftu : OUT std_logic := '0';
246 sd_ready : OUT std_logic := '0';
247 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
248 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
249 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
250 sd_addr : IN std_logic_vector (11 DOWNTO 0);
251 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
252 config_start_cc : IN std_logic ;
253 config_started_cc : OUT std_logic := '0';
254 config_ready_cc : OUT std_logic := '0';
255 -- data from config ram
256 general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
257 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
258 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
259 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
260 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
261 lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
262 lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
263 coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
264 coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
265 trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
266 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
267 dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
268 cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
269 cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
270 cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
271 cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
272 cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
273 cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
274 cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
275 cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
276 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
277 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
278 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
279 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
280 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
281 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
282 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
283 );
284 END COMPONENT;
285 COMPONENT dd_write_general_modul
286 PORT (
287 clk : IN std_logic ;
288 dd_write_general : IN std_logic ;
289 dd_write_general_started : OUT std_logic := '0';
290 dd_write_general_ready : OUT std_logic := '0';
291 dd_busy : IN std_logic ;
292 dd_write : OUT std_logic := '0';
293 dd_started : IN std_logic ;
294 dd_ready : IN std_logic ;
295 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
296 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
297 get_ot_counter : OUT std_logic := '0';
298 get_ot_counter_started : IN std_logic ;
299 get_ot_counter_ready : IN std_logic ;
300 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
301 temp_sensor_ready : IN std_logic ;
302 temp_sensor_array : IN sensor_array_type
303 );
304 END COMPONENT;
305 COMPONENT dram_control
306 PORT (
307 clk : IN std_logic ;
308 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
309 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
310 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
311 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
312 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
313 dd_block_start : IN std_logic ;
314 dd_block_start_ftu : IN std_logic ;
315 dd_block_start_ack : OUT std_logic := '0';
316 dd_block_start_ack_ftu : OUT std_logic := '0';
317 dd_block_ready : IN std_logic ;
318 dd_block_ready_ftu : IN std_logic ;
319 dd_read : IN std_logic ;
320 dd_write_ftu : IN std_logic ;
321 dd_write_general : IN std_logic ;
322 dd_busy : OUT std_logic := '1';
323 dd_started : OUT std_logic := '0';
324 dd_started_ftu : OUT std_logic := '0';
325 dd_started_general : OUT std_logic := '0';
326 dd_ready : OUT std_logic := '0';
327 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
328 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
329 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0);
330 dd_addr : IN std_logic_vector (11 DOWNTO 0);
331 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
332 dd_addr_general : IN std_logic_vector (11 DOWNTO 0)
333 );
334 END COMPONENT;
335 COMPONENT eth_config_modul
336 PORT (
337 clk : IN std_logic ;
338 config_start_eth : IN std_logic ;
339 config_started_eth : OUT std_logic := '0';
340 config_ready_eth : OUT std_logic := '0';
341 config_start_cc : OUT std_logic := '0';
342 config_started_cc : IN std_logic ;
343 config_ready_cc : IN std_logic
344 );
345 END COMPONENT;
346 COMPONENT fram_control
347 PORT (
348 clk : IN std_logic ;
349 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
350 fram_data_out : IN std_logic_vector (15 DOWNTO 0);
351 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
352 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
353 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
354 fl_read : IN std_logic ;
355 fl_write_ftu : IN std_logic ;
356 fl_busy : OUT std_logic := '1';
357 fl_started : OUT std_logic := '0';
358 fl_started_ftu : OUT std_logic := '0';
359 fl_ready : OUT std_logic := '0';
360 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
361 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
362 fl_addr : IN std_logic_vector (11 DOWNTO 0);
363 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
364 );
365 END COMPONENT;
366 COMPONENT header_modul
367 PORT (
368 clk : IN std_logic ;
369 get_header : IN std_logic ;
370 get_header_started : OUT std_logic := '0';
371 get_header_ready : OUT std_logic := '0';
372 board_id : IN std_logic_vector (63 DOWNTO 0);
373 trigger_counter_read : OUT std_logic := '0';
374 trigger_counter_valid : IN std_logic ;
375 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
376 get_ts_counter : OUT std_logic := '0';
377 get_ts_counter_started : IN std_logic ;
378 get_ts_counter_ready : IN std_logic ;
379 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
380 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0');
381 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
382 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
383 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0');
384 header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
385 current_cc_state : IN std_logic_vector (15 DOWNTO 0)
386 );
387 END COMPONENT;
388 COMPONENT w5300_modul
389 PORT (
390 clk : IN std_logic ;
391 wiz_reset : OUT std_logic := '1';
392 addr : OUT std_logic_vector (9 DOWNTO 0);
393 data : INOUT std_logic_vector (15 DOWNTO 0);
394 cs : OUT std_logic := '1';
395 wr : OUT std_logic := '1';
396 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
397 rd : OUT std_logic := '1';
398 int : IN std_logic ;
399 busy : OUT std_logic := '1';
400 new_config : OUT std_logic := '0';
401 config_started : IN std_logic ;
402 config_started_ack : OUT std_logic := '0';
403 --
404 ping_ftu_start : OUT std_logic := '0';
405 ping_ftu_started : IN std_logic ;
406 ping_ftu_ready : IN std_logic ;
407 --
408 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
409 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
410 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
411 sd_write : OUT std_logic := '0';
412 sd_read : OUT std_logic := '0';
413 sd_started : IN std_logic ;
414 sd_ready : IN std_logic ;
415 sd_busy : IN std_logic ;
416 --
417 dd_block_start : OUT std_logic := '0';
418 dd_block_start_ack : IN std_logic ;
419 dd_block_ready : OUT std_logic := '1';
420 dd_send : IN std_logic ;
421 dd_send_ack : OUT std_logic := '1';
422 dd_send_ready : OUT std_logic := '1';
423 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
424 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
425 dd_read : OUT std_logic := '0';
426 dd_started : IN std_logic ;
427 dd_ready : IN std_logic ;
428 dd_busy : IN std_logic ;
429 dd_write_general : OUT std_logic := '0';
430 dd_write_general_started : IN std_logic ;
431 dd_write_general_ready : IN std_logic ;
432 --
433 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
434 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
435 fl_read : OUT std_logic := '0';
436 fl_started : IN std_logic ;
437 fl_ready : IN std_logic ;
438 fl_busy : IN std_logic ;
439 --
440 ftu_error_send : IN std_logic ;
441 ftu_error_send_ack : OUT std_logic := '1';
442 ftu_error_send_ready : OUT std_logic := '1';
443 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
444 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
445 --
446 get_header : OUT std_logic := '0';
447 get_header_started : IN std_logic ;
448 get_header_ready : IN std_logic ;
449 header_board_id : IN std_logic_vector (63 DOWNTO 0);
450 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
451 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
452 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
453 header_current_state : IN std_logic_vector (15 DOWNTO 0);
454 --
455 start_run : OUT std_logic := '0';
456 start_run_ack : IN std_logic ;
457 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
458 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
459 stop_run : OUT std_logic := '0';
460 stop_run_ack : IN std_logic ;
461 crate_reset : OUT std_logic := '0';
462 crate_reset_ack : IN std_logic ;
463 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
464 new_config_ftu : OUT std_logic := '0';
465 new_config_ftu_ack : IN std_logic ;
466 new_config_ftu_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
467 );
468 END COMPONENT;
469
470BEGIN
471
472 -- ModuleWare code(v1.9) for instance 'U_3' of 'or'
473 led <= led1 OR led2;
474
475 -- Instance port mappings.
476 U_1 : CRAM_4096_16b
477 PORT MAP (
478 clka => clk,
479 dina => cram_data_in,
480 addra => cram_addr_in,
481 wea => cram_we,
482 clkb => clk,
483 addrb => cram_addr_out,
484 doutb => cram_data_out
485 );
486 U_7 : DRAM_4096_16b
487 PORT MAP (
488 clka => clk,
489 dina => dram_data_in,
490 addra => dram_addr_in,
491 wea => dram_we,
492 clkb => clk,
493 addrb => dram_addr_out,
494 doutb => doutb1
495 );
496 U_5 : FRAM_4096_16b
497 PORT MAP (
498 clka => clk,
499 dina => fram_data_in,
500 addra => fram_addr_in,
501 wea => fram_we,
502 clkb => clk,
503 addrb => fram_addr_out,
504 doutb => doutb
505 );
506 U_2 : cram_control
507 PORT MAP (
508 clk => clk,
509 led => led2,
510 cram_data_in => cram_data_in,
511 cram_data_out => cram_data_out,
512 cram_addr_in => cram_addr_in,
513 cram_addr_out => cram_addr_out,
514 cram_we => cram_we,
515 sd_write => sd_write,
516 sd_read => sd_read,
517 sd_read_ftu => sd_read_ftu,
518 sd_busy => sd_busy_internal,
519 sd_started => sd_started,
520 sd_started_ftu => sd_started_ftu,
521 sd_ready => sd_ready_internal,
522 sd_data_in => sd_data_in,
523 sd_data_out => sd_data_out,
524 sd_data_out_ftu => sd_data_out_ftu,
525 sd_addr => sd_addr,
526 sd_addr_ftu => sd_addr_ftu,
527 config_start_cc => config_start_cc,
528 config_started_cc => config_started_cc,
529 config_ready_cc => config_ready_cc,
530 general_settings => general_settings,
531 lp_pt_freq => lp_pt_freq,
532 lp_pt_ratio => lp_pt_ratio,
533 lp1_amplitude => lp1_amplitude,
534 lp2_amplitude => lp2_amplitude,
535 lp1_delay => lp1_delay,
536 lp2_delay => lp2_delay,
537 coin_n_p => coin_n_p,
538 coin_n_c => coin_n_c,
539 trigger_delay => trigger_delay,
540 timemarker_delay => timemarker_delay,
541 dead_time => dead_time,
542 cc_R0 => cc_R0,
543 cc_R1 => cc_R1,
544 cc_R8 => cc_R8,
545 cc_R9 => cc_R9,
546 cc_R11 => cc_R11,
547 cc_R13 => cc_R13,
548 cc_R14 => cc_R14,
549 cc_R15 => cc_R15,
550 coin_win_p => coin_win_p,
551 coin_win_c => coin_win_c,
552 prescaling_FTU01 => prescaling_FTU01,
553 ftu_active_cr0 => ftu_active_cr0,
554 ftu_active_cr1 => ftu_active_cr1,
555 ftu_active_cr2 => ftu_active_cr2,
556 ftu_active_cr3 => ftu_active_cr3
557 );
558 U_9 : dd_write_general_modul
559 PORT MAP (
560 clk => clk,
561 dd_write_general => dd_write_general,
562 dd_write_general_started => dd_write_general_started,
563 dd_write_general_ready => dd_write_general_ready,
564 dd_busy => dd_busy_internal,
565 dd_write => dd_write,
566 dd_started => dd_started_general,
567 dd_ready => dd_ready_internal,
568 dd_addr => dd_addr1,
569 dd_data => dd_data,
570 get_ot_counter => get_ot_counter,
571 get_ot_counter_started => get_ot_counter_started,
572 get_ot_counter_ready => get_ot_counter_ready,
573 on_time_counter => on_time_counter,
574 temp_sensor_ready => temp_sensor_ready,
575 temp_sensor_array => temp_sensor_array
576 );
577 U_8 : dram_control
578 PORT MAP (
579 clk => clk,
580 dram_data_in => dram_data_in,
581 dram_data_out => doutb1,
582 dram_addr_in => dram_addr_in,
583 dram_addr_out => dram_addr_out,
584 dram_we => dram_we,
585 dd_block_start => dd_block_start,
586 dd_block_start_ftu => dd_block_start_ftu,
587 dd_block_start_ack => dd_block_start_ack,
588 dd_block_start_ack_ftu => dd_block_start_ack_ftu,
589 dd_block_ready => dd_block_ready,
590 dd_block_ready_ftu => dd_block_ready_ftu,
591 dd_read => dd_read,
592 dd_write_ftu => dd_write_ftu,
593 dd_write_general => dd_write,
594 dd_busy => dd_busy_internal,
595 dd_started => dd_started,
596 dd_started_ftu => dd_started_ftu,
597 dd_started_general => dd_started_general,
598 dd_ready => dd_ready_internal,
599 dd_data_out => dd_data_out,
600 dd_data_in_ftu => dd_data_in_ftu,
601 dd_data_in_general => dd_data,
602 dd_addr => dd_addr,
603 dd_addr_ftu => dd_addr_ftu,
604 dd_addr_general => dd_addr1
605 );
606 U_4 : eth_config_modul
607 PORT MAP (
608 clk => clk,
609 config_start_eth => config_start_eth,
610 config_started_eth => config_started_eth,
611 config_ready_eth => config_ready_eth,
612 config_start_cc => config_start_cc,
613 config_started_cc => config_started_cc,
614 config_ready_cc => config_ready_cc
615 );
616 U_6 : fram_control
617 PORT MAP (
618 clk => clk,
619 fram_data_in => fram_data_in,
620 fram_data_out => doutb,
621 fram_addr_in => fram_addr_in,
622 fram_addr_out => fram_addr_out,
623 fram_we => fram_we,
624 fl_read => fl_read,
625 fl_write_ftu => fl_write_ftu,
626 fl_busy => fl_busy_internal,
627 fl_started => fl_started,
628 fl_started_ftu => fl_started_ftu,
629 fl_ready => fl_ready_internal,
630 fl_data_out => fl_data_out,
631 fl_data_in_ftu => fl_data_in_ftu,
632 fl_addr => fl_addr,
633 fl_addr_ftu => fl_addr_ftu
634 );
635 U_10 : header_modul
636 PORT MAP (
637 clk => clk,
638 get_header => get_header,
639 get_header_started => get_header_started,
640 get_header_ready => get_header_ready,
641 board_id => board_id,
642 trigger_counter_read => trigger_counter_read,
643 trigger_counter_valid => trigger_counter_valid,
644 trigger_counter => trigger_counter,
645 get_ts_counter => get_ts_counter,
646 get_ts_counter_started => get_ts_counter_started,
647 get_ts_counter_ready => get_ts_counter_ready,
648 timestamp_counter => timestamp_counter,
649 header_board_id => header_board_id,
650 header_firmware_id => header_firmware_id,
651 header_trigger_counter => header_trigger_counter,
652 header_timestamp_counter => header_timestamp_counter,
653 header_current_state => header_current_state,
654 current_cc_state => current_cc_state
655 );
656 U_0 : w5300_modul
657 PORT MAP (
658 clk => clk,
659 wiz_reset => wiz_reset,
660 addr => wiz_addr,
661 data => wiz_data,
662 cs => wiz_cs,
663 wr => wiz_wr,
664 led => led1,
665 rd => wiz_rd,
666 int => wiz_int,
667 busy => busy,
668 new_config => new_config,
669 config_started => config_started,
670 config_started_ack => config_started_ack,
671 ping_ftu_start => ping_ftu_start,
672 ping_ftu_started => ping_ftu_started,
673 ping_ftu_ready => ping_ftu_ready,
674 sd_addr => sd_addr,
675 sd_data_out => sd_data_in,
676 sd_data_in => sd_data_out,
677 sd_write => sd_write,
678 sd_read => sd_read,
679 sd_started => sd_started,
680 sd_ready => sd_ready_internal,
681 sd_busy => sd_busy_internal,
682 dd_block_start => dd_block_start,
683 dd_block_start_ack => dd_block_start_ack,
684 dd_block_ready => dd_block_ready,
685 dd_send => dd_send,
686 dd_send_ack => dd_send_ack,
687 dd_send_ready => dd_send_ready,
688 dd_addr => dd_addr,
689 dd_data_in => dd_data_out,
690 dd_read => dd_read,
691 dd_started => dd_started,
692 dd_ready => dd_ready_internal,
693 dd_busy => dd_busy_internal,
694 dd_write_general => dd_write_general,
695 dd_write_general_started => dd_write_general_started,
696 dd_write_general_ready => dd_write_general_ready,
697 fl_addr => fl_addr,
698 fl_data_in => fl_data_out,
699 fl_read => fl_read,
700 fl_started => fl_started,
701 fl_ready => fl_ready_internal,
702 fl_busy => fl_busy_internal,
703 ftu_error_send => ftu_error_send,
704 ftu_error_send_ack => ftu_error_send_ack,
705 ftu_error_send_ready => ftu_error_send_ready,
706 ftu_error_calls => ftu_error_calls,
707 ftu_error_data => ftu_error_data,
708 get_header => get_header,
709 get_header_started => get_header_started,
710 get_header_ready => get_header_ready,
711 header_board_id => header_board_id,
712 header_firmware_id => header_firmware_id,
713 header_trigger_counter => header_trigger_counter,
714 header_timestamp_counter => header_timestamp_counter,
715 header_current_state => header_current_state,
716 start_run => start_run,
717 start_run_ack => start_run_ack,
718 start_run_param => start_run_param,
719 start_run_num_events => start_run_num_events,
720 stop_run => stop_run,
721 stop_run_ack => stop_run_ack,
722 crate_reset => crate_reset,
723 crate_reset_ack => crate_reset_ack,
724 crate_reset_param => crate_reset_param,
725 new_config_ftu => new_config_ftu,
726 new_config_ftu_ack => new_config_ftu_ack,
727 new_config_ftu_param => new_config_ftu_param
728 );
729
730 -- Implicit buffered output assignments
731 dd_busy <= dd_busy_internal;
732 dd_ready <= dd_ready_internal;
733 fl_busy <= fl_busy_internal;
734 fl_ready <= fl_ready_internal;
735 sd_busy <= sd_busy_internal;
736 sd_ready <= sd_ready_internal;
737
738END beha;
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