source: firmware/FTM/ethernet/ethernet_modul_beha.vhd@ 10247

Last change on this file since 10247 was 10227, checked in by weitzel, 14 years ago
first version of FTM firmware including ethernet and FTU interface; still some debugging needed
File size: 25.6 KB
Line 
1-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 11:17:45 25.02.2011
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12--LIBRARY FACT_FTM_lib;
13library ftm_definitions;
14USE ftm_definitions.ftm_array_types.all;
15USE ftm_definitions.ftm_constants.all;
16
17ENTITY ethernet_modul IS
18 PORT(
19 wiz_reset : OUT std_logic := '1';
20 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
21 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
22 wiz_cs : OUT std_logic := '1';
23 wiz_wr : OUT std_logic := '1';
24 wiz_rd : OUT std_logic := '1';
25 wiz_int : IN std_logic;
26 clk : IN std_logic;
27 sd_ready : OUT std_logic;
28 sd_busy : OUT std_logic;
29 led : OUT std_logic_vector (7 DOWNTO 0);
30 sd_read_ftu : IN std_logic;
31 sd_started_ftu : OUT std_logic := '0';
32 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
33 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
34 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
35 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
36 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
37 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
38 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
39 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
40 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
41 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
42 dead_time : OUT std_logic_vector (15 DOWNTO 0);
43 -- data from config ram
44 general_settings : OUT std_logic_vector (15 DOWNTO 0);
45 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
46 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
47 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
48 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
49 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
50 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
51 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
52 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
53 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
54 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
55 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
56 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
57 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
58 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
59 new_config : OUT std_logic := '0';
60 config_started : IN std_logic;
61 config_start_eth : IN std_logic;
62 config_started_eth : OUT std_logic := '0';
63 config_ready_eth : OUT std_logic := '0';
64 config_started_ack : OUT std_logic := '0';
65 fl_busy : OUT std_logic;
66 fl_ready : OUT std_logic;
67 fl_write_ftu : IN std_logic;
68 fl_started_ftu : OUT std_logic := '0';
69 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
70 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
71 --
72 ping_ftu_start : OUT std_logic := '0';
73 ping_ftu_started : IN std_logic;
74 ping_ftu_ready : IN std_logic;
75 dd_write_ftu : IN std_logic;
76 dd_started_ftu : OUT std_logic := '0';
77 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
78 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
79 dd_busy : OUT std_logic;
80 dd_ready : OUT std_logic;
81 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
82 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
83 );
84
85-- Declarations
86
87END ethernet_modul ;
88
89--
90-- VHDL Architecture FACT_FTM_lib.ethernet_modul.beha
91--
92-- Created:
93-- by - kai.UNKNOWN (E5PCXX)
94-- at - 11:17:46 25.02.2011
95--
96-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
97--
98--
99--
100--LIBRARY IEEE;
101--USE IEEE.STD_LOGIC_1164.all;
102--USE IEEE.STD_LOGIC_ARITH.all;
103--USE IEEE.STD_LOGIC_UNSIGNED.all;
104--LIBRARY FACT_FTM_lib;
105--USE FACT_FTM_lib.ftm_array_types.all;
106--USE FACT_FTM_lib.ftm_constants.all;
107
108--LIBRARY FACT_FTM_lib;
109
110ARCHITECTURE beha OF ethernet_modul IS
111
112 -- Architecture declarations
113
114 -- Internal signal declarations
115 SIGNAL busy : std_logic := '1';
116 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);
117 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);
118 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";
119 SIGNAL sd_write : std_logic := '0';
120 SIGNAL sd_read : std_logic;
121 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
122 SIGNAL sd_started : std_logic;
123 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);
124 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);
125 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);
126 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');
127 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);
128 SIGNAL config_ready_cc : std_logic := '0';
129 SIGNAL config_started_cc : std_logic := '0';
130 SIGNAL config_start_cc : std_logic;
131 SIGNAL fl_started : std_logic;
132 SIGNAL fl_read : std_logic := '0';
133 --
134 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0);
135 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0);
136 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0);
137 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0);
138 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0";
139 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0);
140 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0);
141 SIGNAL led2 : std_logic_vector(7 DOWNTO 0) := X"00";
142 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0);
143 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0);
144 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0";
145 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0);
146 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0);
147 SIGNAL dd_read : std_logic;
148 SIGNAL dd_started : std_logic := '0';
149 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0');
150 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0);
151 SIGNAL dd_block_ready : std_logic := '0';
152 --
153 SIGNAL dd_block_start : std_logic := '0';
154 SIGNAL dd_block_start_ack : std_logic;
155 SIGNAL dd_block_ready_ftu : std_logic;
156 SIGNAL dd_block_start_ack_ftu : std_logic := '0';
157 SIGNAL dd_block_start_ftu : std_logic;
158
159 -- Implicit buffer signal declarations
160 SIGNAL dd_busy_internal : std_logic;
161 SIGNAL dd_ready_internal : std_logic;
162 SIGNAL fl_busy_internal : std_logic;
163 SIGNAL fl_ready_internal : std_logic;
164 SIGNAL sd_busy_internal : std_logic;
165 SIGNAL sd_ready_internal : std_logic;
166
167
168 -- Component Declarations
169 COMPONENT CRAM_4096_16b
170 PORT (
171 clka : IN std_logic ;
172 dina : IN std_logic_VECTOR (15 DOWNTO 0);
173 addra : IN std_logic_VECTOR (11 DOWNTO 0);
174 wea : IN std_logic_VECTOR (0 DOWNTO 0);
175 clkb : IN std_logic ;
176 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
177 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
178 );
179 END COMPONENT;
180 COMPONENT DRAM_4096_16b
181 PORT (
182 clka : IN std_logic ;
183 dina : IN std_logic_VECTOR (15 DOWNTO 0);
184 addra : IN std_logic_VECTOR (11 DOWNTO 0);
185 wea : IN std_logic_VECTOR (0 DOWNTO 0);
186 clkb : IN std_logic ;
187 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
188 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
189 );
190 END COMPONENT;
191 COMPONENT FRAM_4096_16b
192 PORT (
193 clka : IN std_logic ;
194 dina : IN std_logic_VECTOR (15 DOWNTO 0);
195 addra : IN std_logic_VECTOR (11 DOWNTO 0);
196 wea : IN std_logic_VECTOR (0 DOWNTO 0);
197 clkb : IN std_logic ;
198 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
199 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
200 );
201 END COMPONENT;
202 COMPONENT cram_control
203 PORT (
204 clk : IN std_logic ;
205 led : OUT std_logic_vector (7 DOWNTO 0) := X"00";
206 cram_data_in : OUT std_logic_vector (15 DOWNTO 0);
207 cram_data_out : IN std_logic_vector (15 DOWNTO 0);
208 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0);
209 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0);
210 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
211 sd_write : IN std_logic ;
212 sd_read : IN std_logic ;
213 sd_read_ftu : IN std_logic ;
214 sd_busy : OUT std_logic := '1';
215 sd_started : OUT std_logic := '0';
216 sd_started_ftu : OUT std_logic := '0';
217 sd_ready : OUT std_logic := '0';
218 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
219 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
220 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
221 sd_addr : IN std_logic_vector (11 DOWNTO 0);
222 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
223 config_start_cc : IN std_logic ;
224 config_started_cc : OUT std_logic := '0';
225 config_ready_cc : OUT std_logic := '0';
226 -- data from config ram
227 general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
228 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
229 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
230 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
231 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
232 lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
233 lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
234 coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
235 coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
236 trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
237 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
238 dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
239 cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
240 cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
241 cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
242 cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
243 cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
244 cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
245 cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
246 cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
247 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
248 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
249 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
250 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
251 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
252 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
253 );
254 END COMPONENT;
255 COMPONENT dram_control
256 PORT (
257 clk : IN std_logic ;
258 dram_data_in : OUT std_logic_vector (15 DOWNTO 0);
259 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
260 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0);
261 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0);
262 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
263 dd_block_start : IN std_logic ;
264 dd_block_start_ftu : IN std_logic ;
265 dd_block_start_ack : OUT std_logic := '0';
266 dd_block_start_ack_ftu : OUT std_logic := '0';
267 dd_block_ready : IN std_logic ;
268 dd_block_ready_ftu : IN std_logic ;
269 dd_read : IN std_logic ;
270 dd_write_ftu : IN std_logic ;
271 dd_busy : OUT std_logic := '1';
272 dd_started : OUT std_logic := '0';
273 dd_started_ftu : OUT std_logic := '0';
274 dd_ready : OUT std_logic := '0';
275 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
276 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
277 dd_addr : IN std_logic_vector (11 DOWNTO 0);
278 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
279 );
280 END COMPONENT;
281 COMPONENT eth_config_modul
282 PORT (
283 clk : IN std_logic ;
284 config_start_eth : IN std_logic ;
285 config_started_eth : OUT std_logic := '0';
286 config_ready_eth : OUT std_logic := '0';
287 config_start_cc : OUT std_logic := '0';
288 config_started_cc : IN std_logic ;
289 config_ready_cc : IN std_logic
290 );
291 END COMPONENT;
292 COMPONENT fram_control
293 PORT (
294 clk : IN std_logic ;
295 fram_data_in : OUT std_logic_vector (15 DOWNTO 0);
296 fram_data_out : IN std_logic_vector (15 DOWNTO 0);
297 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0);
298 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0);
299 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
300 fl_read : IN std_logic ;
301 fl_write_ftu : IN std_logic ;
302 fl_busy : OUT std_logic := '1';
303 fl_started : OUT std_logic := '0';
304 fl_started_ftu : OUT std_logic := '0';
305 fl_ready : OUT std_logic := '0';
306 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
307 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
308 fl_addr : IN std_logic_vector (11 DOWNTO 0);
309 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
310 );
311 END COMPONENT;
312 COMPONENT w5300_modul
313 PORT (
314 clk : IN std_logic ;
315 wiz_reset : OUT std_logic := '1';
316 addr : OUT std_logic_vector (9 DOWNTO 0);
317 data : INOUT std_logic_vector (15 DOWNTO 0);
318 cs : OUT std_logic := '1';
319 wr : OUT std_logic := '1';
320 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
321 rd : OUT std_logic := '1';
322 int : IN std_logic ;
323 busy : OUT std_logic := '1';
324 new_config : OUT std_logic := '0';
325 config_started : IN std_logic ;
326 config_started_ack : OUT std_logic := '0';
327 --
328 ping_ftu_start : OUT std_logic := '0';
329 ping_ftu_started : IN std_logic ;
330 ping_ftu_ready : IN std_logic ;
331 --
332 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
333 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
334 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
335 sd_write : OUT std_logic := '0';
336 sd_read : OUT std_logic := '0';
337 sd_started : IN std_logic ;
338 sd_ready : IN std_logic ;
339 sd_busy : IN std_logic ;
340 --
341 dd_block_start : OUT std_logic := '0';
342 dd_block_start_ack : IN std_logic ;
343 dd_block_ready : OUT std_logic := '0';
344 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
345 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
346 dd_read : OUT std_logic := '0';
347 dd_started : IN std_logic ;
348 dd_ready : IN std_logic ;
349 dd_busy : IN std_logic ;
350 --
351 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
352 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
353 fl_read : OUT std_logic := '0';
354 fl_started : IN std_logic ;
355 fl_ready : IN std_logic ;
356 fl_busy : IN std_logic
357 );
358 END COMPONENT;
359
360 -- Optional embedded configurations
361 -- pragma synthesis_off
362 -- FOR ALL : CRAM_4096_16b USE ENTITY FACT_FTM_lib.CRAM_4096_16b;
363 -- FOR ALL : DRAM_4096_16b USE ENTITY FACT_FTM_lib.DRAM_4096_16b;
364 -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b;
365 -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control;
366 -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control;
367 -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul;
368 -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control;
369 -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul;
370 -- pragma synthesis_on
371
372
373BEGIN
374
375 -- ModuleWare code(v1.9) for instance 'U_3' of 'or'
376 led <= led1 OR led2;
377
378 -- Instance port mappings.
379 U_1 : CRAM_4096_16b
380 PORT MAP (
381 clka => clk,
382 dina => cram_data_in,
383 addra => cram_addr_in,
384 wea => cram_we,
385 clkb => clk,
386 addrb => cram_addr_out,
387 doutb => cram_data_out
388 );
389 U_7 : DRAM_4096_16b
390 PORT MAP (
391 clka => clk,
392 dina => dram_data_in,
393 addra => dram_addr_in,
394 wea => dram_we,
395 clkb => clk,
396 addrb => dram_addr_out,
397 doutb => doutb1
398 );
399 U_5 : FRAM_4096_16b
400 PORT MAP (
401 clka => clk,
402 dina => fram_data_in,
403 addra => fram_addr_in,
404 wea => fram_we,
405 clkb => clk,
406 addrb => fram_addr_out,
407 doutb => doutb
408 );
409 U_2 : cram_control
410 PORT MAP (
411 clk => clk,
412 led => led2,
413 cram_data_in => cram_data_in,
414 cram_data_out => cram_data_out,
415 cram_addr_in => cram_addr_in,
416 cram_addr_out => cram_addr_out,
417 cram_we => cram_we,
418 sd_write => sd_write,
419 sd_read => sd_read,
420 sd_read_ftu => sd_read_ftu,
421 sd_busy => sd_busy_internal,
422 sd_started => sd_started,
423 sd_started_ftu => sd_started_ftu,
424 sd_ready => sd_ready_internal,
425 sd_data_in => sd_data_in,
426 sd_data_out => sd_data_out,
427 sd_data_out_ftu => sd_data_out_ftu,
428 sd_addr => sd_addr,
429 sd_addr_ftu => sd_addr_ftu,
430 config_start_cc => config_start_cc,
431 config_started_cc => config_started_cc,
432 config_ready_cc => config_ready_cc,
433 general_settings => general_settings,
434 lp_pt_freq => lp_pt_freq,
435 lp_pt_ratio => lp_pt_ratio,
436 lp1_amplitude => lp1_amplitude,
437 lp2_amplitude => lp2_amplitude,
438 lp1_delay => lp1_delay,
439 lp2_delay => lp2_delay,
440 coin_n_p => coin_n_p,
441 coin_n_c => coin_n_c,
442 trigger_delay => trigger_delay,
443 timemarker_delay => timemarker_delay,
444 dead_time => dead_time,
445 cc_R0 => cc_R0,
446 cc_R1 => cc_R1,
447 cc_R8 => cc_R8,
448 cc_R9 => cc_R9,
449 cc_R11 => cc_R11,
450 cc_R13 => cc_R13,
451 cc_R14 => cc_R14,
452 cc_R15 => cc_R15,
453 coin_win_p => coin_win_p,
454 coin_win_c => coin_win_c,
455 ftu_active_cr0 => ftu_active_cr0,
456 ftu_active_cr1 => ftu_active_cr1,
457 ftu_active_cr2 => ftu_active_cr2,
458 ftu_active_cr3 => ftu_active_cr3
459 );
460 U_8 : dram_control
461 PORT MAP (
462 clk => clk,
463 dram_data_in => dram_data_in,
464 dram_data_out => doutb1,
465 dram_addr_in => dram_addr_in,
466 dram_addr_out => dram_addr_out,
467 dram_we => dram_we,
468 dd_block_start => dd_block_start,
469 dd_block_start_ftu => dd_block_start_ftu,
470 dd_block_start_ack => dd_block_start_ack,
471 dd_block_start_ack_ftu => dd_block_start_ack_ftu,
472 dd_block_ready => dd_block_ready,
473 dd_block_ready_ftu => dd_block_ready_ftu,
474 dd_read => dd_read,
475 dd_write_ftu => dd_write_ftu,
476 dd_busy => dd_busy_internal,
477 dd_started => dd_started,
478 dd_started_ftu => dd_started_ftu,
479 dd_ready => dd_ready_internal,
480 dd_data_out => dd_data_out,
481 dd_data_in_ftu => dd_data_in_ftu,
482 dd_addr => dd_addr,
483 dd_addr_ftu => dd_addr_ftu
484 );
485 U_4 : eth_config_modul
486 PORT MAP (
487 clk => clk,
488 config_start_eth => config_start_eth,
489 config_started_eth => config_started_eth,
490 config_ready_eth => config_ready_eth,
491 config_start_cc => config_start_cc,
492 config_started_cc => config_started_cc,
493 config_ready_cc => config_ready_cc
494 );
495 U_6 : fram_control
496 PORT MAP (
497 clk => clk,
498 fram_data_in => fram_data_in,
499 fram_data_out => doutb,
500 fram_addr_in => fram_addr_in,
501 fram_addr_out => fram_addr_out,
502 fram_we => fram_we,
503 fl_read => fl_read,
504 fl_write_ftu => fl_write_ftu,
505 fl_busy => fl_busy_internal,
506 fl_started => fl_started,
507 fl_started_ftu => fl_started_ftu,
508 fl_ready => fl_ready_internal,
509 fl_data_out => fl_data_out,
510 fl_data_in_ftu => fl_data_in_ftu,
511 fl_addr => fl_addr,
512 fl_addr_ftu => fl_addr_ftu
513 );
514 U_0 : w5300_modul
515 PORT MAP (
516 clk => clk,
517 wiz_reset => wiz_reset,
518 addr => wiz_addr,
519 data => wiz_data,
520 cs => wiz_cs,
521 wr => wiz_wr,
522 led => led1,
523 rd => wiz_rd,
524 int => wiz_int,
525 busy => busy,
526 new_config => new_config,
527 config_started => config_started,
528 config_started_ack => config_started_ack,
529 ping_ftu_start => ping_ftu_start,
530 ping_ftu_started => ping_ftu_started,
531 ping_ftu_ready => ping_ftu_ready,
532 sd_addr => sd_addr,
533 sd_data_out => sd_data_in,
534 sd_data_in => sd_data_out,
535 sd_write => sd_write,
536 sd_read => sd_read,
537 sd_started => sd_started,
538 sd_ready => sd_ready_internal,
539 sd_busy => sd_busy_internal,
540 dd_block_start => dd_block_start,
541 dd_block_start_ack => dd_block_start_ack,
542 dd_block_ready => dd_block_ready,
543 dd_addr => dd_addr,
544 dd_data_in => dd_data_out,
545 dd_read => dd_read,
546 dd_started => dd_started,
547 dd_ready => dd_ready_internal,
548 dd_busy => dd_busy_internal,
549 fl_addr => fl_addr,
550 fl_data_in => fl_data_out,
551 fl_read => fl_read,
552 fl_started => fl_started,
553 fl_ready => fl_ready_internal,
554 fl_busy => fl_busy_internal
555 );
556
557 -- Implicit buffered output assignments
558 dd_busy <= dd_busy_internal;
559 dd_ready <= dd_ready_internal;
560 fl_busy <= fl_busy_internal;
561 fl_ready <= fl_ready_internal;
562 sd_busy <= sd_busy_internal;
563 sd_ready <= sd_ready_internal;
564
565END beha;
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