source: firmware/FTM/ethernet/ethernet_modul_beha.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 32.9 KB
Line 
1-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol
2--
3-- Created:
4-- by - kai.users (tpkw.local.priv)
5-- at - 10:39:41 04/13/11
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12--LIBRARY FACT_FTM_lib;
13library ftm_definitions;
14USE ftm_definitions.ftm_array_types.all;
15USE ftm_definitions.ftm_constants.all;
16
17
18ENTITY ethernet_modul IS
19 PORT(
20 wiz_reset : OUT std_logic := '1';
21 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
22 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
23 wiz_cs : OUT std_logic := '1';
24 wiz_wr : OUT std_logic := '1';
25 wiz_rd : OUT std_logic := '1';
26 wiz_int : IN std_logic;
27 clk : IN std_logic;
28 sd_ready : OUT std_logic;
29 sd_busy : OUT std_logic;
30 led : OUT std_logic_vector (7 DOWNTO 0);
31 sd_read_ftu : IN std_logic;
32 sd_started_ftu : OUT std_logic := '0';
33 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
34 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
35 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
36 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
37 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
38 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
39 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
40 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
41 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
42 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
43 dead_time : OUT std_logic_vector (15 DOWNTO 0);
44 -- data from config ram
45 general_settings : OUT std_logic_vector (15 DOWNTO 0);
46 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
47 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
48 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
49 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
50 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
51 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
52 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
53 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
54 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
55 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
56 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
57 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
58 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
59 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
60 new_config : OUT std_logic := '0';
61 config_started : IN std_logic;
62 config_start_eth : IN std_logic;
63 config_started_eth : OUT std_logic := '0';
64 config_ready_eth : OUT std_logic := '0';
65 config_started_ack : OUT std_logic := '0';
66 fl_busy : OUT std_logic;
67 fl_ready : OUT std_logic;
68 fl_write_ftu : IN std_logic;
69 fl_started_ftu : OUT std_logic := '0';
70 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
71 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
72 ping_ftu_start : OUT std_logic := '0';
73 ping_ftu_started : IN std_logic;
74 ping_ftu_ready : IN std_logic;
75 dd_write_ftu : IN std_logic;
76 dd_started_ftu : OUT std_logic := '0';
77 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
78 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
79 dd_busy : OUT std_logic;
80 dd_ready : OUT std_logic;
81 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
82 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
83 dd_block_ready_ftu : IN std_logic;
84 dd_block_start_ack_ftu : OUT std_logic := '0';
85 dd_block_start_ftu : IN std_logic;
86 dd_send : IN std_logic;
87 dd_send_ack : OUT std_logic := '1';
88 dd_send_ready : OUT std_logic := '1';
89 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
90 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
91 ftu_error_send : IN std_logic;
92 ftu_error_send_ack : OUT std_logic := '1';
93 ftu_error_send_ready : OUT std_logic := '1';
94 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
95 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
96 trigger_counter_read : OUT std_logic := '0';
97 trigger_counter_valid : IN std_logic
98 );
99
100END ethernet_modul ;
101
102ARCHITECTURE beha OF ethernet_modul IS
103
104 -- Architecture declarations
105
106 -- Internal signal declarations
107 SIGNAL busy : std_logic := '1';
108 SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0);
109 SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0);
110 SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0";
111 SIGNAL sd_write : std_logic := '0';
112 SIGNAL sd_read : std_logic;
113 SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0');
114 SIGNAL sd_started : std_logic;
115 SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0);
116 SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0);
117 SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0);
118 SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0');
119 SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0);
120 SIGNAL config_ready_cc : std_logic := '0';
121 SIGNAL config_started_cc : std_logic := '0';
122 SIGNAL config_start_cc : std_logic;
123 SIGNAL fl_started : std_logic;
124 SIGNAL fl_read : std_logic := '0';
125 --
126 SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0);
127 SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0);
128 SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0);
129 SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0);
130 SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0";
131 SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0);
132 SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0);
133 SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0);
134 SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0);
135 SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0";
136 SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0);
137 SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0);
138 SIGNAL dd_read : std_logic;
139 SIGNAL dd_started : std_logic := '0';
140 SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0');
141 SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0);
142 SIGNAL dd_block_ready : std_logic := '0';
143 --
144 SIGNAL dd_block_start : std_logic := '0';
145 SIGNAL dd_block_start_ack : std_logic;
146 SIGNAL dd_write_general : std_logic := '0';
147 SIGNAL dd_write_general_ready : std_logic;
148 SIGNAL dd_write_general_started : std_logic;
149 SIGNAL dd_write : std_logic := '0';
150 SIGNAL dd_started_general : std_logic := '0';
151 SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0');
152 SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0');
153 SIGNAL get_header : std_logic;
154 SIGNAL get_header_started : std_logic := '0';
155 SIGNAL get_header_ready : std_logic := '0';
156 SIGNAL led2 : std_logic_vector(7 DOWNTO 0);
157 SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0);
158 SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0);
159 SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0);
160 SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0);
161
162 -- Implicit buffer signal declarations
163 SIGNAL dd_busy_internal : std_logic;
164 SIGNAL dd_ready_internal : std_logic;
165 SIGNAL fl_busy_internal : std_logic;
166 SIGNAL fl_ready_internal : std_logic;
167 SIGNAL sd_busy_internal : std_logic;
168 SIGNAL sd_ready_internal : std_logic;
169
170
171 -- Component Declarations
172 COMPONENT CRAM_4096_16b
173 PORT (
174 clka : IN std_logic ;
175 dina : IN std_logic_VECTOR (15 DOWNTO 0);
176 addra : IN std_logic_VECTOR (11 DOWNTO 0);
177 wea : IN std_logic_VECTOR (0 DOWNTO 0);
178 clkb : IN std_logic ;
179 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
180 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
181 );
182 END COMPONENT;
183 COMPONENT DRAM_4096_16b
184 PORT (
185 clka : IN std_logic ;
186 dina : IN std_logic_VECTOR (15 DOWNTO 0);
187 addra : IN std_logic_VECTOR (11 DOWNTO 0);
188 wea : IN std_logic_VECTOR (0 DOWNTO 0);
189 clkb : IN std_logic ;
190 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
191 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
192 );
193 END COMPONENT;
194 COMPONENT FRAM_4096_16b
195 PORT (
196 clka : IN std_logic ;
197 dina : IN std_logic_VECTOR (15 DOWNTO 0);
198 addra : IN std_logic_VECTOR (11 DOWNTO 0);
199 wea : IN std_logic_VECTOR (0 DOWNTO 0);
200 clkb : IN std_logic ;
201 addrb : IN std_logic_VECTOR (11 DOWNTO 0);
202 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
203 );
204 END COMPONENT;
205 COMPONENT cram_control
206 PORT (
207 clk : IN std_logic ;
208 led : OUT std_logic_vector (7 DOWNTO 0) := X"00";
209 cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
210 cram_data_out : IN std_logic_vector (15 DOWNTO 0);
211 cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
212 cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
213 cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
214 sd_write : IN std_logic ;
215 sd_read : IN std_logic ;
216 sd_read_ftu : IN std_logic ;
217 sd_busy : OUT std_logic := '1';
218 sd_started : OUT std_logic := '0';
219 sd_started_ftu : OUT std_logic := '0';
220 sd_ready : OUT std_logic := '0';
221 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
222 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
223 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
224 sd_addr : IN std_logic_vector (11 DOWNTO 0);
225 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
226 config_start_cc : IN std_logic ;
227 config_started_cc : OUT std_logic := '0';
228 config_ready_cc : OUT std_logic := '0';
229 -- data from config ram
230 general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
231 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
232 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
233 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
234 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
235 lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
236 lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
237 coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
238 coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
239 trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
240 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
241 dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
242 cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
243 cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
244 cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
245 cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
246 cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
247 cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
248 cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
249 cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
250 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
251 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
252 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
253 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
254 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
255 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
256 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
257 );
258 END COMPONENT;
259 COMPONENT dd_write_general_modul
260 PORT (
261 clk : IN std_logic ;
262 dd_write_general : IN std_logic ;
263 dd_write_general_started : OUT std_logic := '0';
264 dd_write_general_ready : OUT std_logic := '0';
265 dd_busy : IN std_logic ;
266 dd_write : OUT std_logic := '0';
267 dd_started : IN std_logic ;
268 dd_ready : IN std_logic ;
269 dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
270 dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
271 );
272 END COMPONENT;
273 COMPONENT dram_control
274 PORT (
275 clk : IN std_logic ;
276 dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
277 dram_data_out : IN std_logic_vector (15 DOWNTO 0);
278 dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
279 dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
280 dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
281 dd_block_start : IN std_logic ;
282 dd_block_start_ftu : IN std_logic ;
283 dd_block_start_ack : OUT std_logic := '0';
284 dd_block_start_ack_ftu : OUT std_logic := '0';
285 dd_block_ready : IN std_logic ;
286 dd_block_ready_ftu : IN std_logic ;
287 dd_read : IN std_logic ;
288 dd_write_ftu : IN std_logic ;
289 dd_write_general : IN std_logic ;
290 dd_busy : OUT std_logic := '1';
291 dd_started : OUT std_logic := '0';
292 dd_started_ftu : OUT std_logic := '0';
293 dd_started_general : OUT std_logic := '0';
294 dd_ready : OUT std_logic := '0';
295 dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
296 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
297 dd_data_in_general : IN std_logic_vector (15 DOWNTO 0);
298 dd_addr : IN std_logic_vector (11 DOWNTO 0);
299 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
300 dd_addr_general : IN std_logic_vector (11 DOWNTO 0)
301 );
302 END COMPONENT;
303 COMPONENT eth_config_modul
304 PORT (
305 clk : IN std_logic ;
306 config_start_eth : IN std_logic ;
307 config_started_eth : OUT std_logic := '0';
308 config_ready_eth : OUT std_logic := '0';
309 config_start_cc : OUT std_logic := '0';
310 config_started_cc : IN std_logic ;
311 config_ready_cc : IN std_logic
312 );
313 END COMPONENT;
314 COMPONENT fram_control
315 PORT (
316 clk : IN std_logic ;
317 fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
318 fram_data_out : IN std_logic_vector (15 DOWNTO 0);
319 fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
320 fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');
321 fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0";
322 fl_read : IN std_logic ;
323 fl_write_ftu : IN std_logic ;
324 fl_busy : OUT std_logic := '1';
325 fl_started : OUT std_logic := '0';
326 fl_started_ftu : OUT std_logic := '0';
327 fl_ready : OUT std_logic := '0';
328 fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
329 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
330 fl_addr : IN std_logic_vector (11 DOWNTO 0);
331 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0)
332 );
333 END COMPONENT;
334 COMPONENT header_modul
335 PORT (
336 clk : IN std_logic ;
337 get_header : IN std_logic ;
338 get_header_started : OUT std_logic := '0';
339 get_header_ready : OUT std_logic := '0';
340 trigger_counter_read : OUT std_logic := '0';
341 trigger_counter_valid : IN std_logic ;
342 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
343 header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0');
344 header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
345 header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
346 header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
347 );
348 END COMPONENT;
349 COMPONENT w5300_modul
350 PORT (
351 clk : IN std_logic ;
352 wiz_reset : OUT std_logic := '1';
353 addr : OUT std_logic_vector (9 DOWNTO 0);
354 data : INOUT std_logic_vector (15 DOWNTO 0);
355 cs : OUT std_logic := '1';
356 wr : OUT std_logic := '1';
357 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
358 rd : OUT std_logic := '1';
359 int : IN std_logic ;
360 busy : OUT std_logic := '1';
361 new_config : OUT std_logic := '0';
362 config_started : IN std_logic ;
363 config_started_ack : OUT std_logic := '0';
364 --
365 ping_ftu_start : OUT std_logic := '0';
366 ping_ftu_started : IN std_logic ;
367 ping_ftu_ready : IN std_logic ;
368 --
369 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
370 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
371 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
372 sd_write : OUT std_logic := '0';
373 sd_read : OUT std_logic := '0';
374 sd_started : IN std_logic ;
375 sd_ready : IN std_logic ;
376 sd_busy : IN std_logic ;
377 --
378 dd_block_start : OUT std_logic := '0';
379 dd_block_start_ack : IN std_logic ;
380 dd_block_ready : OUT std_logic := '1';
381 dd_send : IN std_logic ;
382 dd_send_ack : OUT std_logic := '1';
383 dd_send_ready : OUT std_logic := '1';
384 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
385 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
386 dd_read : OUT std_logic := '0';
387 dd_started : IN std_logic ;
388 dd_ready : IN std_logic ;
389 dd_busy : IN std_logic ;
390 dd_write_general : OUT std_logic := '0';
391 dd_write_general_started : IN std_logic ;
392 dd_write_general_ready : IN std_logic ;
393 --
394 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
395 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
396 fl_read : OUT std_logic := '0';
397 fl_started : IN std_logic ;
398 fl_ready : IN std_logic ;
399 fl_busy : IN std_logic ;
400 --
401 ftu_error_send : IN std_logic ;
402 ftu_error_send_ack : OUT std_logic := '1';
403 ftu_error_send_ready : OUT std_logic := '1';
404 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
405 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
406 --
407 get_header : OUT std_logic := '0';
408 get_header_started : IN std_logic ;
409 get_header_ready : IN std_logic ;
410 header_board_id : IN std_logic_vector (63 DOWNTO 0);
411 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
412 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
413 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0)
414 );
415 END COMPONENT;
416
417BEGIN
418
419 -- ModuleWare code(v1.9) for instance 'U_3' of 'or'
420 led <= led1 OR led2;
421
422 -- Instance port mappings.
423 U_1 : CRAM_4096_16b
424 PORT MAP (
425 clka => clk,
426 dina => cram_data_in,
427 addra => cram_addr_in,
428 wea => cram_we,
429 clkb => clk,
430 addrb => cram_addr_out,
431 doutb => cram_data_out
432 );
433 U_7 : DRAM_4096_16b
434 PORT MAP (
435 clka => clk,
436 dina => dram_data_in,
437 addra => dram_addr_in,
438 wea => dram_we,
439 clkb => clk,
440 addrb => dram_addr_out,
441 doutb => doutb1
442 );
443 U_5 : FRAM_4096_16b
444 PORT MAP (
445 clka => clk,
446 dina => fram_data_in,
447 addra => fram_addr_in,
448 wea => fram_we,
449 clkb => clk,
450 addrb => fram_addr_out,
451 doutb => doutb
452 );
453 U_2 : cram_control
454 PORT MAP (
455 clk => clk,
456 led => led2,
457 cram_data_in => cram_data_in,
458 cram_data_out => cram_data_out,
459 cram_addr_in => cram_addr_in,
460 cram_addr_out => cram_addr_out,
461 cram_we => cram_we,
462 sd_write => sd_write,
463 sd_read => sd_read,
464 sd_read_ftu => sd_read_ftu,
465 sd_busy => sd_busy_internal,
466 sd_started => sd_started,
467 sd_started_ftu => sd_started_ftu,
468 sd_ready => sd_ready_internal,
469 sd_data_in => sd_data_in,
470 sd_data_out => sd_data_out,
471 sd_data_out_ftu => sd_data_out_ftu,
472 sd_addr => sd_addr,
473 sd_addr_ftu => sd_addr_ftu,
474 config_start_cc => config_start_cc,
475 config_started_cc => config_started_cc,
476 config_ready_cc => config_ready_cc,
477 general_settings => general_settings,
478 lp_pt_freq => lp_pt_freq,
479 lp_pt_ratio => lp_pt_ratio,
480 lp1_amplitude => lp1_amplitude,
481 lp2_amplitude => lp2_amplitude,
482 lp1_delay => lp1_delay,
483 lp2_delay => lp2_delay,
484 coin_n_p => coin_n_p,
485 coin_n_c => coin_n_c,
486 trigger_delay => trigger_delay,
487 timemarker_delay => timemarker_delay,
488 dead_time => dead_time,
489 cc_R0 => cc_R0,
490 cc_R1 => cc_R1,
491 cc_R8 => cc_R8,
492 cc_R9 => cc_R9,
493 cc_R11 => cc_R11,
494 cc_R13 => cc_R13,
495 cc_R14 => cc_R14,
496 cc_R15 => cc_R15,
497 coin_win_p => coin_win_p,
498 coin_win_c => coin_win_c,
499 prescaling_FTU01 => prescaling_FTU01,
500 ftu_active_cr0 => ftu_active_cr0,
501 ftu_active_cr1 => ftu_active_cr1,
502 ftu_active_cr2 => ftu_active_cr2,
503 ftu_active_cr3 => ftu_active_cr3
504 );
505 U_9 : dd_write_general_modul
506 PORT MAP (
507 clk => clk,
508 dd_write_general => dd_write_general,
509 dd_write_general_started => dd_write_general_started,
510 dd_write_general_ready => dd_write_general_ready,
511 dd_busy => dd_busy_internal,
512 dd_write => dd_write,
513 dd_started => dd_started_general,
514 dd_ready => dd_ready_internal,
515 dd_addr => dd_addr1,
516 dd_data => dd_data
517 );
518 U_8 : dram_control
519 PORT MAP (
520 clk => clk,
521 dram_data_in => dram_data_in,
522 dram_data_out => doutb1,
523 dram_addr_in => dram_addr_in,
524 dram_addr_out => dram_addr_out,
525 dram_we => dram_we,
526 dd_block_start => dd_block_start,
527 dd_block_start_ftu => dd_block_start_ftu,
528 dd_block_start_ack => dd_block_start_ack,
529 dd_block_start_ack_ftu => dd_block_start_ack_ftu,
530 dd_block_ready => dd_block_ready,
531 dd_block_ready_ftu => dd_block_ready_ftu,
532 dd_read => dd_read,
533 dd_write_ftu => dd_write_ftu,
534 dd_write_general => dd_write,
535 dd_busy => dd_busy_internal,
536 dd_started => dd_started,
537 dd_started_ftu => dd_started_ftu,
538 dd_started_general => dd_started_general,
539 dd_ready => dd_ready_internal,
540 dd_data_out => dd_data_out,
541 dd_data_in_ftu => dd_data_in_ftu,
542 dd_data_in_general => dd_data,
543 dd_addr => dd_addr,
544 dd_addr_ftu => dd_addr_ftu,
545 dd_addr_general => dd_addr1
546 );
547 U_4 : eth_config_modul
548 PORT MAP (
549 clk => clk,
550 config_start_eth => config_start_eth,
551 config_started_eth => config_started_eth,
552 config_ready_eth => config_ready_eth,
553 config_start_cc => config_start_cc,
554 config_started_cc => config_started_cc,
555 config_ready_cc => config_ready_cc
556 );
557 U_6 : fram_control
558 PORT MAP (
559 clk => clk,
560 fram_data_in => fram_data_in,
561 fram_data_out => doutb,
562 fram_addr_in => fram_addr_in,
563 fram_addr_out => fram_addr_out,
564 fram_we => fram_we,
565 fl_read => fl_read,
566 fl_write_ftu => fl_write_ftu,
567 fl_busy => fl_busy_internal,
568 fl_started => fl_started,
569 fl_started_ftu => fl_started_ftu,
570 fl_ready => fl_ready_internal,
571 fl_data_out => fl_data_out,
572 fl_data_in_ftu => fl_data_in_ftu,
573 fl_addr => fl_addr,
574 fl_addr_ftu => fl_addr_ftu
575 );
576 U_10 : header_modul
577 PORT MAP (
578 clk => clk,
579 get_header => get_header,
580 get_header_started => get_header_started,
581 get_header_ready => get_header_ready,
582 trigger_counter_read => trigger_counter_read,
583 trigger_counter_valid => trigger_counter_valid,
584 trigger_counter => trigger_counter,
585 header_board_id => header_board_id,
586 header_firmware_id => header_firmware_id,
587 header_trigger_counter => header_trigger_counter,
588 header_timestamp_counter => header_timestamp_counter
589 );
590 U_0 : w5300_modul
591 PORT MAP (
592 clk => clk,
593 wiz_reset => wiz_reset,
594 addr => wiz_addr,
595 data => wiz_data,
596 cs => wiz_cs,
597 wr => wiz_wr,
598 led => led1,
599 rd => wiz_rd,
600 int => wiz_int,
601 busy => busy,
602 new_config => new_config,
603 config_started => config_started,
604 config_started_ack => config_started_ack,
605 ping_ftu_start => ping_ftu_start,
606 ping_ftu_started => ping_ftu_started,
607 ping_ftu_ready => ping_ftu_ready,
608 sd_addr => sd_addr,
609 sd_data_out => sd_data_in,
610 sd_data_in => sd_data_out,
611 sd_write => sd_write,
612 sd_read => sd_read,
613 sd_started => sd_started,
614 sd_ready => sd_ready_internal,
615 sd_busy => sd_busy_internal,
616 dd_block_start => dd_block_start,
617 dd_block_start_ack => dd_block_start_ack,
618 dd_block_ready => dd_block_ready,
619 dd_send => dd_send,
620 dd_send_ack => dd_send_ack,
621 dd_send_ready => dd_send_ready,
622 dd_addr => dd_addr,
623 dd_data_in => dd_data_out,
624 dd_read => dd_read,
625 dd_started => dd_started,
626 dd_ready => dd_ready_internal,
627 dd_busy => dd_busy_internal,
628 dd_write_general => dd_write_general,
629 dd_write_general_started => dd_write_general_started,
630 dd_write_general_ready => dd_write_general_ready,
631 fl_addr => fl_addr,
632 fl_data_in => fl_data_out,
633 fl_read => fl_read,
634 fl_started => fl_started,
635 fl_ready => fl_ready_internal,
636 fl_busy => fl_busy_internal,
637 ftu_error_send => ftu_error_send,
638 ftu_error_send_ack => ftu_error_send_ack,
639 ftu_error_send_ready => ftu_error_send_ready,
640 ftu_error_calls => ftu_error_calls,
641 ftu_error_data => ftu_error_data,
642 get_header => get_header,
643 get_header_started => get_header_started,
644 get_header_ready => get_header_ready,
645 header_board_id => header_board_id,
646 header_firmware_id => header_firmware_id,
647 header_trigger_counter => header_trigger_counter,
648 header_timestamp_counter => header_timestamp_counter
649 );
650
651 -- Implicit buffered output assignments
652 dd_busy <= dd_busy_internal;
653 dd_ready <= dd_ready_internal;
654 fl_busy <= fl_busy_internal;
655 fl_ready <= fl_ready_internal;
656 sd_busy <= sd_busy_internal;
657 sd_ready <= sd_ready_internal;
658
659END beha;
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