source: firmware/FTM/ethernet/w5300_modul.vhd@ 10323

Last change on this file since 10323 was 10256, checked in by weitzel, 15 years ago
new version of FTM ethernet module; first version of clock conditioner
File size: 42.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.all;
23USE IEEE.STD_LOGIC_ARITH.all;
24USE IEEE.STD_LOGIC_UNSIGNED.all;
25-- LIBRARY FACT_FTM_lib;
26-- USE FACT_FTM_lib.ftm_array_types.all;
27-- USE FACT_FTM_lib.ftm_constants.all;
28library ftm_definitions;
29USE ftm_definitions.ftm_array_types.all;
30USE ftm_definitions.ftm_constants.all;
31
32-- Uncomment the following library declaration if instantiating
33-- any Xilinx primitives in this code.
34library UNISIM;
35use UNISIM.VComponents.all;
36
37
38ENTITY w5300_modul IS
39 PORT(
40 clk : IN std_logic;
41 wiz_reset : OUT std_logic := '1';
42 addr : OUT std_logic_vector (9 DOWNTO 0);
43 data : INOUT std_logic_vector (15 DOWNTO 0);
44 cs : OUT std_logic := '1';
45 wr : OUT std_logic := '1';
46 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
47 rd : OUT std_logic := '1';
48 int : IN std_logic;
49 busy : OUT std_logic := '1';
50 new_config : OUT std_logic := '0';
51 config_started : IN std_logic;
52 config_started_ack : OUT std_logic := '0';
53 --
54 ping_ftu_start : OUT std_logic := '0';
55 ping_ftu_started : IN std_logic;
56 ping_ftu_ready : IN std_logic;
57 --
58 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
59 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
60 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
61 sd_write : OUT std_logic := '0';
62 sd_read : OUT std_logic := '0';
63 sd_started : IN std_logic;
64 sd_ready : IN std_logic;
65 sd_busy : IN std_logic;
66 --
67 dd_block_start : OUT std_logic := '0';
68 dd_block_start_ack : IN std_logic;
69 dd_block_ready : OUT std_logic := '1';
70 dd_send : IN std_logic;
71 dd_send_ack : OUT std_logic := '1';
72 dd_send_ready : OUT std_logic := '1';
73 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
74 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
75 dd_read : OUT std_logic := '0';
76 dd_started : IN std_logic;
77 dd_ready : IN std_logic;
78 dd_busy : IN std_logic;
79 dd_write_general : OUT std_logic := '0';
80 dd_write_general_started : IN std_logic;
81 dd_write_general_ready : IN std_logic;
82 --
83 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
84 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
85 fl_read : OUT std_logic := '0';
86 fl_started : IN std_logic;
87 fl_ready : IN std_logic;
88 fl_busy : IN std_logic;
89 --
90 get_header : OUT std_logic := '0';
91 get_header_started : IN std_logic;
92 get_header_ready : IN std_logic;
93 header_board_id : IN std_logic_vector (63 DOWNTO 0);
94 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
95 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
96 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0)
97 );
98
99END w5300_modul ;
100
101architecture Behavioral of w5300_modul is
102
103 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
104 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
105 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED,
106 READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
107 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
108 WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01);
109 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
110 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
111 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_END);
112 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END);
113 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END);
114 type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END);
115 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST);
116 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
117 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
118
119 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
120
121 signal par_addr : std_logic_vector (9 downto 0) := (others => '0');
122 signal par_data : std_logic_vector (15 downto 0) := (others => '0');
123 signal data_read : std_logic_vector (15 downto 0) := (others => '0');
124
125 signal state_init, next_state , next_state_tmp : state_init_type := RESET;
126 signal read_addr_state : state_init_type := RESET;
127 signal count : std_logic_vector (2 downto 0) := "000";
128 signal state_write : state_write_type := WR_START;
129 signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
130 signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
131 signal state_read_data : state_read_data_type := RD_1;
132 signal next_state_read_data : state_read_data_type := RD_CMD;
133 signal state_write_sd : state_write_sd_type := WRITE_SD_START;
134 signal state_read_sd : state_read_sd_type := READ_SD_START;
135 signal state_read_fl : state_read_fl_type := READ_FL_START;
136 signal state_ping : state_ping_type := PING_START;
137 signal state_read_dd : state_read_dd_type := READ_DD_START;
138 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START;
139
140
141 signal interrupt_ignore : std_logic := '1';
142 signal int_flag : std_logic := '0';
143
144 signal zaehler : std_logic_vector (19 downto 0) := (others => '0');
145 signal data_cnt : integer := 0;
146 signal header_cnt : integer := 0;
147 signal socket_cnt : std_logic_vector (2 downto 0) := "000";
148
149 signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
150 signal write_length_bytes : std_logic_vector (16 downto 0);
151
152 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
153 signal chk_recv_cntr : integer range 0 to 10000 := 0;
154
155 signal next_packet_data_cnt : integer range 0 to 4095 := 0;
156 signal rx_packets_cnt : std_logic_vector (15 downto 0);
157 signal new_config_flag : std_logic := '0';
158
159 signal local_write_length : std_logic_vector (16 downto 0);
160 signal local_socket_nr : std_logic_vector (2 downto 0);
161
162 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0);
163 signal cmd_array : cmd_array_type;
164 signal internal_cmd : std_logic := '0';
165
166 -- -- --
167 signal led_int : std_logic_vector (7 downto 0) := X"00";
168 signal led_cnt : integer range 0 to 2**22 := 0;
169 -- -- --
170
171 signal local_sd_addr : std_logic_vector (11 downto 0);
172 signal local_sd_data : std_logic_vector (15 downto 0);
173
174
175begin
176
177 --synthesis translate_off
178 RST_TIME <= X"00120";
179 --synthesis translate_on
180
181
182 w5300_init_proc : process (clk, int)
183 begin
184
185 if rising_edge (clk) then
186
187 -- -- --
188 led <= led_int;
189 -- -- --
190
191 -- Interrupt low
192 if (int = '0') and (interrupt_ignore = '0') then
193 case state_interrupt_1 is
194 when IR1_01 =>
195 int_flag <= '1';
196 busy <= '1';
197 state_interrupt_1 <= IR1_02;
198 when IR1_02 =>
199 state_interrupt_1 <= IR1_03;
200 when IR1_03 =>
201 state_init <= INTERRUPT;
202 socket_cnt <= "000";
203 zaehler <= X"00000";
204 count <= "000";
205 int_flag <= '0';
206 interrupt_ignore <= '1';
207 state_interrupt_1 <= IR1_04;
208 when others =>
209 null;
210 end case;
211 end if; -- int = '0'
212
213 if int_flag = '0' then
214 case state_init is
215 -- Interrupt
216 when INTERRUPT =>
217 case state_interrupt_2 is
218 when IR2_01 =>
219 par_addr <= W5300_IR;
220 state_init <= READ_REG;
221 next_state <= INTERRUPT;
222 state_interrupt_2 <= IR2_02;
223 when IR2_02 =>
224 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
225 state_interrupt_2 <= IR2_03;
226 else
227 socket_cnt <= socket_cnt + 1;
228 if (socket_cnt = W5300_LAST_SOCKET) then
229 state_interrupt_2 <= IR2_06;
230 else
231 state_interrupt_2 <= IR2_02;
232 end if;
233 end if;
234 when IR2_03 =>
235 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
236 state_init <= READ_REG;
237 next_state <= INTERRUPT;
238 state_interrupt_2 <= IR2_04;
239 when IR2_04 =>
240 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
241 par_data <= data_read; -- clear Interrupts
242 state_init <= WRITE_REG;
243 next_state <= INTERRUPT;
244 state_interrupt_2 <= IR2_05;
245 when IR2_05 =>
246 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
247 par_data <= X"0010"; -- CLOSE
248 state_init <= WRITE_REG;
249 next_state <= INTERRUPT;
250 socket_cnt <= socket_cnt + 1;
251 if (socket_cnt = W5300_LAST_SOCKET) then
252 state_interrupt_2 <= IR2_06;
253 else
254 state_interrupt_2 <= IR2_01;
255 end if;
256
257 when IR2_06 =>
258 state_interrupt_1 <= IR1_01;
259 state_interrupt_2 <= IR2_01;
260 socket_cnt <= "000";
261 state_init <= RESET;
262 end case;
263
264 -- reset W5300
265 when RESET =>
266 busy <= '1';
267 zaehler <= zaehler + 1;
268 wiz_reset <= '0';
269 if (zaehler >= X"00064") then -- wait 2µs
270 wiz_reset <= '1';
271 end if;
272 if (zaehler = RST_TIME) then -- wait 10ms
273 zaehler <= X"00000";
274 socket_cnt <= "000";
275 count <= "000";
276 interrupt_ignore <= '0';
277 rd <= '1';
278 wr <= '1';
279 cs <= '1';
280 -- reset states
281 state_write <= WR_START;
282 state_init <= INIT;
283 state_read_data <= RD_1;
284 next_state_read_data <= RD_CMD;
285 state_write_sd <= WRITE_SD_START;
286 state_read_sd <= READ_SD_START;
287 state_read_fl <= READ_FL_START;
288 state_ping <= PING_START;
289 state_read_dd <= READ_DD_START;
290 state_read_dd_block <= READ_DD_BLOCK_START;
291 -- reset output signals
292 new_config <= '0';
293 config_started_ack <= '1';
294 ping_ftu_start <= '0';
295 sd_write <= '0';
296 sd_read <= '0';
297 dd_block_start <= '0';
298 dd_block_ready <= '1';
299 dd_send_ack <= '1';
300 dd_send_ready <= '1';
301 dd_read <= '0';
302 dd_write_general <= '0';
303 fl_read <= '0';
304 -- set internal signals
305 new_config_flag <= '0';
306 chk_recv_cntr <= 0;
307 next_packet_data_cnt <= 0;
308 internal_cmd <= '0';
309 -- -- --
310 led_int <= X"00";
311 -- -- --
312 end if;
313
314 -- Init
315 when INIT =>
316 par_addr <= W5300_MR;
317 par_data <= X"0000";
318 state_init <= WRITE_REG;
319 next_state <= IM;
320
321 -- Interrupt Mask
322 when IM =>
323 par_addr <= W5300_IMR;
324 par_data <= X"00FF"; -- S0-S7 Interrupts
325 state_init <= WRITE_REG;
326 next_state <= MT;
327
328 -- Memory Type
329 when MT =>
330 par_addr <= W5300_MTYPER;
331 par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer
332 state_init <= WRITE_REG;
333 next_state <= STX;
334
335 -- Socket TX Memory Size
336 when STX =>
337 par_data <= X"4000"; -- 64K TX for socket 0, others 0
338
339 par_addr <= W5300_TMS01R;
340 state_init <= WRITE_REG;
341 next_state <= STX1;
342 when STX1 =>
343 par_data <= X"0000";
344 par_addr <= W5300_TMS23R;
345 state_init <= WRITE_REG;
346 next_state <= STX2;
347 when STX2 =>
348 par_addr <= W5300_TMS45R;
349 state_init <= WRITE_REG;
350 next_state <= STX3;
351 when STX3 =>
352 par_addr <= W5300_TMS67R;
353 state_init <= WRITE_REG;
354 next_state <= SRX;
355
356 -- Socket RX Memory Size
357 when SRX =>
358 par_data <= X"4000"; -- 64K RX for socket 0, others 0
359
360 par_addr <= W5300_RMS01R;
361 state_init <= WRITE_REG;
362 next_state <= SRX1;
363 when SRX1 =>
364 par_data <= X"0000";
365 par_addr <= W5300_RMS23R;
366 state_init <= WRITE_REG;
367 next_state <= SRX2;
368 when SRX2 =>
369 par_addr <= W5300_RMS45R;
370 state_init <= WRITE_REG;
371 next_state <= SRX3;
372 when SRX3 =>
373 par_addr <= W5300_RMS67R;
374 state_init <= WRITE_REG;
375 next_state <= MAC;
376
377 -- MAC
378 when MAC =>
379 par_addr <= W5300_SHAR;
380 par_data <= MAC_ADDRESS (0);
381 state_init <= WRITE_REG;
382 next_state <= MAC1;
383 when MAC1 =>
384 par_addr <= W5300_SHAR + 2;
385 par_data <= MAC_ADDRESS (1);
386 state_init <= WRITE_REG;
387 next_state <= MAC2;
388 when MAC2 =>
389 par_addr <= W5300_SHAR + 4;
390 par_data <= MAC_ADDRESS (2);
391 state_init <= WRITE_REG;
392 next_state <= GW;
393
394 -- Gateway
395 when GW =>
396 par_addr <= W5300_GAR;
397 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8);
398 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8);
399 state_init <= WRITE_REG;
400 next_state <= GW1;
401 when GW1 =>
402 par_addr <= W5300_GAR + 2;
403 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8);
404 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8);
405 state_init <= WRITE_REG;
406 next_state <= SNM;
407
408 -- Subnet Mask
409 when SNM =>
410 par_addr <= W5300_SUBR;
411 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8);
412 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8);
413 state_init <= WRITE_REG;
414 next_state <= SNM1;
415 when SNM1 =>
416 par_addr <= W5300_SUBR + 2;
417 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8);
418 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8);
419 state_init <= WRITE_REG;
420 next_state <= IP;
421 -- Own IP-Address
422 when IP =>
423 par_addr <= W5300_SIPR;
424 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8);
425 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8);
426 state_init <= WRITE_REG;
427 next_state <= IP1;
428 when IP1 =>
429 par_addr <= W5300_SIPR + 2;
430 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8);
431 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8);
432 state_init <= WRITE_REG;
433 next_state <= SI;
434 -- Socket Init
435 when SI =>
436 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
437 par_data <= X"0101"; -- ALIGN, TCP
438 state_init <= WRITE_REG;
439 next_state <= SI1;
440 -- Sx Interrupt Mask
441 when SI1 =>
442 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
443 par_data <= X"000A"; -- TIMEOUT, DISCON
444 state_init <= WRITE_REG;
445 next_state <= SI2;
446 when SI2 =>
447 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
448 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
449 state_init <= WRITE_REG;
450 next_state <= SI3;
451 when SI3 =>
452 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
453 par_data <= X"0001"; -- OPEN
454 state_init <= WRITE_REG;
455 next_state <= SI4;
456 when SI4 =>
457 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
458 state_init <= READ_REG;
459 next_state <= SI5;
460 when SI5 =>
461 if (data_read (7 downto 0) = X"13") then -- is open?
462 state_init <= SI6;
463 else
464 state_init <= SI4;
465 end if;
466 when SI6 =>
467 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
468 par_data <= X"0002"; -- LISTEN
469 state_init <= WRITE_REG;
470 socket_cnt <= socket_cnt + 1;
471 if (socket_cnt = W5300_LAST_SOCKET) then
472 socket_cnt <= "000";
473 next_state <= ESTABLISH; -- All Sockets open
474 else
475 next_state <= SI; -- Next Socket
476 end if;
477 -- End Socket Init
478
479 when ESTABLISH =>
480 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
481 state_init <= READ_REG;
482 next_state <= EST1;
483 when EST1 =>
484 case data_read (7 downto 0) is
485 when X"17" => -- established
486 if (socket_cnt = W5300_LAST_SOCKET) then
487 socket_cnt <= "000";
488 busy <= '0';
489 state_init <= MAIN;
490 -- -- --
491 config_started_ack <= '0';
492 dd_block_ready <= '0';
493 dd_send_ack <= '0';
494 dd_send_ready <= '0';
495 led_int <= X"00";
496 -- -- --
497 else
498 socket_cnt <= socket_cnt + 1;
499 state_init <= ESTABLISH;
500 end if;
501 when others =>
502 state_init <= ESTABLISH;
503 -- -- --
504 -- Just for fun...
505 if (led_cnt = 1100000) then
506 if (led_int = X"00") then
507 led_int <= X"18";
508 else
509 led_int (7 downto 4) <= led_int (6 downto 4) & '0';
510 led_int (3 downto 0) <= '0' & led_int (3 downto 1);
511 end if;
512 led_cnt <= 0;
513 else
514 led_cnt <= led_cnt + 1;
515 end if;
516 -- -- --
517 end case;
518
519 when CONFIG =>
520 new_config <= '1';
521 config_started_ack <= '0';
522 if (config_started = '1') then
523 new_config <= '0';
524 config_started_ack <= '1';
525 state_init <= MAIN;
526 end if;
527
528 -- main "loop"
529 when MAIN =>
530 chk_recv_cntr <= chk_recv_cntr + 1;
531 if (chk_recv_cntr = 1000) then
532 chk_recv_cntr <= 0;
533 state_read_data <= RD_1;
534 state_init <= READ_DATA;
535 busy <= '1';
536 elsif (dd_send = '1') then
537 internal_cmd <= '1';
538 dd_send_ack <= '1';
539 dd_send_ready <= '0';
540 -- "simulate" command read dynamic data block
541 cmd_array (0) <= CMD_START_DELIMITER;
542 cmd_array (1) <= CMD_READ;
543 cmd_array (2) <= PAR_READ_DD;
544 state_read_data <= RD_CMD_PARSE;
545 state_init <= READ_DATA;
546 end if;
547
548
549 -- read data from socket 0
550 when READ_DATA =>
551 case state_read_data is
552 when RD_1 =>
553 par_addr <= W5300_S0_RX_RSR;
554 state_init <= READ_REG;
555 next_state <= READ_DATA;
556 state_read_data <= RD_2;
557 when RD_2 =>
558 socket_rx_received (31 downto 16) <= data_read;
559 par_addr <= W5300_S0_RX_RSR + X"2";
560 state_init <= READ_REG;
561 next_state <= READ_DATA;
562 state_read_data <= RD_3;
563 when RD_3 =>
564 socket_rx_received (15 downto 0) <= data_read;
565 state_read_data <= RD_4;
566 when RD_4 =>
567 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
568 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
569 state_read_data <= RD_5;
570 else
571 busy <= '0';
572 state_init <= MAIN;
573 end if;
574 when RD_5 =>
575 if (rx_packets_cnt > 0) then
576 rx_packets_cnt <= rx_packets_cnt - '1';
577 par_addr <= W5300_S0_RX_FIFOR;
578 state_init <= READ_REG;
579 next_state <= READ_DATA;
580 state_read_data <= next_state_read_data;
581 else
582 state_read_data <= RD_END;
583 end if;
584
585 when RD_END =>
586 if (internal_cmd = '0') then
587 par_addr <= W5300_S0_CR;
588 par_data <= X"0040"; -- RECV
589 state_init <= WRITE_REG;
590 else
591 internal_cmd <= '0';
592 end if;
593 if (new_config_flag = '1') then
594 new_config_flag <= '0';
595 next_state <= CONFIG;
596 else
597 next_state <= MAIN;
598 end if;
599
600
601 -------------------------
602 -- command handling
603 -------------------------
604
605 -- read command (5 words)
606 when RD_CMD =>
607 cmd_array (next_packet_data_cnt) <= data_read;
608 next_packet_data_cnt <= next_packet_data_cnt + 1;
609 -- look for command start
610 if (next_packet_data_cnt = 0) then
611 if (data_read /= CMD_START_DELIMITER) then
612 next_packet_data_cnt <= 0;
613 end if;
614 end if;
615 -- last command-word
616 if (next_packet_data_cnt = 4) then
617 next_packet_data_cnt <= 0;
618 state_read_data <= RD_CMD_PARSE;
619 else
620 state_read_data <= RD_5;
621 end if;
622
623 -- process commands and parameters
624 when RD_CMD_PARSE =>
625 case cmd_array (1) is
626
627 when CMD_TLED =>
628 led_int <= NOT led_int;
629 state_read_data <= RD_5;
630
631 when CMD_WRITE =>
632 case cmd_array (2) is
633 -- write to address in static data block
634 when PAR_WRITE_SD_ADDR =>
635 new_config_flag <= '1';
636 next_state_read_data <= RD_WRITE_SD_ADDR;
637 state_read_data <= RD_5;
638 -- write static data block
639 when PAR_WRITE_SD =>
640 new_config_flag <= '1';
641 next_state_read_data <= RD_WRITE_SD_BLOCK;
642 state_read_data <= RD_5;
643 when others =>
644 state_read_data <= RD_5;
645 end case; -- cmd_array (2)
646
647 when CMD_READ =>
648 case cmd_array (2) is
649 -- read from address in static data block
650 when PAR_READ_SD_ADDR =>
651 next_state_read_data <= RD_READ_SD_ADDR;
652 state_read_data <= RD_5;
653 -- read static data block
654 when PAR_READ_SD =>
655 state_read_data <= RD_READ_SD_BLOCK;
656 -- read dynamic data block
657 when PAR_READ_DD =>
658 state_read_data <= RD_READ_DD_BLOCK;
659 when others =>
660 state_read_data <= RD_5;
661 end case; -- cmd_array (2)
662
663 when CMD_PING =>
664 state_ping <= PING_START;
665 state_read_data <= RD_PING;
666
667 when others =>
668 state_read_data <= RD_5;
669
670 end case; -- cmd_array (1)
671
672
673 -- ping all FTUs and write FTU-list to ethernet
674 when RD_PING =>
675 case state_ping is
676 when PING_START =>
677 ping_ftu_start <= '1';
678 if (ping_ftu_started = '1') then
679 ping_ftu_start <= '0';
680 state_ping <= PING_WAIT;
681 end if;
682 when PING_WAIT =>
683 if (ping_ftu_ready = '1') then
684 state_ping <= PING_WRITE_LIST;
685 end if;
686 when PING_WRITE_LIST =>
687 state_read_data <= RD_5;
688 read_addr_state <= READ_FROM_FL_ADDR;
689 local_sd_addr <= X"000"; --start at address 0x000
690 local_write_length <= "00000" & FL_BLOCK_SIZE;
691 next_state_read_data <= RD_CMD;
692 next_state <= READ_DATA;
693 state_init <= WRITE_DATA;
694 end case;
695
696 -- read dynamic data block and write it to ethernet
697 when RD_READ_DD_BLOCK =>
698 case state_read_dd_block is
699 when READ_DD_BLOCK_START =>
700 dd_block_start <= '1';
701 dd_block_ready <= '0';
702 if (dd_block_start_ack = '1') then
703 dd_block_start <= '0';
704 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;
705 end if;
706 -- write on-time counter and tempertures to dd-block
707 when READ_DD_BLOCK_WRITE_GENERAL =>
708 dd_write_general <= '1';
709 if (dd_write_general_started = '1') then
710 dd_write_general <= '0';
711 state_read_dd_block <= READ_DD_BLOCK_WRITE;
712 end if;
713 -- write dd-block to ethernet when on-time counter and temperatures are ready
714 when READ_DD_BLOCK_WRITE =>
715 if (dd_write_general_ready = '1') then
716 read_addr_state <= READ_FROM_DD_ADDR;
717 local_sd_addr <= X"000"; -- start at address 0x000
718 local_write_length <= "00000" & DD_BLOCK_SIZE;
719 state_read_dd_block <= READ_DD_BLOCK_END;
720 next_state <= READ_DATA;
721 state_init <= WRITE_DATA;
722 end if;
723 when READ_DD_BLOCK_END =>
724 dd_block_ready <= '1';
725 next_state_read_data <= RD_CMD;
726 --
727 if (internal_cmd = '1') then
728 state_read_dd_block <= READ_DD_BLOCK_INTERN;
729 else
730 state_read_dd_block <= READ_DD_BLOCK_START;
731 state_read_data <= RD_5;
732 end if;
733 when READ_DD_BLOCK_INTERN =>
734 if (dd_send = '0') then
735 dd_send_ready <= '1';
736 dd_send_ack <= '0';
737 state_read_dd_block <= READ_DD_BLOCK_START;
738 state_read_data <= RD_5;
739 end if;
740
741 end case;
742
743 -- read static data block and write it to ethernet
744 when RD_READ_SD_BLOCK =>
745 state_read_data <= RD_5;
746 read_addr_state <= READ_FROM_SD_ADDR;
747 local_sd_addr <= X"000"; -- start at address 0x000
748 local_write_length <= "00000" & SD_BLOCK_SIZE;
749 next_state_read_data <= RD_CMD;
750 next_state <= READ_DATA;
751 state_init <= WRITE_DATA;
752
753 -- read from address in static data ram and write data to ethernet
754 when RD_READ_SD_ADDR =>
755 state_read_data <= RD_5;
756 read_addr_state <= READ_FROM_SD_ADDR;
757 local_sd_addr <= data_read (11 downto 0);
758 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
759 next_state_read_data <= RD_CMD;
760 next_state <= READ_DATA;
761 state_init <= WRITE_DATA;
762
763 -- read static data block from ethernet and write it to static data ram
764 when RD_WRITE_SD_BLOCK =>
765 state_read_data <= RD_5;
766 next_packet_data_cnt <= next_packet_data_cnt + 1;
767 local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12);
768 local_sd_data <= data_read;
769 next_state <= READ_DATA;
770 state_init <= WRITE_TO_SD_ADDR;
771 -- last word
772 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
773 next_packet_data_cnt <= 0;
774 next_state_read_data <= RD_CMD;
775 end if;
776
777 -- write to address in static data ram
778 when RD_WRITE_SD_ADDR =>
779 state_read_data <= RD_5;
780 next_packet_data_cnt <= next_packet_data_cnt + 1;
781 if (next_packet_data_cnt = 0) then
782 local_sd_addr <= data_read (11 downto 0);
783 else
784 local_sd_data <= data_read;
785 next_packet_data_cnt <= 0;
786 next_state_read_data <= RD_CMD;
787 next_state <= READ_DATA;
788 state_init <= WRITE_TO_SD_ADDR;
789 end if;
790
791 end case; -- state_read_data
792
793
794 -- read from header modul
795 when READ_FROM_HEADER_MODUL =>
796 state_init <= next_state;
797 case header_cnt is
798 when 0 =>
799 local_sd_data <= header_board_id (63 DOWNTO 48);
800 when 1 =>
801 local_sd_data <= header_board_id (47 DOWNTO 32);
802 when 2 =>
803 local_sd_data <= header_board_id (31 DOWNTO 16);
804 when 3 =>
805 local_sd_data <= header_board_id (15 DOWNTO 0);
806 when 4 =>
807 local_sd_data <= header_firmware_id;
808 when 5 =>
809 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
810 when 6 =>
811 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
812 when 7 =>
813 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
814 when 8 =>
815 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
816 when 9 =>
817 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
818 when 10 =>
819 local_sd_data <= X"FFFF"; -- spare
820 when others =>
821 null;
822 end case;
823
824 -- read from ftu list ram
825 when READ_FROM_FL_ADDR =>
826 case state_read_fl is
827 when READ_FL_START =>
828 if (fl_busy = '0') then
829 fl_addr <= local_sd_addr;
830 fl_read <= '1';
831 state_read_fl <= READ_FL_WAIT;
832 end if;
833 when READ_FL_WAIT =>
834 if (fl_started = '1') then
835 state_read_fl <= READ_FL_END;
836 end if;
837 when READ_FL_END =>
838 if (fl_ready = '1') then
839 local_sd_data <= fl_data_in;
840 fl_read <= '0';
841 state_read_fl <= READ_FL_START;
842 state_init <= next_state;
843 end if;
844 end case;
845
846 -- read from dynamic data block
847 when READ_FROM_DD_ADDR =>
848 case state_read_dd is
849 when READ_DD_START =>
850 if (dd_busy = '0') then
851 dd_addr <= local_sd_addr;
852 dd_read <= '1';
853 state_read_dd <= READ_DD_WAIT;
854 end if;
855 when READ_DD_WAIT =>
856 if (dd_started = '1') then
857 state_read_dd <= READ_DD_END;
858 end if;
859 when READ_DD_END =>
860 if (dd_ready = '1') then
861 local_sd_data <= dd_data_in;
862 dd_read <= '0';
863 state_read_dd <= READ_DD_START;
864 state_init <= next_state;
865 end if;
866 end case;
867
868 -- read from static data block
869 when READ_FROM_SD_ADDR =>
870 case state_read_sd is
871 when READ_SD_START =>
872 if (sd_busy = '0') then
873 sd_addr <= local_sd_addr;
874 sd_read <= '1';
875 state_read_sd <= READ_SD_WAIT;
876 end if;
877 when READ_SD_WAIT =>
878 if (sd_started = '1') then
879 state_read_sd <= READ_SD_END;
880 end if;
881 when READ_SD_END =>
882 if (sd_ready = '1') then
883 local_sd_data <= sd_data_in;
884 sd_read <= '0';
885 state_read_sd <= READ_SD_START;
886 state_init <= next_state;
887 end if;
888 end case;
889
890 -- write to static data block
891 when WRITE_TO_SD_ADDR =>
892 case state_write_sd is
893 when WRITE_SD_START =>
894 if (sd_busy = '0') then
895 sd_addr <= local_sd_addr;
896 sd_data_out <= local_sd_data;
897 sd_write <= '1';
898 state_write_sd <= WRITE_SD_WAIT;
899 end if;
900 when WRITE_SD_WAIT =>
901 if (sd_started = '1') then
902 sd_write <= '0';
903 state_write_sd <= WRITE_SD_END;
904 end if;
905 when WRITE_SD_END =>
906 if (sd_ready = '1') then
907 state_write_sd <= WRITE_SD_START;
908 state_init <= next_state;
909 end if;
910 end case;
911
912 -- write to ethernet interface
913 when WRITE_DATA =>
914 case state_write is
915 when WR_START =>
916 state_write <= WR_LENGTH;
917 when WR_LENGTH =>
918 local_socket_nr <= "000";
919 next_state_tmp <= next_state;
920 write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2)
921 data_cnt <= 0;
922 header_cnt <= 0;
923 state_write <= WR_01;
924 -- Check FIFO Size
925 when WR_01 =>
926 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
927 state_init <= READ_REG;
928 next_state <= WRITE_DATA;
929 state_write <= WR_02;
930 when WR_02 =>
931 socket_tx_free (31 downto 16) <= data_read;
932 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
933 state_init <= READ_REG;
934 next_state <= WRITE_DATA;
935 state_write <= WR_03;
936 when WR_03 =>
937 socket_tx_free (15 downto 0) <= data_read;
938 state_write <= WR_04;
939 when WR_04 =>
940 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
941 state_write <= WR_01;
942 else
943 state_write <= WR_GET_HEADER;
944 end if;
945
946 -- get header data
947 when WR_GET_HEADER =>
948 get_header <= '1';
949 if (get_header_started = '1') then
950 get_header <= '0';
951 state_write <= WR_GET_HEADER_WAIT;
952 end if;
953
954 when WR_GET_HEADER_WAIT =>
955 if (get_header_ready = '1') then
956 state_write <= WR_FIFO_HEADER;
957 end if;
958
959 -- Fill FIFO
960 when WR_FIFO_HEADER =>
961 state_init <= READ_FROM_HEADER_MODUL;
962 next_state <= WRITE_DATA;
963 state_write <= WR_FIFO_HEADER_01;
964
965 when WR_FIFO_HEADER_01 =>
966 header_cnt <= header_cnt + 1;
967 if (header_cnt < FTM_HEADER_LENGTH) then
968 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
969 par_data <= local_sd_data;
970 state_init <= WRITE_REG;
971 next_state <= WRITE_DATA;
972 state_write <= WR_FIFO_HEADER;
973 else
974 state_write <= WR_FIFO_DATA;
975 end if;
976
977 when WR_FIFO_DATA =>
978 state_init <= read_addr_state;
979 next_state <= WRITE_DATA;
980 state_write <= WR_FIFO_DATA_01;
981
982 when WR_FIFO_DATA_01 =>
983 data_cnt <= data_cnt + 1;
984 if (data_cnt < local_write_length) then
985 local_sd_addr <= local_sd_addr + 1;
986 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
987 par_data <= local_sd_data;
988 state_init <= WRITE_REG;
989 next_state <= WRITE_DATA;
990 state_write <= WR_FIFO_DATA;
991 else
992 state_write <= WR_05;
993 end if;
994
995 -- Send FIFO
996 when WR_05 =>
997 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
998 par_data <= (0 => write_length_bytes (16), others => '0');
999 state_init <= WRITE_REG;
1000 state_write <= WR_06;
1001 when WR_06 =>
1002 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1003 par_data <= write_length_bytes (15 downto 0);
1004 state_init <= WRITE_REG;
1005 state_write <= WR_07;
1006 when WR_07 =>
1007 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1008 par_data <= X"0020"; -- Send
1009 state_init <= WRITE_REG;
1010 state_write <= WR_08;
1011 when others =>
1012 state_init <= next_state_tmp;
1013 state_write <= WR_START;
1014 end case;
1015 -- End WRITE_DATA
1016
1017 when READ_REG =>
1018 case count is
1019 when "000" =>
1020 cs <= '0';
1021 rd <= '0';
1022 wr <= '1';
1023 data <= (others => 'Z'); -- !!!!!!!!!!
1024 count <= "001";
1025 addr <= par_addr;
1026 when "001" =>
1027 count <= "010";
1028 when "010" =>
1029 count <= "100";
1030 when "100" =>
1031 data_read <= data;
1032 count <= "110";
1033 when "110" =>
1034 count <= "111";
1035 when "111" =>
1036 cs <= '1';
1037 rd <= '1';
1038 count <= "000";
1039 state_init <= next_state;
1040 when others =>
1041 null;
1042 end case;
1043
1044 when WRITE_REG =>
1045 case count is
1046 when "000" =>
1047 cs <= '0';
1048 wr <= '0';
1049 rd <= '1';
1050 addr <= par_addr;
1051 data <= par_data;
1052 count <= "100";
1053 when "100" =>
1054 count <= "101";
1055 when "101" =>
1056 count <= "110";
1057 when "110" =>
1058 cs <= '1';
1059 wr <= '1';
1060 state_init <= next_state;
1061 count <= "000";
1062 when others =>
1063 null;
1064 end case;
1065
1066 when others =>
1067 null;
1068 end case;
1069 end if; -- int_flag = '0'
1070
1071 end if; -- rising_edge (clk)
1072
1073 end process w5300_init_proc;
1074
1075end Behavioral;
1076
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