source: firmware/FTM/ethernet/w5300_modul.vhd@ 10397

Last change on this file since 10397 was 10366, checked in by weitzel, 14 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 44.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.all;
23USE IEEE.STD_LOGIC_ARITH.all;
24USE IEEE.STD_LOGIC_UNSIGNED.all;
25
26--LIBRARY FACT_FTM_lib;
27--USE FACT_FTM_lib.ftm_array_types.all;
28--USE FACT_FTM_lib.ftm_constants.all;
29library ftm_definitions;
30USE ftm_definitions.ftm_array_types.all;
31USE ftm_definitions.ftm_constants.all;
32
33-- Uncomment the following library declaration if instantiating
34-- any Xilinx primitives in this code.
35library UNISIM;
36use UNISIM.VComponents.all;
37
38ENTITY w5300_modul IS
39 PORT(
40 clk : IN std_logic;
41 wiz_reset : OUT std_logic := '1';
42 addr : OUT std_logic_vector (9 DOWNTO 0);
43 data : INOUT std_logic_vector (15 DOWNTO 0);
44 cs : OUT std_logic := '1';
45 wr : OUT std_logic := '1';
46 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
47 rd : OUT std_logic := '1';
48 int : IN std_logic;
49 busy : OUT std_logic := '1';
50 new_config : OUT std_logic := '0';
51 config_started : IN std_logic;
52 config_started_ack : OUT std_logic := '0';
53 --
54 ping_ftu_start : OUT std_logic := '0';
55 ping_ftu_started : IN std_logic;
56 ping_ftu_ready : IN std_logic;
57 --
58 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
59 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
60 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
61 sd_write : OUT std_logic := '0';
62 sd_read : OUT std_logic := '0';
63 sd_started : IN std_logic;
64 sd_ready : IN std_logic;
65 sd_busy : IN std_logic;
66 --
67 dd_block_start : OUT std_logic := '0';
68 dd_block_start_ack : IN std_logic;
69 dd_block_ready : OUT std_logic := '1';
70 dd_send : IN std_logic;
71 dd_send_ack : OUT std_logic := '1';
72 dd_send_ready : OUT std_logic := '1';
73 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
74 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
75 dd_read : OUT std_logic := '0';
76 dd_started : IN std_logic;
77 dd_ready : IN std_logic;
78 dd_busy : IN std_logic;
79 dd_write_general : OUT std_logic := '0';
80 dd_write_general_started : IN std_logic;
81 dd_write_general_ready : IN std_logic;
82 --
83 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
84 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
85 fl_read : OUT std_logic := '0';
86 fl_started : IN std_logic;
87 fl_ready : IN std_logic;
88 fl_busy : IN std_logic;
89 --
90 ftu_error_send : IN std_logic;
91 ftu_error_send_ack : OUT std_logic := '1';
92 ftu_error_send_ready : OUT std_logic := '1';
93 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
94 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
95 --
96 get_header : OUT std_logic := '0';
97 get_header_started : IN std_logic;
98 get_header_ready : IN std_logic;
99 header_board_id : IN std_logic_vector (63 DOWNTO 0);
100 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
101 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
102 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0)
103
104 );
105
106END w5300_modul ;
107
108architecture Behavioral of w5300_modul is
109
110 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
111 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
112 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
113 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
114 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
115 WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01);
116 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
117 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
118 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_END);
119 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END);
120 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END);
121 type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END);
122 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST);
123 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
124 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
125 type state_send_ftu_error_type is (SFE_START, SFE_END);
126
127 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
128
129 signal par_addr : std_logic_vector (9 downto 0) := (others => '0');
130 signal par_data : std_logic_vector (15 downto 0) := (others => '0');
131 signal data_read : std_logic_vector (15 downto 0) := (others => '0');
132
133 signal state_init, next_state , next_state_tmp : state_init_type := RESET;
134 signal read_addr_state : state_init_type := RESET;
135 signal count : std_logic_vector (2 downto 0) := "000";
136 signal state_write : state_write_type := WR_START;
137 signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
138 signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
139 signal state_read_data : state_read_data_type := RD_1;
140 signal next_state_read_data : state_read_data_type := RD_CMD;
141 signal state_write_sd : state_write_sd_type := WRITE_SD_START;
142 signal state_read_sd : state_read_sd_type := READ_SD_START;
143 signal state_read_fl : state_read_fl_type := READ_FL_START;
144 signal state_ping : state_ping_type := PING_START;
145 signal state_read_dd : state_read_dd_type := READ_DD_START;
146 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START;
147 signal state_send_ftu_error : state_send_ftu_error_type := SFE_START;
148
149
150 signal interrupt_ignore : std_logic := '1';
151 signal int_flag : std_logic := '0';
152
153 signal zaehler : std_logic_vector (19 downto 0) := (others => '0');
154 signal data_cnt : integer := 0;
155 signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00";
156 signal socket_cnt : std_logic_vector (2 downto 0) := "000";
157
158 signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
159 signal write_length_bytes : std_logic_vector (16 downto 0);
160
161 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
162 signal chk_recv_cntr : integer range 0 to 10000 := 0;
163
164 signal next_packet_data_cnt : integer range 0 to 4095 := 0;
165 signal rx_packets_cnt : std_logic_vector (15 downto 0);
166 signal new_config_flag : std_logic := '0';
167
168 signal local_write_length : std_logic_vector (16 downto 0);
169 signal local_socket_nr : std_logic_vector (2 downto 0);
170
171 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0);
172 signal cmd_array : cmd_array_type;
173 signal internal_cmd : std_logic := '0';
174
175 signal autosend_flag : std_logic := '1';
176
177 -- -- --
178 signal led_int : std_logic_vector (7 downto 0) := X"00";
179 signal led_cnt : integer range 0 to 2**22 := 0;
180 -- -- --
181
182 signal local_sd_addr : std_logic_vector (11 downto 0);
183 signal local_sd_data : std_logic_vector (15 downto 0);
184
185
186begin
187
188 --synthesis translate_off
189 RST_TIME <= X"00120";
190 --synthesis translate_on
191
192
193 w5300_init_proc : process (clk, int)
194 begin
195
196 if rising_edge (clk) then
197
198 -- -- --
199 led <= led_int;
200 -- -- --
201
202 -- Interrupt low
203 if (int = '0') and (interrupt_ignore = '0') then
204 case state_interrupt_1 is
205 when IR1_01 =>
206 int_flag <= '1';
207 busy <= '1';
208 state_interrupt_1 <= IR1_02;
209 when IR1_02 =>
210 state_interrupt_1 <= IR1_03;
211 when IR1_03 =>
212 state_init <= INTERRUPT;
213 socket_cnt <= "000";
214 zaehler <= X"00000";
215 count <= "000";
216 int_flag <= '0';
217 interrupt_ignore <= '1';
218 state_interrupt_1 <= IR1_04;
219 when others =>
220 null;
221 end case;
222 end if; -- int = '0'
223
224 if int_flag = '0' then
225 case state_init is
226 -- Interrupt
227 when INTERRUPT =>
228 case state_interrupt_2 is
229 when IR2_01 =>
230 par_addr <= W5300_IR;
231 state_init <= READ_REG;
232 next_state <= INTERRUPT;
233 state_interrupt_2 <= IR2_02;
234 when IR2_02 =>
235 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
236 state_interrupt_2 <= IR2_03;
237 else
238 socket_cnt <= socket_cnt + 1;
239 if (socket_cnt = W5300_LAST_SOCKET) then
240 state_interrupt_2 <= IR2_06;
241 else
242 state_interrupt_2 <= IR2_02;
243 end if;
244 end if;
245 when IR2_03 =>
246 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
247 state_init <= READ_REG;
248 next_state <= INTERRUPT;
249 state_interrupt_2 <= IR2_04;
250 when IR2_04 =>
251 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
252 par_data <= data_read; -- clear Interrupts
253 state_init <= WRITE_REG;
254 next_state <= INTERRUPT;
255 state_interrupt_2 <= IR2_05;
256 when IR2_05 =>
257 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
258 par_data <= X"0010"; -- CLOSE
259 state_init <= WRITE_REG;
260 next_state <= INTERRUPT;
261 socket_cnt <= socket_cnt + 1;
262 if (socket_cnt = W5300_LAST_SOCKET) then
263 state_interrupt_2 <= IR2_06;
264 else
265 state_interrupt_2 <= IR2_01;
266 end if;
267
268 when IR2_06 =>
269 state_interrupt_1 <= IR1_01;
270 state_interrupt_2 <= IR2_01;
271 socket_cnt <= "000";
272 state_init <= RESET;
273 end case;
274
275 -- reset W5300
276 when RESET =>
277 busy <= '1';
278 zaehler <= zaehler + 1;
279 wiz_reset <= '0';
280 if (zaehler >= X"00064") then -- wait 2µs
281 wiz_reset <= '1';
282 end if;
283 if (zaehler = RST_TIME) then -- wait 10ms
284 zaehler <= X"00000";
285 socket_cnt <= "000";
286 count <= "000";
287 interrupt_ignore <= '0';
288 rd <= '1';
289 wr <= '1';
290 cs <= '1';
291 -- reset states
292 state_write <= WR_START;
293 state_init <= INIT;
294 state_read_data <= RD_1;
295 next_state_read_data <= RD_CMD;
296 state_write_sd <= WRITE_SD_START;
297 state_read_sd <= READ_SD_START;
298 state_read_fl <= READ_FL_START;
299 state_ping <= PING_START;
300 state_read_dd <= READ_DD_START;
301 state_read_dd_block <= READ_DD_BLOCK_START;
302 state_send_ftu_error <= SFE_START;
303 -- reset output signals
304 new_config <= '0';
305 config_started_ack <= '1';
306 ping_ftu_start <= '0';
307 sd_write <= '0';
308 sd_read <= '0';
309 dd_block_start <= '0';
310 dd_block_ready <= '1';
311 dd_send_ack <= '1';
312 dd_send_ready <= '1';
313 dd_read <= '0';
314 dd_write_general <= '0';
315 fl_read <= '0';
316 ftu_error_send_ack <= '1';
317 ftu_error_send_ready <= '1';
318 -- set internal signals
319 new_config_flag <= '0';
320 chk_recv_cntr <= 0;
321 next_packet_data_cnt <= 0;
322 internal_cmd <= '0';
323 -- -- --
324 led_int <= X"00";
325 -- -- --
326 end if;
327
328 -- Init
329 when INIT =>
330 par_addr <= W5300_MR;
331 par_data <= X"0000";
332 state_init <= WRITE_REG;
333 next_state <= IM;
334
335 -- Interrupt Mask
336 when IM =>
337 par_addr <= W5300_IMR;
338 par_data <= X"00FF"; -- S0-S7 Interrupts
339 state_init <= WRITE_REG;
340 next_state <= MT;
341
342 -- Memory Type
343 when MT =>
344 par_addr <= W5300_MTYPER;
345 par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer
346 state_init <= WRITE_REG;
347 next_state <= STX;
348
349 -- Socket TX Memory Size
350 when STX =>
351 par_data <= X"4000"; -- 64K TX for socket 0, others 0
352
353 par_addr <= W5300_TMS01R;
354 state_init <= WRITE_REG;
355 next_state <= STX1;
356 when STX1 =>
357 par_data <= X"0000";
358 par_addr <= W5300_TMS23R;
359 state_init <= WRITE_REG;
360 next_state <= STX2;
361 when STX2 =>
362 par_addr <= W5300_TMS45R;
363 state_init <= WRITE_REG;
364 next_state <= STX3;
365 when STX3 =>
366 par_addr <= W5300_TMS67R;
367 state_init <= WRITE_REG;
368 next_state <= SRX;
369
370 -- Socket RX Memory Size
371 when SRX =>
372 par_data <= X"4000"; -- 64K RX for socket 0, others 0
373
374 par_addr <= W5300_RMS01R;
375 state_init <= WRITE_REG;
376 next_state <= SRX1;
377 when SRX1 =>
378 par_data <= X"0000";
379 par_addr <= W5300_RMS23R;
380 state_init <= WRITE_REG;
381 next_state <= SRX2;
382 when SRX2 =>
383 par_addr <= W5300_RMS45R;
384 state_init <= WRITE_REG;
385 next_state <= SRX3;
386 when SRX3 =>
387 par_addr <= W5300_RMS67R;
388 state_init <= WRITE_REG;
389 next_state <= MAC;
390
391 -- MAC
392 when MAC =>
393 par_addr <= W5300_SHAR;
394 par_data <= MAC_ADDRESS (0);
395 state_init <= WRITE_REG;
396 next_state <= MAC1;
397 when MAC1 =>
398 par_addr <= W5300_SHAR + 2;
399 par_data <= MAC_ADDRESS (1);
400 state_init <= WRITE_REG;
401 next_state <= MAC2;
402 when MAC2 =>
403 par_addr <= W5300_SHAR + 4;
404 par_data <= MAC_ADDRESS (2);
405 state_init <= WRITE_REG;
406 next_state <= GW;
407
408 -- Gateway
409 when GW =>
410 par_addr <= W5300_GAR;
411 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8);
412 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8);
413 state_init <= WRITE_REG;
414 next_state <= GW1;
415 when GW1 =>
416 par_addr <= W5300_GAR + 2;
417 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8);
418 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8);
419 state_init <= WRITE_REG;
420 next_state <= SNM;
421
422 -- Subnet Mask
423 when SNM =>
424 par_addr <= W5300_SUBR;
425 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8);
426 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8);
427 state_init <= WRITE_REG;
428 next_state <= SNM1;
429 when SNM1 =>
430 par_addr <= W5300_SUBR + 2;
431 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8);
432 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8);
433 state_init <= WRITE_REG;
434 next_state <= IP;
435 -- Own IP-Address
436 when IP =>
437 par_addr <= W5300_SIPR;
438 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8);
439 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8);
440 state_init <= WRITE_REG;
441 next_state <= IP1;
442 when IP1 =>
443 par_addr <= W5300_SIPR + 2;
444 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8);
445 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8);
446 state_init <= WRITE_REG;
447 next_state <= SI;
448 -- Socket Init
449 when SI =>
450 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
451 par_data <= X"0101"; -- ALIGN, TCP
452 state_init <= WRITE_REG;
453 next_state <= SI1;
454 -- Sx Interrupt Mask
455 when SI1 =>
456 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
457 par_data <= X"000A"; -- TIMEOUT, DISCON
458 state_init <= WRITE_REG;
459 next_state <= SI2;
460 when SI2 =>
461 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
462 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
463 state_init <= WRITE_REG;
464 next_state <= SI3;
465 when SI3 =>
466 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
467 par_data <= X"0001"; -- OPEN
468 state_init <= WRITE_REG;
469 next_state <= SI4;
470 when SI4 =>
471 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
472 state_init <= READ_REG;
473 next_state <= SI5;
474 when SI5 =>
475 if (data_read (7 downto 0) = X"13") then -- is open?
476 state_init <= SI6;
477 else
478 state_init <= SI4;
479 end if;
480 when SI6 =>
481 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
482 par_data <= X"0002"; -- LISTEN
483 state_init <= WRITE_REG;
484 socket_cnt <= socket_cnt + 1;
485 if (socket_cnt = W5300_LAST_SOCKET) then
486 socket_cnt <= "000";
487 next_state <= ESTABLISH; -- All Sockets open
488 else
489 next_state <= SI; -- Next Socket
490 end if;
491 -- End Socket Init
492
493 when ESTABLISH =>
494 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
495 state_init <= READ_REG;
496 next_state <= EST1;
497 when EST1 =>
498 case data_read (7 downto 0) is
499 when X"17" => -- established
500 if (socket_cnt = W5300_LAST_SOCKET) then
501 socket_cnt <= "000";
502 busy <= '0';
503 state_init <= MAIN;
504 -- -- --
505 config_started_ack <= '0';
506 dd_block_ready <= '0';
507 dd_send_ack <= '0';
508 dd_send_ready <= '0';
509 ftu_error_send_ack <= '0';
510 ftu_error_send_ready <= '0';
511 led_int <= X"00";
512 -- -- --
513 else
514 socket_cnt <= socket_cnt + 1;
515 state_init <= ESTABLISH;
516 end if;
517 when others =>
518 state_init <= ESTABLISH;
519 -- -- --
520 -- Just for fun...
521 if (led_cnt = 1100000) then
522 if (led_int = X"00") then
523 led_int <= X"18";
524 else
525 led_int (7 downto 4) <= led_int (6 downto 4) & '0';
526 led_int (3 downto 0) <= '0' & led_int (3 downto 1);
527 end if;
528 led_cnt <= 0;
529 else
530 led_cnt <= led_cnt + 1;
531 end if;
532 -- -- --
533 end case;
534
535 when CONFIG =>
536 new_config <= '1';
537 config_started_ack <= '0';
538 if (config_started = '1') then
539 new_config <= '0';
540 config_started_ack <= '1';
541 state_init <= MAIN;
542 end if;
543
544 -- main "loop"
545 when MAIN =>
546 chk_recv_cntr <= chk_recv_cntr + 1;
547 if (chk_recv_cntr = 1000) then
548 chk_recv_cntr <= 0;
549 state_read_data <= RD_1;
550 state_init <= READ_DATA;
551 busy <= '1';
552 elsif (dd_send = '1') then
553 internal_cmd <= '1';
554 dd_send_ack <= '1';
555 dd_send_ready <= '0';
556 if (autosend_flag = '0') then
557 state_read_dd_block <= READ_DD_BLOCK_END;
558 end if;
559 state_read_data <= RD_READ_DD_BLOCK;
560 state_init <= READ_DATA;
561 elsif (ftu_error_send = '1') then
562 ftu_error_send_ack <= '1';
563 ftu_error_send_ready <= '0';
564 if (autosend_flag = '0') then
565 state_send_ftu_error <= SFE_END;
566 end if;
567 state_init <= SEND_FTU_ERROR;
568 end if;
569
570
571 -- send FTU error message
572 when SEND_FTU_ERROR =>
573 case state_send_ftu_error is
574 when SFE_START =>
575 next_state <= SEND_FTU_ERROR;
576 read_addr_state <= READ_FTU_ERROR;
577 local_sd_addr <= X"000";
578 local_write_length <= "00000" & FTU_ERROR_LENGTH;
579 state_send_ftu_error <= SFE_END;
580 state_init <= WRITE_DATA;
581 when SFE_END =>
582 if (ftu_error_send = '0') then
583 ftu_error_send_ack <= '0';
584 ftu_error_send_ready <= '1';
585 state_send_ftu_error <= SFE_START;
586 state_init <= MAIN;
587 end if;
588 end case;
589
590
591 -- read data from socket 0
592 when READ_DATA =>
593 case state_read_data is
594 when RD_1 =>
595 par_addr <= W5300_S0_RX_RSR;
596 state_init <= READ_REG;
597 next_state <= READ_DATA;
598 state_read_data <= RD_2;
599 when RD_2 =>
600 socket_rx_received (31 downto 16) <= data_read;
601 par_addr <= W5300_S0_RX_RSR + X"2";
602 state_init <= READ_REG;
603 next_state <= READ_DATA;
604 state_read_data <= RD_3;
605 when RD_3 =>
606 socket_rx_received (15 downto 0) <= data_read;
607 state_read_data <= RD_4;
608 when RD_4 =>
609 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
610 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
611 state_read_data <= RD_5;
612 else
613 busy <= '0';
614 state_init <= MAIN;
615 end if;
616 when RD_5 =>
617 if (rx_packets_cnt > 0) then
618 rx_packets_cnt <= rx_packets_cnt - '1';
619 par_addr <= W5300_S0_RX_FIFOR;
620 state_init <= READ_REG;
621 next_state <= READ_DATA;
622 state_read_data <= next_state_read_data;
623 else
624 state_read_data <= RD_END;
625 end if;
626
627 when RD_END =>
628 if (internal_cmd = '0') then
629 par_addr <= W5300_S0_CR;
630 par_data <= X"0040"; -- RECV
631 state_init <= WRITE_REG;
632 else
633 internal_cmd <= '0';
634 end if;
635 if (new_config_flag = '1') then
636 new_config_flag <= '0';
637 next_state <= CONFIG;
638 else
639 next_state <= MAIN;
640 end if;
641
642
643 -------------------------
644 -- command handling
645 -------------------------
646
647 -- read command (5 words)
648 when RD_CMD =>
649 cmd_array (next_packet_data_cnt) <= data_read;
650 next_packet_data_cnt <= next_packet_data_cnt + 1;
651 -- look for command start
652 if (next_packet_data_cnt = 0) then
653 if (data_read /= CMD_START_DELIMITER) then
654 next_packet_data_cnt <= 0;
655 end if;
656 end if;
657 -- last command-word
658 if (next_packet_data_cnt = 4) then
659 next_packet_data_cnt <= 0;
660 state_read_data <= RD_CMD_PARSE;
661 else
662 state_read_data <= RD_5;
663 end if;
664
665 -- process commands and parameters
666 when RD_CMD_PARSE =>
667 case cmd_array (1) is
668
669 when CMD_TLED =>
670 led_int <= NOT led_int;
671 state_read_data <= RD_5;
672
673 when CMD_WRITE =>
674 case cmd_array (2) is
675 -- write to address in static data block
676 when PAR_WRITE_SD_ADDR =>
677 new_config_flag <= '1';
678 next_state_read_data <= RD_WRITE_SD_ADDR;
679 state_read_data <= RD_5;
680 -- write static data block
681 when PAR_WRITE_SD =>
682 new_config_flag <= '1';
683 next_state_read_data <= RD_WRITE_SD_BLOCK;
684 state_read_data <= RD_5;
685 when others =>
686 state_read_data <= RD_5;
687 end case; -- cmd_array (2)
688
689 when CMD_READ =>
690 case cmd_array (2) is
691 -- read from address in static data block
692 when PAR_READ_SD_ADDR =>
693 next_state_read_data <= RD_READ_SD_ADDR;
694 state_read_data <= RD_5;
695 -- read static data block
696 when PAR_READ_SD =>
697 state_read_data <= RD_READ_SD_BLOCK;
698 -- read dynamic data block
699 when PAR_READ_DD =>
700 state_read_data <= RD_READ_DD_BLOCK;
701 when others =>
702 state_read_data <= RD_5;
703 end case; -- cmd_array (2)
704
705 when CMD_PING =>
706 state_ping <= PING_START;
707 state_read_data <= RD_PING;
708
709 when CMD_AUTOSEND =>
710 state_read_data <= RD_5;
711 case cmd_array (2) is
712 when PAR_AUTOSEND_EA =>
713 autosend_flag <= '1';
714 when PAR_AUTOSEND_DA =>
715 autosend_flag <= '0';
716 when others =>
717 null;
718 end case;
719
720 when others =>
721 state_read_data <= RD_5;
722
723 end case; -- cmd_array (1)
724
725
726 -- ping all FTUs and write FTU-list to ethernet
727 when RD_PING =>
728 case state_ping is
729 when PING_START =>
730 ping_ftu_start <= '1';
731 if (ping_ftu_started = '1') then
732 ping_ftu_start <= '0';
733 state_ping <= PING_WAIT;
734 end if;
735 when PING_WAIT =>
736 if (ping_ftu_ready = '1') then
737 state_ping <= PING_WRITE_LIST;
738 end if;
739 when PING_WRITE_LIST =>
740 state_read_data <= RD_5;
741 read_addr_state <= READ_FROM_FL_ADDR;
742 local_sd_addr <= X"000"; --start at address 0x000
743 local_write_length <= "00000" & FL_BLOCK_SIZE;
744 next_state_read_data <= RD_CMD;
745 next_state <= READ_DATA;
746 state_init <= WRITE_DATA;
747 end case;
748
749 -- read dynamic data block and write it to ethernet
750 when RD_READ_DD_BLOCK =>
751 case state_read_dd_block is
752 when READ_DD_BLOCK_START =>
753 dd_block_start <= '1';
754 dd_block_ready <= '0';
755 if (dd_block_start_ack = '1') then
756 dd_block_start <= '0';
757 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;
758 end if;
759 -- write on-time counter and tempertures to dd-block
760 when READ_DD_BLOCK_WRITE_GENERAL =>
761 dd_write_general <= '1';
762 if (dd_write_general_started = '1') then
763 dd_write_general <= '0';
764 state_read_dd_block <= READ_DD_BLOCK_WRITE;
765 end if;
766 -- write dd-block to ethernet when on-time counter and temperatures are ready
767 when READ_DD_BLOCK_WRITE =>
768 if (dd_write_general_ready = '1') then
769 read_addr_state <= READ_FROM_DD_ADDR;
770 local_sd_addr <= X"000"; -- start at address 0x000
771 local_write_length <= "00000" & DD_BLOCK_SIZE;
772 state_read_dd_block <= READ_DD_BLOCK_END;
773 next_state <= READ_DATA;
774 state_init <= WRITE_DATA;
775 end if;
776 when READ_DD_BLOCK_END =>
777 dd_block_ready <= '1';
778 next_state_read_data <= RD_CMD;
779 --
780 if (internal_cmd = '1') then
781 state_read_dd_block <= READ_DD_BLOCK_INTERN;
782 else
783 state_read_dd_block <= READ_DD_BLOCK_START;
784 state_read_data <= RD_5;
785 end if;
786 when READ_DD_BLOCK_INTERN =>
787 if (dd_send = '0') then
788 dd_send_ready <= '1';
789 dd_send_ack <= '0';
790 state_read_dd_block <= READ_DD_BLOCK_START;
791 state_read_data <= RD_5;
792 end if;
793
794 end case;
795
796 -- read static data block and write it to ethernet
797 when RD_READ_SD_BLOCK =>
798 state_read_data <= RD_5;
799 read_addr_state <= READ_FROM_SD_ADDR;
800 local_sd_addr <= X"000"; -- start at address 0x000
801 local_write_length <= "00000" & SD_BLOCK_SIZE;
802 next_state_read_data <= RD_CMD;
803 next_state <= READ_DATA;
804 state_init <= WRITE_DATA;
805
806 -- read from address in static data ram and write data to ethernet
807 when RD_READ_SD_ADDR =>
808 state_read_data <= RD_5;
809 read_addr_state <= READ_FROM_SD_ADDR;
810 local_sd_addr <= data_read (11 downto 0);
811 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
812 next_state_read_data <= RD_CMD;
813 next_state <= READ_DATA;
814 state_init <= WRITE_DATA;
815
816 -- read static data block from ethernet and write it to static data ram
817 when RD_WRITE_SD_BLOCK =>
818 state_read_data <= RD_5;
819 next_packet_data_cnt <= next_packet_data_cnt + 1;
820 local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12);
821 local_sd_data <= data_read;
822 next_state <= READ_DATA;
823 state_init <= WRITE_TO_SD_ADDR;
824 -- last word
825 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
826 next_packet_data_cnt <= 0;
827 next_state_read_data <= RD_CMD;
828 end if;
829
830 -- write to address in static data ram
831 when RD_WRITE_SD_ADDR =>
832 state_read_data <= RD_5;
833 next_packet_data_cnt <= next_packet_data_cnt + 1;
834 if (next_packet_data_cnt = 0) then
835 local_sd_addr <= data_read (11 downto 0);
836 else
837 local_sd_data <= data_read;
838 next_packet_data_cnt <= 0;
839 next_state_read_data <= RD_CMD;
840 next_state <= READ_DATA;
841 state_init <= WRITE_TO_SD_ADDR;
842 end if;
843
844 end case; -- state_read_data
845
846
847 -- read FTU errors
848 when READ_FTU_ERROR =>
849 state_init <= next_state;
850 if (data_cnt = 0) then
851 local_sd_data <= ftu_error_calls;
852 else
853 local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8));
854 end if;
855
856
857 -- read from header modul
858 when READ_FROM_HEADER_MODUL =>
859 state_init <= next_state;
860 case header_cnt is
861 when X"00" =>
862 local_sd_data <= header_board_id (63 DOWNTO 48);
863 when X"01" =>
864 local_sd_data <= header_board_id (47 DOWNTO 32);
865 when X"02" =>
866 local_sd_data <= header_board_id (31 DOWNTO 16);
867 when X"03" =>
868 local_sd_data <= header_board_id (15 DOWNTO 0);
869 when X"04" =>
870 local_sd_data <= header_firmware_id;
871 when X"05" =>
872 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
873 when X"06" =>
874 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
875 when X"07" =>
876 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
877 when X"08" =>
878 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
879 when X"09" =>
880 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
881 when X"0A" =>
882 local_sd_data <= X"FFFF"; -- spare
883 when others =>
884 null;
885 end case;
886
887 -- read from ftu list ram
888 when READ_FROM_FL_ADDR =>
889 case state_read_fl is
890 when READ_FL_START =>
891 if (fl_busy = '0') then
892 fl_addr <= local_sd_addr;
893 fl_read <= '1';
894 state_read_fl <= READ_FL_WAIT;
895 end if;
896 when READ_FL_WAIT =>
897 if (fl_started = '1') then
898 state_read_fl <= READ_FL_END;
899 end if;
900 when READ_FL_END =>
901 if (fl_ready = '1') then
902 local_sd_data <= fl_data_in;
903 fl_read <= '0';
904 state_read_fl <= READ_FL_START;
905 state_init <= next_state;
906 end if;
907 end case;
908
909 -- read from dynamic data block
910 when READ_FROM_DD_ADDR =>
911 case state_read_dd is
912 when READ_DD_START =>
913 if (dd_busy = '0') then
914 dd_addr <= local_sd_addr;
915 dd_read <= '1';
916 state_read_dd <= READ_DD_WAIT;
917 end if;
918 when READ_DD_WAIT =>
919 if (dd_started = '1') then
920 state_read_dd <= READ_DD_END;
921 end if;
922 when READ_DD_END =>
923 if (dd_ready = '1') then
924 local_sd_data <= dd_data_in;
925 dd_read <= '0';
926 state_read_dd <= READ_DD_START;
927 state_init <= next_state;
928 end if;
929 end case;
930
931 -- read from static data block
932 when READ_FROM_SD_ADDR =>
933 case state_read_sd is
934 when READ_SD_START =>
935 if (sd_busy = '0') then
936 sd_addr <= local_sd_addr;
937 sd_read <= '1';
938 state_read_sd <= READ_SD_WAIT;
939 end if;
940 when READ_SD_WAIT =>
941 if (sd_started = '1') then
942 state_read_sd <= READ_SD_END;
943 end if;
944 when READ_SD_END =>
945 if (sd_ready = '1') then
946 local_sd_data <= sd_data_in;
947 sd_read <= '0';
948 state_read_sd <= READ_SD_START;
949 state_init <= next_state;
950 end if;
951 end case;
952
953 -- write to static data block
954 when WRITE_TO_SD_ADDR =>
955 case state_write_sd is
956 when WRITE_SD_START =>
957 if (sd_busy = '0') then
958 sd_addr <= local_sd_addr;
959 sd_data_out <= local_sd_data;
960 sd_write <= '1';
961 state_write_sd <= WRITE_SD_WAIT;
962 end if;
963 when WRITE_SD_WAIT =>
964 if (sd_started = '1') then
965 sd_write <= '0';
966 state_write_sd <= WRITE_SD_END;
967 end if;
968 when WRITE_SD_END =>
969 if (sd_ready = '1') then
970 state_write_sd <= WRITE_SD_START;
971 state_init <= next_state;
972 end if;
973 end case;
974
975 -- write to ethernet interface
976 when WRITE_DATA =>
977 case state_write is
978 when WR_START =>
979 state_write <= WR_LENGTH;
980 when WR_LENGTH =>
981 local_socket_nr <= "000";
982 next_state_tmp <= next_state;
983 write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2)
984 data_cnt <= 0;
985 header_cnt <= X"00";
986 state_write <= WR_01;
987 -- Check FIFO Size
988 when WR_01 =>
989 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
990 state_init <= READ_REG;
991 next_state <= WRITE_DATA;
992 state_write <= WR_02;
993 when WR_02 =>
994 socket_tx_free (31 downto 16) <= data_read;
995 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
996 state_init <= READ_REG;
997 next_state <= WRITE_DATA;
998 state_write <= WR_03;
999 when WR_03 =>
1000 socket_tx_free (15 downto 0) <= data_read;
1001 state_write <= WR_04;
1002 when WR_04 =>
1003 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1004 state_write <= WR_01;
1005 else
1006 state_write <= WR_GET_HEADER;
1007 end if;
1008
1009 -- get header data
1010 when WR_GET_HEADER =>
1011 get_header <= '1';
1012 if (get_header_started = '1') then
1013 get_header <= '0';
1014 state_write <= WR_GET_HEADER_WAIT;
1015 end if;
1016
1017 when WR_GET_HEADER_WAIT =>
1018 if (get_header_ready = '1') then
1019 state_write <= WR_FIFO_HEADER;
1020 end if;
1021
1022 -- Fill FIFO
1023 when WR_FIFO_HEADER =>
1024 state_init <= READ_FROM_HEADER_MODUL;
1025 next_state <= WRITE_DATA;
1026 state_write <= WR_FIFO_HEADER_01;
1027
1028 when WR_FIFO_HEADER_01 =>
1029 header_cnt <= header_cnt + 1;
1030 if (header_cnt < FTM_HEADER_LENGTH) then
1031 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1032 par_data <= local_sd_data;
1033 state_init <= WRITE_REG;
1034 next_state <= WRITE_DATA;
1035 state_write <= WR_FIFO_HEADER;
1036 else
1037 state_write <= WR_FIFO_DATA;
1038 end if;
1039
1040 when WR_FIFO_DATA =>
1041 state_init <= read_addr_state;
1042 next_state <= WRITE_DATA;
1043 state_write <= WR_FIFO_DATA_01;
1044
1045 when WR_FIFO_DATA_01 =>
1046 data_cnt <= data_cnt + 1;
1047 if (data_cnt < local_write_length) then
1048 local_sd_addr <= local_sd_addr + 1;
1049 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1050 par_data <= local_sd_data;
1051 state_init <= WRITE_REG;
1052 next_state <= WRITE_DATA;
1053 state_write <= WR_FIFO_DATA;
1054 else
1055 state_write <= WR_05;
1056 end if;
1057
1058 -- Send FIFO
1059 when WR_05 =>
1060 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
1061 par_data <= (0 => write_length_bytes (16), others => '0');
1062 state_init <= WRITE_REG;
1063 state_write <= WR_06;
1064 when WR_06 =>
1065 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1066 par_data <= write_length_bytes (15 downto 0);
1067 state_init <= WRITE_REG;
1068 state_write <= WR_07;
1069 when WR_07 =>
1070 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1071 par_data <= X"0020"; -- Send
1072 state_init <= WRITE_REG;
1073 state_write <= WR_08;
1074 when others =>
1075 state_init <= next_state_tmp;
1076 state_write <= WR_START;
1077 end case;
1078 -- End WRITE_DATA
1079
1080 when READ_REG =>
1081 case count is
1082 when "000" =>
1083 cs <= '0';
1084 rd <= '0';
1085 wr <= '1';
1086 data <= (others => 'Z'); -- !!!!!!!!!!
1087 count <= "001";
1088 addr <= par_addr;
1089 when "001" =>
1090 count <= "010";
1091 when "010" =>
1092 count <= "100";
1093 when "100" =>
1094 data_read <= data;
1095 count <= "110";
1096 when "110" =>
1097 count <= "111";
1098 when "111" =>
1099 cs <= '1';
1100 rd <= '1';
1101 count <= "000";
1102 state_init <= next_state;
1103 when others =>
1104 null;
1105 end case;
1106
1107 when WRITE_REG =>
1108 case count is
1109 when "000" =>
1110 cs <= '0';
1111 wr <= '0';
1112 rd <= '1';
1113 addr <= par_addr;
1114 data <= par_data;
1115 count <= "100";
1116 when "100" =>
1117 count <= "101";
1118 when "101" =>
1119 count <= "110";
1120 when "110" =>
1121 cs <= '1';
1122 wr <= '1';
1123 state_init <= next_state;
1124 count <= "000";
1125 when others =>
1126 null;
1127 end case;
1128
1129 when others =>
1130 null;
1131 end case;
1132 end if; -- int_flag = '0'
1133
1134 end if; -- rising_edge (clk)
1135
1136 end process w5300_init_proc;
1137
1138end Behavioral;
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