source: firmware/FTM/ethernet/w5300_modul.vhd@ 10506

Last change on this file since 10506 was 10441, checked in by weitzel, 14 years ago
new FTM firmware featuring e.g. start/stop run commands and new header
File size: 49.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20-- hds interface_start
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.all;
23USE IEEE.STD_LOGIC_ARITH.all;
24USE IEEE.STD_LOGIC_UNSIGNED.all;
25
26library ftm_definitions;
27USE ftm_definitions.ftm_array_types.all;
28USE ftm_definitions.ftm_constants.all;
29
30-- Uncomment the following library declaration if instantiating
31-- any Xilinx primitives in this code.
32library UNISIM;
33use UNISIM.VComponents.all;
34
35ENTITY w5300_modul IS
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 busy : OUT std_logic := '1';
47 new_config : OUT std_logic := '0';
48 config_started : IN std_logic;
49 config_started_ack : OUT std_logic := '0';
50 --
51 ping_ftu_start : OUT std_logic := '0';
52 ping_ftu_started : IN std_logic;
53 ping_ftu_ready : IN std_logic;
54 --
55 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
56 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
57 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
58 sd_write : OUT std_logic := '0';
59 sd_read : OUT std_logic := '0';
60 sd_started : IN std_logic;
61 sd_ready : IN std_logic;
62 sd_busy : IN std_logic;
63 --
64 dd_block_start : OUT std_logic := '0';
65 dd_block_start_ack : IN std_logic;
66 dd_block_ready : OUT std_logic := '1';
67 dd_send : IN std_logic;
68 dd_send_ack : OUT std_logic := '1';
69 dd_send_ready : OUT std_logic := '1';
70 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
71 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
72 dd_read : OUT std_logic := '0';
73 dd_started : IN std_logic;
74 dd_ready : IN std_logic;
75 dd_busy : IN std_logic;
76 dd_write_general : OUT std_logic := '0';
77 dd_write_general_started : IN std_logic;
78 dd_write_general_ready : IN std_logic;
79 --
80 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
81 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
82 fl_read : OUT std_logic := '0';
83 fl_started : IN std_logic;
84 fl_ready : IN std_logic;
85 fl_busy : IN std_logic;
86 --
87 ftu_error_send : IN std_logic;
88 ftu_error_send_ack : OUT std_logic := '1';
89 ftu_error_send_ready : OUT std_logic := '1';
90 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
91 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
92 --
93 get_header : OUT std_logic := '0';
94 get_header_started : IN std_logic;
95 get_header_ready : IN std_logic;
96 header_board_id : IN std_logic_vector (63 DOWNTO 0);
97 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
98 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
99 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
100 header_current_state : IN std_logic_vector (15 DOWNTO 0);
101 --
102 start_run : OUT std_logic := '0';
103 start_run_ack : IN std_logic;
104 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
105 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
106 stop_run : OUT std_logic := '0';
107 stop_run_ack : IN std_logic;
108 crate_reset : OUT std_logic := '0';
109 crate_reset_ack : IN std_logic;
110 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
111 );
112
113END w5300_modul ;
114
115architecture Behavioral of w5300_modul is
116
117 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
118 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
119 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
120 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
121 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
122 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);
123 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
124 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
125 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END);
126 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END);
127 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END);
128 type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END);
129 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST);
130 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
131 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
132 type state_send_ftu_error_type is (SFE_START, SFE_END);
133
134 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
135
136 signal par_addr : std_logic_vector (9 downto 0) := (others => '0');
137 signal par_data : std_logic_vector (15 downto 0) := (others => '0');
138 signal data_read : std_logic_vector (15 downto 0) := (others => '0');
139
140 signal state_init, next_state , next_state_tmp : state_init_type := RESET;
141 signal read_addr_state : state_init_type := RESET;
142 signal count : std_logic_vector (2 downto 0) := "000";
143 signal state_write : state_write_type := WR_START;
144 signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
145 signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
146 signal state_read_data : state_read_data_type := RD_1;
147 signal next_state_read_data : state_read_data_type := RD_CMD;
148 signal state_write_sd : state_write_sd_type := WRITE_SD_START;
149 signal state_read_sd : state_read_sd_type := READ_SD_START;
150 signal state_read_fl : state_read_fl_type := READ_FL_START;
151 signal state_ping : state_ping_type := PING_START;
152 signal state_read_dd : state_read_dd_type := READ_DD_START;
153 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START;
154 signal state_send_ftu_error : state_send_ftu_error_type := SFE_START;
155
156
157 signal interrupt_ignore : std_logic := '1';
158 signal int_flag : std_logic := '0';
159
160 signal zaehler : std_logic_vector (19 downto 0) := (others => '0');
161 signal data_cnt : integer := 0;
162 signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00";
163 signal socket_cnt : std_logic_vector (2 downto 0) := "000";
164
165 signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
166 signal write_length_bytes : std_logic_vector (16 downto 0);
167
168 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
169 signal chk_recv_cntr : integer range 0 to 10000 := 0;
170
171 signal next_packet_data_cnt : integer range 0 to 4095 := 0;
172 signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000";
173 signal new_config_flag : std_logic := '0';
174
175 signal local_write_length : std_logic_vector (16 downto 0);
176 signal local_socket_nr : std_logic_vector (2 downto 0);
177
178 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0);
179 signal cmd_array : cmd_array_type;
180 signal internal_cmd : std_logic := '0';
181
182 signal autosend_flag : std_logic := '1';
183
184 -- -- --
185 signal led_int : std_logic_vector (7 downto 0) := X"00";
186 signal led_cnt : integer range 0 to 2**22 := 0;
187 -- -- --
188
189 signal local_sd_addr : std_logic_vector (11 downto 0);
190 signal local_sd_data : std_logic_vector (15 downto 0);
191
192 signal data_package_type : std_logic_vector (15 downto 0) := X"0000";
193 signal data_package_length : std_logic_vector (15 downto 0) := X"0000";
194
195
196begin
197
198 --synthesis translate_off
199 RST_TIME <= X"00120";
200 --synthesis translate_on
201
202
203 w5300_init_proc : process (clk, int)
204 begin
205
206 if rising_edge (clk) then
207
208 -- -- --
209 led <= led_int;
210 -- -- --
211
212 -- Interrupt low
213 if (int = '0') and (interrupt_ignore = '0') then
214 case state_interrupt_1 is
215 when IR1_01 =>
216 int_flag <= '1';
217 busy <= '1';
218 state_interrupt_1 <= IR1_02;
219 when IR1_02 =>
220 state_interrupt_1 <= IR1_03;
221 when IR1_03 =>
222 state_init <= INTERRUPT;
223 socket_cnt <= "000";
224 zaehler <= X"00000";
225 count <= "000";
226 int_flag <= '0';
227 interrupt_ignore <= '1';
228 state_interrupt_1 <= IR1_04;
229 when others =>
230 null;
231 end case;
232 end if; -- int = '0'
233
234 if int_flag = '0' then
235 case state_init is
236 -- Interrupt
237 when INTERRUPT =>
238 case state_interrupt_2 is
239 when IR2_01 =>
240 par_addr <= W5300_IR;
241 state_init <= READ_REG;
242 next_state <= INTERRUPT;
243 state_interrupt_2 <= IR2_02;
244 when IR2_02 =>
245 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
246 state_interrupt_2 <= IR2_03;
247 else
248 socket_cnt <= socket_cnt + 1;
249 if (socket_cnt = W5300_LAST_SOCKET) then
250 state_interrupt_2 <= IR2_06;
251 else
252 state_interrupt_2 <= IR2_02;
253 end if;
254 end if;
255 when IR2_03 =>
256 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
257 state_init <= READ_REG;
258 next_state <= INTERRUPT;
259 state_interrupt_2 <= IR2_04;
260 when IR2_04 =>
261 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
262 par_data <= data_read; -- clear Interrupts
263 state_init <= WRITE_REG;
264 next_state <= INTERRUPT;
265 state_interrupt_2 <= IR2_05;
266 when IR2_05 =>
267 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
268 par_data <= X"0010"; -- CLOSE
269 state_init <= WRITE_REG;
270 next_state <= INTERRUPT;
271 socket_cnt <= socket_cnt + 1;
272 if (socket_cnt = W5300_LAST_SOCKET) then
273 state_interrupt_2 <= IR2_06;
274 else
275 state_interrupt_2 <= IR2_01;
276 end if;
277
278 when IR2_06 =>
279 state_interrupt_1 <= IR1_01;
280 state_interrupt_2 <= IR2_01;
281 socket_cnt <= "000";
282 state_init <= RESET;
283 end case;
284
285 -- reset W5300
286 when RESET =>
287 busy <= '1';
288 zaehler <= zaehler + 1;
289 wiz_reset <= '0';
290 if (zaehler >= X"00064") then -- wait 2µs
291 wiz_reset <= '1';
292 end if;
293 if (zaehler = RST_TIME) then -- wait 10ms
294 zaehler <= X"00000";
295 socket_cnt <= "000";
296 count <= "000";
297 interrupt_ignore <= '0';
298 rd <= '1';
299 wr <= '1';
300 cs <= '1';
301 -- reset states
302 state_write <= WR_START;
303 state_init <= INIT;
304 state_read_data <= RD_1;
305 next_state_read_data <= RD_CMD;
306 state_write_sd <= WRITE_SD_START;
307 state_read_sd <= READ_SD_START;
308 state_read_fl <= READ_FL_START;
309 state_ping <= PING_START;
310 state_read_dd <= READ_DD_START;
311 state_read_dd_block <= READ_DD_BLOCK_START;
312 state_send_ftu_error <= SFE_START;
313 -- reset output signals
314 new_config <= '0';
315 config_started_ack <= '1';
316 ping_ftu_start <= '0';
317 sd_write <= '0';
318 sd_read <= '0';
319 dd_block_start <= '0';
320 dd_block_ready <= '1';
321 dd_send_ack <= '1';
322 dd_send_ready <= '1';
323 dd_read <= '0';
324 dd_write_general <= '0';
325 fl_read <= '0';
326 ftu_error_send_ack <= '1';
327 ftu_error_send_ready <= '1';
328 -- set internal signals
329 new_config_flag <= '0';
330 chk_recv_cntr <= 0;
331 next_packet_data_cnt <= 0;
332 internal_cmd <= '0';
333 -- -- --
334 led_int <= X"00";
335 -- -- --
336 end if;
337
338 -- Init
339 when INIT =>
340 par_addr <= W5300_MR;
341 par_data <= X"0000";
342 state_init <= WRITE_REG;
343 next_state <= IM;
344
345 -- Interrupt Mask
346 when IM =>
347 par_addr <= W5300_IMR;
348 par_data <= X"00FF"; -- S0-S7 Interrupts
349 state_init <= WRITE_REG;
350 next_state <= MT;
351
352 -- Memory Type
353 when MT =>
354 par_addr <= W5300_MTYPER;
355 par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer
356 state_init <= WRITE_REG;
357 next_state <= STX;
358
359 -- Socket TX Memory Size
360 when STX =>
361 par_data <= X"4000"; -- 64K TX for socket 0, others 0
362
363 par_addr <= W5300_TMS01R;
364 state_init <= WRITE_REG;
365 next_state <= STX1;
366 when STX1 =>
367 par_data <= X"0000";
368 par_addr <= W5300_TMS23R;
369 state_init <= WRITE_REG;
370 next_state <= STX2;
371 when STX2 =>
372 par_addr <= W5300_TMS45R;
373 state_init <= WRITE_REG;
374 next_state <= STX3;
375 when STX3 =>
376 par_addr <= W5300_TMS67R;
377 state_init <= WRITE_REG;
378 next_state <= SRX;
379
380 -- Socket RX Memory Size
381 when SRX =>
382 par_data <= X"4000"; -- 64K RX for socket 0, others 0
383
384 par_addr <= W5300_RMS01R;
385 state_init <= WRITE_REG;
386 next_state <= SRX1;
387 when SRX1 =>
388 par_data <= X"0000";
389 par_addr <= W5300_RMS23R;
390 state_init <= WRITE_REG;
391 next_state <= SRX2;
392 when SRX2 =>
393 par_addr <= W5300_RMS45R;
394 state_init <= WRITE_REG;
395 next_state <= SRX3;
396 when SRX3 =>
397 par_addr <= W5300_RMS67R;
398 state_init <= WRITE_REG;
399 next_state <= MAC;
400
401 -- MAC
402 when MAC =>
403 par_addr <= W5300_SHAR;
404 par_data <= MAC_ADDRESS (0);
405 state_init <= WRITE_REG;
406 next_state <= MAC1;
407 when MAC1 =>
408 par_addr <= W5300_SHAR + 2;
409 par_data <= MAC_ADDRESS (1);
410 state_init <= WRITE_REG;
411 next_state <= MAC2;
412 when MAC2 =>
413 par_addr <= W5300_SHAR + 4;
414 par_data <= MAC_ADDRESS (2);
415 state_init <= WRITE_REG;
416 next_state <= GW;
417
418 -- Gateway
419 when GW =>
420 par_addr <= W5300_GAR;
421 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8);
422 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8);
423 state_init <= WRITE_REG;
424 next_state <= GW1;
425 when GW1 =>
426 par_addr <= W5300_GAR + 2;
427 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8);
428 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8);
429 state_init <= WRITE_REG;
430 next_state <= SNM;
431
432 -- Subnet Mask
433 when SNM =>
434 par_addr <= W5300_SUBR;
435 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8);
436 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8);
437 state_init <= WRITE_REG;
438 next_state <= SNM1;
439 when SNM1 =>
440 par_addr <= W5300_SUBR + 2;
441 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8);
442 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8);
443 state_init <= WRITE_REG;
444 next_state <= IP;
445 -- Own IP-Address
446 when IP =>
447 par_addr <= W5300_SIPR;
448 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8);
449 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8);
450 state_init <= WRITE_REG;
451 next_state <= IP1;
452 when IP1 =>
453 par_addr <= W5300_SIPR + 2;
454 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8);
455 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8);
456 state_init <= WRITE_REG;
457 next_state <= SI;
458 -- Socket Init
459 when SI =>
460 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
461 par_data <= X"0101"; -- ALIGN, TCP
462 state_init <= WRITE_REG;
463 next_state <= SI1;
464 -- Sx Interrupt Mask
465 when SI1 =>
466 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
467 par_data <= X"000A"; -- TIMEOUT, DISCON
468 state_init <= WRITE_REG;
469 next_state <= SI2;
470 when SI2 =>
471 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
472 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
473 state_init <= WRITE_REG;
474 next_state <= SI3;
475 when SI3 =>
476 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
477 par_data <= X"0001"; -- OPEN
478 state_init <= WRITE_REG;
479 next_state <= SI4;
480 when SI4 =>
481 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
482 state_init <= READ_REG;
483 next_state <= SI5;
484 when SI5 =>
485 if (data_read (7 downto 0) = X"13") then -- is open?
486 state_init <= SI6;
487 else
488 state_init <= SI4;
489 end if;
490 when SI6 =>
491 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
492 par_data <= X"0002"; -- LISTEN
493 state_init <= WRITE_REG;
494 socket_cnt <= socket_cnt + 1;
495 if (socket_cnt = W5300_LAST_SOCKET) then
496 socket_cnt <= "000";
497 next_state <= ESTABLISH; -- All Sockets open
498 else
499 next_state <= SI; -- Next Socket
500 end if;
501 -- End Socket Init
502
503 when ESTABLISH =>
504 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
505 state_init <= READ_REG;
506 next_state <= EST1;
507 when EST1 =>
508 case data_read (7 downto 0) is
509 when X"17" => -- established
510 if (socket_cnt = W5300_LAST_SOCKET) then
511 socket_cnt <= "000";
512 busy <= '0';
513 state_init <= MAIN;
514 -- -- --
515 config_started_ack <= '0';
516 dd_block_ready <= '0';
517 dd_send_ack <= '0';
518 dd_send_ready <= '0';
519 ftu_error_send_ack <= '0';
520 ftu_error_send_ready <= '0';
521 led_int <= X"00";
522 -- -- --
523 else
524 socket_cnt <= socket_cnt + 1;
525 state_init <= ESTABLISH;
526 end if;
527 when others =>
528 state_init <= ESTABLISH;
529 -- -- --
530 -- Just for fun...
531 if (led_cnt = 1100000) then
532 if (led_int = X"00") then
533 led_int <= X"18";
534 else
535 led_int (7 downto 4) <= led_int (6 downto 4) & '0';
536 led_int (3 downto 0) <= '0' & led_int (3 downto 1);
537 end if;
538 led_cnt <= 0;
539 else
540 led_cnt <= led_cnt + 1;
541 end if;
542 -- -- --
543 end case;
544
545 when CONFIG =>
546 new_config <= '1';
547 config_started_ack <= '0';
548 if (config_started = '1') then
549 new_config <= '0';
550 config_started_ack <= '1';
551 state_init <= MAIN;
552 end if;
553
554 -- main "loop"
555 when MAIN =>
556 chk_recv_cntr <= chk_recv_cntr + 1;
557 if (chk_recv_cntr = 1000) then
558 chk_recv_cntr <= 0;
559 state_read_data <= RD_1;
560 state_init <= READ_DATA;
561 busy <= '1';
562 elsif (dd_send = '1') then
563 internal_cmd <= '1';
564 dd_send_ack <= '1';
565 dd_send_ready <= '0';
566 if (autosend_flag = '0') then
567 state_read_dd_block <= READ_DD_BLOCK_END;
568 end if;
569 state_read_data <= RD_READ_DD_BLOCK;
570 state_init <= READ_DATA;
571 elsif (ftu_error_send = '1') then
572 ftu_error_send_ack <= '1';
573 ftu_error_send_ready <= '0';
574 if (autosend_flag = '0') then
575 state_send_ftu_error <= SFE_END;
576 end if;
577 state_init <= SEND_FTU_ERROR;
578 end if;
579
580
581 -- send FTU error message
582 when SEND_FTU_ERROR =>
583 case state_send_ftu_error is
584 when SFE_START =>
585 next_state <= SEND_FTU_ERROR;
586 data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR;
587 data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end
588 read_addr_state <= READ_FTU_ERROR;
589 local_sd_addr <= X"000";
590 local_write_length <= "00000" & FTU_ERROR_LENGTH;
591 state_send_ftu_error <= SFE_END;
592 state_init <= WRITE_DATA;
593 when SFE_END =>
594 if (ftu_error_send = '0') then
595 ftu_error_send_ack <= '0';
596 ftu_error_send_ready <= '1';
597 state_send_ftu_error <= SFE_START;
598 state_init <= MAIN;
599 end if;
600 end case;
601
602
603 -- read data from socket 0
604 when READ_DATA =>
605 case state_read_data is
606 when RD_1 =>
607 par_addr <= W5300_S0_RX_RSR;
608 state_init <= READ_REG;
609 next_state <= READ_DATA;
610 state_read_data <= RD_2;
611 when RD_2 =>
612 socket_rx_received (31 downto 16) <= data_read;
613 par_addr <= W5300_S0_RX_RSR + X"2";
614 state_init <= READ_REG;
615 next_state <= READ_DATA;
616 state_read_data <= RD_3;
617 when RD_3 =>
618 socket_rx_received (15 downto 0) <= data_read;
619 state_read_data <= RD_4;
620 when RD_4 =>
621 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
622 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
623 state_read_data <= RD_5;
624 else
625 busy <= '0';
626 state_init <= MAIN;
627 end if;
628 when RD_5 =>
629 if (rx_packets_cnt > 0) then
630 rx_packets_cnt <= rx_packets_cnt - '1';
631 par_addr <= W5300_S0_RX_FIFOR;
632 state_init <= READ_REG;
633 next_state <= READ_DATA;
634 state_read_data <= next_state_read_data;
635 else
636 state_read_data <= RD_END;
637 end if;
638
639 when RD_END =>
640 if (new_config_flag = '1') then
641 new_config_flag <= '0';
642 next_state <= CONFIG;
643 else
644 next_state <= MAIN;
645 end if;
646 if (internal_cmd = '0') then
647 par_addr <= W5300_S0_CR;
648 par_data <= X"0040"; -- RECV
649 state_init <= WRITE_REG;
650 else
651 internal_cmd <= '0';
652 state_init <= MAIN;
653 end if;
654
655
656 -------------------------
657 -- command handling
658 -------------------------
659
660 -- read command (5 words)
661 when RD_CMD =>
662 cmd_array (next_packet_data_cnt) <= data_read;
663 next_packet_data_cnt <= next_packet_data_cnt + 1;
664 -- look for command start
665 if (next_packet_data_cnt = 0) then
666 if (data_read /= CMD_START_DELIMITER) then
667 next_packet_data_cnt <= 0;
668 end if;
669 end if;
670 -- last command-word
671 if (next_packet_data_cnt = 4) then
672 next_packet_data_cnt <= 0;
673 state_read_data <= RD_CMD_PARSE;
674 else
675 state_read_data <= RD_5;
676 end if;
677
678 -- process commands and parameters
679 when RD_CMD_PARSE =>
680 case cmd_array (1) is
681
682 when CMD_TLED =>
683 led_int <= NOT led_int;
684 state_read_data <= RD_5;
685
686 when CMD_START =>
687 case cmd_array (2) is
688 -- start "normal" run
689 when PAR_START_RUN =>
690 start_run <= '1';
691 start_run_param <= cmd_array (2);
692 if (start_run_ack = '1') then
693 start_run <= '0';
694 state_read_data <= RD_5;
695 end if;
696 -- start run an take X events
697 when PAR_START_X_EVNTS =>
698 next_state_read_data <= RD_X_EVNTS;
699 state_read_data <= RD_5;
700 when others =>
701 state_read_data <= RD_5;
702 end case;
703
704 when CMD_STOP =>
705 stop_run <= '1';
706 if (stop_run_ack = '1') then
707 stop_run <= '0';
708 state_read_data <= RD_5;
709 end if;
710
711 when CMD_CRESET =>
712 crate_reset <= '1';
713 crate_reset_param <= cmd_array (2);
714 if (crate_reset_ack = '1') then
715 crate_reset <= '0';
716 state_read_data <= RD_5;
717 end if;
718
719 when CMD_WRITE =>
720 case cmd_array (2) is
721 -- write to address in static data block
722 when PAR_WRITE_SD_ADDR =>
723 new_config_flag <= '1';
724 next_state_read_data <= RD_WRITE_SD_ADDR;
725 state_read_data <= RD_5;
726 -- write static data block
727 when PAR_WRITE_SD =>
728 new_config_flag <= '1';
729 next_state_read_data <= RD_WRITE_SD_BLOCK;
730 state_read_data <= RD_5;
731 when others =>
732 state_read_data <= RD_5;
733 end case; -- cmd_array (2)
734
735 when CMD_READ =>
736 case cmd_array (2) is
737 -- read from address in static data block
738 when PAR_READ_SD_ADDR =>
739 next_state_read_data <= RD_READ_SD_ADDR;
740 state_read_data <= RD_5;
741 -- read static data block
742 when PAR_READ_SD =>
743 state_read_data <= RD_READ_SD_BLOCK;
744 -- read dynamic data block
745 when PAR_READ_DD =>
746 state_read_data <= RD_READ_DD_BLOCK;
747 when others =>
748 state_read_data <= RD_5;
749 end case; -- cmd_array (2)
750
751 when CMD_PING =>
752 state_ping <= PING_START;
753 state_read_data <= RD_PING;
754
755 when CMD_AUTOSEND =>
756 state_read_data <= RD_5;
757 case cmd_array (2) is
758 when PAR_AUTOSEND_EA =>
759 autosend_flag <= '1';
760 when PAR_AUTOSEND_DA =>
761 autosend_flag <= '0';
762 when others =>
763 null;
764 end case;
765
766 when others =>
767 state_read_data <= RD_5;
768
769 end case; -- cmd_array (1)
770
771
772 -- ping all FTUs and write FTU-list to ethernet
773 when RD_PING =>
774 case state_ping is
775 when PING_START =>
776 ping_ftu_start <= '1';
777 if (ping_ftu_started = '1') then
778 ping_ftu_start <= '0';
779 state_ping <= PING_WAIT;
780 end if;
781 when PING_WAIT =>
782 if (ping_ftu_ready = '1') then
783 state_ping <= PING_WRITE_LIST;
784 end if;
785 when PING_WRITE_LIST =>
786 state_read_data <= RD_5;
787 data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST;
788 data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end
789 read_addr_state <= READ_FROM_FL_ADDR;
790 local_sd_addr <= X"000"; --start at address 0x000
791 local_write_length <= "00000" & FL_BLOCK_SIZE;
792 next_state_read_data <= RD_CMD;
793 next_state <= READ_DATA;
794 state_init <= WRITE_DATA;
795 end case;
796
797 -- read dynamic data block and write it to ethernet
798 when RD_READ_DD_BLOCK =>
799 case state_read_dd_block is
800 when READ_DD_BLOCK_START =>
801 dd_block_start <= '1';
802 dd_block_ready <= '0';
803 if (dd_block_start_ack = '1') then
804 dd_block_start <= '0';
805 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;
806 end if;
807 -- write on-time counter and tempertures to dd-block
808 when READ_DD_BLOCK_WRITE_GENERAL =>
809 dd_write_general <= '1';
810 if (dd_write_general_started = '1') then
811 dd_write_general <= '0';
812 state_read_dd_block <= READ_DD_BLOCK_WRITE;
813 end if;
814 -- write dd-block to ethernet when on-time counter and temperatures are ready
815 when READ_DD_BLOCK_WRITE =>
816 if (dd_write_general_ready = '1') then
817 data_package_type <= FTM_PACKAGE_TYPE_DD;
818 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end
819 read_addr_state <= READ_FROM_DD_ADDR;
820 local_sd_addr <= X"000"; -- start at address 0x000
821 local_write_length <= "00000" & DD_BLOCK_SIZE;
822 state_read_dd_block <= READ_DD_BLOCK_END;
823 next_state <= READ_DATA;
824 state_init <= WRITE_DATA;
825 end if;
826 when READ_DD_BLOCK_END =>
827 dd_block_ready <= '1';
828 next_state_read_data <= RD_CMD;
829 --
830 if (internal_cmd = '1') then
831 state_read_dd_block <= READ_DD_BLOCK_INTERN;
832 else
833 state_read_dd_block <= READ_DD_BLOCK_START;
834 state_read_data <= RD_5;
835 end if;
836 when READ_DD_BLOCK_INTERN =>
837 if (dd_send = '0') then
838 dd_send_ready <= '1';
839 dd_send_ack <= '0';
840 state_read_dd_block <= READ_DD_BLOCK_START;
841 state_read_data <= RD_5;
842 end if;
843
844 end case;
845
846 -- read static data block and write it to ethernet
847 when RD_READ_SD_BLOCK =>
848 data_package_type <= FTM_PACKAGE_TYPE_SD;
849 data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end
850 state_read_data <= RD_5;
851 read_addr_state <= READ_FROM_SD_ADDR;
852 local_sd_addr <= X"000"; -- start at address 0x000
853 local_write_length <= "00000" & SD_BLOCK_SIZE;
854 next_state_read_data <= RD_CMD;
855 next_state <= READ_DATA;
856 state_init <= WRITE_DATA;
857
858 -- read from address in static data ram and write data to ethernet
859 when RD_READ_SD_ADDR =>
860 data_package_type <= FTM_PACKAGE_TYPE_SD_WORD;
861 data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end
862 state_read_data <= RD_5;
863 read_addr_state <= READ_FROM_SD_ADDR;
864 local_sd_addr <= data_read (11 downto 0);
865 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
866 next_state_read_data <= RD_CMD;
867 next_state <= READ_DATA;
868 state_init <= WRITE_DATA;
869
870 -- read static data block from ethernet and write it to static data ram
871 when RD_WRITE_SD_BLOCK =>
872 state_read_data <= RD_5;
873 next_packet_data_cnt <= next_packet_data_cnt + 1;
874 local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12);
875 local_sd_data <= data_read;
876 next_state <= READ_DATA;
877 state_init <= WRITE_TO_SD_ADDR;
878 -- last word
879 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
880 next_packet_data_cnt <= 0;
881 next_state_read_data <= RD_CMD;
882 end if;
883
884 -- write to address in static data ram
885 when RD_WRITE_SD_ADDR =>
886 state_read_data <= RD_5;
887 next_packet_data_cnt <= next_packet_data_cnt + 1;
888 if (next_packet_data_cnt = 0) then
889 local_sd_addr <= data_read (11 downto 0);
890 else
891 local_sd_data <= data_read;
892 next_packet_data_cnt <= 0;
893 next_state_read_data <= RD_CMD;
894 next_state <= READ_DATA;
895 state_init <= WRITE_TO_SD_ADDR;
896 end if;
897
898 -- read X events
899 when RD_X_EVNTS =>
900 if (next_packet_data_cnt = 0) then
901 start_run_num_events (31 downto 16) <= data_read;
902 else
903 start_run_num_events (15 downto 0) <= data_read;
904 start_run_param <= cmd_array (2);
905 start_run <= '1';
906 if (start_run_ack = '1') then
907 start_run <= '0';
908 next_packet_data_cnt <= 0;
909 next_state_read_data <= RD_CMD;
910 state_read_data <= RD_5;
911 end if;
912 end if;
913
914 end case; -- state_read_data
915
916
917 -- read FTU errors
918 when READ_FTU_ERROR =>
919 state_init <= next_state;
920 if (data_cnt = 0) then
921 local_sd_data <= ftu_error_calls;
922 else
923 local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8));
924 end if;
925
926
927 -- read from header modul
928 when READ_FROM_HEADER_MODUL =>
929 state_init <= next_state;
930 case header_cnt is
931 when X"00" =>
932 local_sd_data <= data_package_type;
933 when X"01" =>
934 local_sd_data <= data_package_length;
935 when X"02" =>
936 local_sd_data <= header_current_state;
937 when X"03" =>
938 local_sd_data <= header_board_id (63 DOWNTO 48);
939 when X"04" =>
940 local_sd_data <= header_board_id (47 DOWNTO 32);
941 when X"05" =>
942 local_sd_data <= header_board_id (31 DOWNTO 16);
943 when X"06" =>
944 local_sd_data <= header_board_id (15 DOWNTO 0);
945 when X"07" =>
946 local_sd_data <= header_firmware_id;
947 when X"08" =>
948 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
949 when X"09" =>
950 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
951 when X"0A" =>
952 local_sd_data <= X"0000";
953 when X"0B" =>
954 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
955 when X"0C" =>
956 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
957 when X"0D" =>
958 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
959 when others =>
960 null;
961 end case;
962
963 -- read from ftu list ram
964 when READ_FROM_FL_ADDR =>
965 case state_read_fl is
966 when READ_FL_START =>
967 if (fl_busy = '0') then
968 fl_addr <= local_sd_addr;
969 fl_read <= '1';
970 state_read_fl <= READ_FL_WAIT;
971 end if;
972 when READ_FL_WAIT =>
973 if (fl_started = '1') then
974 state_read_fl <= READ_FL_END;
975 end if;
976 when READ_FL_END =>
977 if (fl_ready = '1') then
978 local_sd_data <= fl_data_in;
979 fl_read <= '0';
980 state_read_fl <= READ_FL_START;
981 state_init <= next_state;
982 end if;
983 end case;
984
985 -- read from dynamic data block
986 when READ_FROM_DD_ADDR =>
987 case state_read_dd is
988 when READ_DD_START =>
989 if (dd_busy = '0') then
990 dd_addr <= local_sd_addr;
991 dd_read <= '1';
992 state_read_dd <= READ_DD_WAIT;
993 end if;
994 when READ_DD_WAIT =>
995 if (dd_started = '1') then
996 state_read_dd <= READ_DD_END;
997 end if;
998 when READ_DD_END =>
999 if (dd_ready = '1') then
1000 local_sd_data <= dd_data_in;
1001 dd_read <= '0';
1002 state_read_dd <= READ_DD_START;
1003 state_init <= next_state;
1004 end if;
1005 end case;
1006
1007 -- read from static data block
1008 when READ_FROM_SD_ADDR =>
1009 case state_read_sd is
1010 when READ_SD_START =>
1011 if (sd_busy = '0') then
1012 sd_addr <= local_sd_addr;
1013 sd_read <= '1';
1014 state_read_sd <= READ_SD_WAIT;
1015 end if;
1016 when READ_SD_WAIT =>
1017 if (sd_started = '1') then
1018 state_read_sd <= READ_SD_END;
1019 end if;
1020 when READ_SD_END =>
1021 if (sd_ready = '1') then
1022 local_sd_data <= sd_data_in;
1023 sd_read <= '0';
1024 state_read_sd <= READ_SD_START;
1025 state_init <= next_state;
1026 end if;
1027 end case;
1028
1029 -- write to static data block
1030 when WRITE_TO_SD_ADDR =>
1031 case state_write_sd is
1032 when WRITE_SD_START =>
1033 if (sd_busy = '0') then
1034 sd_addr <= local_sd_addr;
1035 sd_data_out <= local_sd_data;
1036 sd_write <= '1';
1037 state_write_sd <= WRITE_SD_WAIT;
1038 end if;
1039 when WRITE_SD_WAIT =>
1040 if (sd_started = '1') then
1041 sd_write <= '0';
1042 state_write_sd <= WRITE_SD_END;
1043 end if;
1044 when WRITE_SD_END =>
1045 if (sd_ready = '1') then
1046 state_write_sd <= WRITE_SD_START;
1047 state_init <= next_state;
1048 end if;
1049 end case;
1050
1051 -- write to ethernet interface
1052 when WRITE_DATA =>
1053 case state_write is
1054 when WR_START =>
1055 state_write <= WR_LENGTH;
1056 when WR_LENGTH =>
1057 local_socket_nr <= "000";
1058 next_state_tmp <= next_state;
1059 -- Write Length: 2 := START and END of package
1060 write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2)
1061 data_cnt <= 0;
1062 header_cnt <= X"00";
1063 state_write <= WR_01;
1064 -- Check FIFO Size
1065 when WR_01 =>
1066 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
1067 state_init <= READ_REG;
1068 next_state <= WRITE_DATA;
1069 state_write <= WR_02;
1070 when WR_02 =>
1071 socket_tx_free (31 downto 16) <= data_read;
1072 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
1073 state_init <= READ_REG;
1074 next_state <= WRITE_DATA;
1075 state_write <= WR_03;
1076 when WR_03 =>
1077 socket_tx_free (15 downto 0) <= data_read;
1078 state_write <= WR_04;
1079 when WR_04 =>
1080 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1081 state_write <= WR_01;
1082 else
1083 state_write <= WR_WRITE_START_DEL;
1084 end if;
1085
1086 -- write package start delimiter
1087 when WR_WRITE_START_DEL =>
1088 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1089 par_data <= FTM_PACKAGE_START;
1090 state_init <= WRITE_REG;
1091 next_state <= WRITE_DATA;
1092 state_write <= WR_GET_HEADER;
1093
1094 -- get header data
1095 when WR_GET_HEADER =>
1096 get_header <= '1';
1097 if (get_header_started = '1') then
1098 get_header <= '0';
1099 state_write <= WR_GET_HEADER_WAIT;
1100 end if;
1101
1102 when WR_GET_HEADER_WAIT =>
1103 if (get_header_ready = '1') then
1104 state_write <= WR_FIFO_HEADER;
1105 end if;
1106
1107 -- Fill FIFO
1108 when WR_FIFO_HEADER =>
1109 state_init <= READ_FROM_HEADER_MODUL;
1110 next_state <= WRITE_DATA;
1111 state_write <= WR_FIFO_HEADER_01;
1112
1113 when WR_FIFO_HEADER_01 =>
1114 header_cnt <= header_cnt + 1;
1115 if (header_cnt < FTM_HEADER_LENGTH) then
1116 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1117 par_data <= local_sd_data;
1118 state_init <= WRITE_REG;
1119 next_state <= WRITE_DATA;
1120 state_write <= WR_FIFO_HEADER;
1121 else
1122 state_write <= WR_FIFO_DATA;
1123 end if;
1124
1125 when WR_FIFO_DATA =>
1126 state_init <= read_addr_state;
1127 next_state <= WRITE_DATA;
1128 state_write <= WR_FIFO_DATA_01;
1129
1130 when WR_FIFO_DATA_01 =>
1131 data_cnt <= data_cnt + 1;
1132 if (data_cnt < local_write_length) then
1133 local_sd_addr <= local_sd_addr + 1;
1134 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1135 par_data <= local_sd_data;
1136 state_init <= WRITE_REG;
1137 next_state <= WRITE_DATA;
1138 state_write <= WR_FIFO_DATA;
1139 else
1140 state_write <= WR_WRITE_END_DEL;
1141 end if;
1142
1143 -- write package end delimiter
1144 when WR_WRITE_END_DEL =>
1145 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1146 par_data <= FTM_PACKAGE_END;
1147 state_init <= WRITE_REG;
1148 next_state <= WRITE_DATA;
1149 state_write <= WR_05;
1150
1151 -- Send FIFO
1152 when WR_05 =>
1153 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
1154 par_data <= (0 => write_length_bytes (16), others => '0');
1155 state_init <= WRITE_REG;
1156 state_write <= WR_06;
1157 when WR_06 =>
1158 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1159 par_data <= write_length_bytes (15 downto 0);
1160 state_init <= WRITE_REG;
1161 state_write <= WR_07;
1162 when WR_07 =>
1163 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1164 par_data <= X"0020"; -- Send
1165 state_init <= WRITE_REG;
1166 state_write <= WR_08;
1167 when others =>
1168 state_init <= next_state_tmp;
1169 state_write <= WR_START;
1170 end case;
1171 -- End WRITE_DATA
1172
1173 when READ_REG =>
1174 case count is
1175 when "000" =>
1176 cs <= '0';
1177 rd <= '0';
1178 wr <= '1';
1179 data <= (others => 'Z'); -- !!!!!!!!!!
1180 count <= "001";
1181 addr <= par_addr;
1182 when "001" =>
1183 count <= "010";
1184 when "010" =>
1185 count <= "100";
1186 when "100" =>
1187 data_read <= data;
1188 count <= "110";
1189 when "110" =>
1190 count <= "111";
1191 when "111" =>
1192 cs <= '1';
1193 rd <= '1';
1194 count <= "000";
1195 state_init <= next_state;
1196 when others =>
1197 null;
1198 end case;
1199
1200 when WRITE_REG =>
1201 case count is
1202 when "000" =>
1203 cs <= '0';
1204 wr <= '0';
1205 rd <= '1';
1206 addr <= par_addr;
1207 data <= par_data;
1208 count <= "100";
1209 when "100" =>
1210 count <= "101";
1211 when "101" =>
1212 count <= "110";
1213 when "110" =>
1214 cs <= '1';
1215 wr <= '1';
1216 state_init <= next_state;
1217 count <= "000";
1218 when others =>
1219 null;
1220 end case;
1221
1222 when others =>
1223 null;
1224 end case;
1225 end if; -- int_flag = '0'
1226
1227 end if; -- rising_edge (clk)
1228
1229 end process w5300_init_proc;
1230
1231end Behavioral;
1232
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