1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: |
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4 | -- |
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5 | -- Create Date: 11:48:48 11/10/2009 |
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6 | -- Design Name: |
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7 | -- Module Name: w5300_modul - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | LIBRARY IEEE; |
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21 | USE IEEE.STD_LOGIC_1164.all; |
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22 | USE IEEE.STD_LOGIC_ARITH.all; |
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23 | USE IEEE.STD_LOGIC_UNSIGNED.all; |
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24 | |
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25 | library ftm_definitions; |
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26 | USE ftm_definitions.ftm_array_types.all; |
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27 | USE ftm_definitions.ftm_constants.all; |
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28 | |
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29 | -- Uncomment the following library declaration if instantiating |
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30 | -- any Xilinx primitives in this code. |
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31 | library UNISIM; |
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32 | use UNISIM.VComponents.all; |
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33 | |
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34 | ENTITY w5300_modul IS |
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35 | PORT( |
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36 | clk : IN std_logic; |
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37 | wiz_reset : OUT std_logic := '1'; |
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38 | addr : OUT std_logic_vector (9 DOWNTO 0); |
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39 | data : INOUT std_logic_vector (15 DOWNTO 0); |
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40 | cs : OUT std_logic := '1'; |
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41 | wr : OUT std_logic := '1'; |
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42 | led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); |
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43 | rd : OUT std_logic := '1'; |
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44 | int : IN std_logic; |
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45 | busy : OUT std_logic := '1'; |
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46 | new_config : OUT std_logic := '0'; |
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47 | config_started : IN std_logic; |
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48 | config_started_ack : OUT std_logic := '0'; |
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49 | -- |
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50 | ping_ftu_start : OUT std_logic := '0'; |
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51 | ping_ftu_started : IN std_logic; |
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52 | ping_ftu_ready : IN std_logic; |
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53 | -- |
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54 | sd_addr : OUT std_logic_vector (11 DOWNTO 0); |
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55 | sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); |
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56 | sd_data_in : IN std_logic_vector (15 DOWNTO 0); |
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57 | sd_write : OUT std_logic := '0'; |
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58 | sd_read : OUT std_logic := '0'; |
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59 | sd_started : IN std_logic; |
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60 | sd_ready : IN std_logic; |
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61 | sd_busy : IN std_logic; |
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62 | -- |
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63 | dd_block_start : OUT std_logic := '0'; |
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64 | dd_block_start_ack : IN std_logic; |
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65 | dd_block_ready : OUT std_logic := '1'; |
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66 | dd_send : IN std_logic; |
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67 | dd_send_ack : OUT std_logic := '1'; |
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68 | dd_send_ready : OUT std_logic := '1'; |
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69 | dd_addr : OUT std_logic_vector (11 DOWNTO 0); |
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70 | dd_data_in : IN std_logic_vector (15 DOWNTO 0); |
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71 | dd_read : OUT std_logic := '0'; |
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72 | dd_started : IN std_logic; |
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73 | dd_ready : IN std_logic; |
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74 | dd_busy : IN std_logic; |
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75 | dd_write_general : OUT std_logic := '0'; |
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76 | dd_write_general_started : IN std_logic; |
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77 | dd_write_general_ready : IN std_logic; |
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78 | -- |
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79 | fl_addr : OUT std_logic_vector (11 DOWNTO 0); |
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80 | fl_data_in : IN std_logic_vector (15 DOWNTO 0); |
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81 | fl_read : OUT std_logic := '0'; |
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82 | fl_started : IN std_logic; |
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83 | fl_ready : IN std_logic; |
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84 | fl_busy : IN std_logic; |
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85 | -- |
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86 | ftu_error_send : IN std_logic; |
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87 | ftu_error_send_ack : OUT std_logic := '1'; |
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88 | ftu_error_send_ready : OUT std_logic := '1'; |
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89 | ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); |
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90 | ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 |
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91 | -- |
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92 | get_header : OUT std_logic := '0'; |
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93 | get_header_started : IN std_logic; |
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94 | get_header_ready : IN std_logic; |
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95 | header_board_id : IN std_logic_vector (63 DOWNTO 0); |
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96 | header_firmware_id : IN std_logic_vector (15 DOWNTO 0); |
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97 | header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); |
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98 | header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0); |
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99 | header_current_state : IN std_logic_vector (15 DOWNTO 0); |
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100 | -- |
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101 | start_run : OUT std_logic := '0'; |
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102 | start_run_ack : IN std_logic; |
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103 | start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); |
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104 | start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); |
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105 | stop_run : OUT std_logic := '0'; |
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106 | stop_run_ack : IN std_logic; |
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107 | crate_reset : OUT std_logic := '0'; |
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108 | crate_reset_ack : IN std_logic; |
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109 | crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') |
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110 | ); |
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111 | |
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112 | END w5300_modul ; |
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113 | |
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114 | architecture Behavioral of w5300_modul is |
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115 | |
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116 | type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, |
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117 | INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, |
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118 | SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, |
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119 | READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_DD_BLOCK, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); |
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120 | type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, |
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121 | WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); |
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122 | type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); |
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123 | type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); |
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124 | type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); |
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125 | type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); |
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126 | type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); |
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127 | type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END); |
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128 | type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST); |
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129 | type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END); |
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130 | type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); |
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131 | type state_send_ftu_error_type is (SFE_START, SFE_END); |
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132 | type state_rd_x_evnts_type is (RD_X_01, RD_X_02, RD_X_03); |
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133 | |
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134 | signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; |
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135 | |
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136 | signal par_addr : std_logic_vector (9 downto 0) := (others => '0'); |
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137 | signal par_data : std_logic_vector (15 downto 0) := (others => '0'); |
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138 | signal data_read : std_logic_vector (15 downto 0) := (others => '0'); |
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139 | |
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140 | signal state_init, next_state , next_state_tmp : state_init_type := RESET; |
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141 | signal read_addr_state : state_init_type := RESET; |
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142 | signal count : std_logic_vector (2 downto 0) := "000"; |
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143 | signal state_write : state_write_type := WR_START; |
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144 | signal state_interrupt_1 : state_interrupt_1_type := IR1_01; |
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145 | signal state_interrupt_2 : state_interrupt_2_type := IR2_01; |
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146 | signal state_read_data : state_read_data_type := RD_1; |
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147 | signal next_state_read_data : state_read_data_type := RD_CMD; |
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148 | signal state_write_sd : state_write_sd_type := WRITE_SD_START; |
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149 | signal state_read_sd : state_read_sd_type := READ_SD_START; |
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150 | signal state_read_fl : state_read_fl_type := READ_FL_START; |
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151 | signal state_ping : state_ping_type := PING_START; |
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152 | signal state_read_dd : state_read_dd_type := READ_DD_START; |
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153 | signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START; |
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154 | signal state_send_ftu_error : state_send_ftu_error_type := SFE_START; |
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155 | signal state_rd_x_evnts : state_rd_x_evnts_type := RD_X_01; |
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156 | |
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157 | signal interrupt_ignore : std_logic := '1'; |
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158 | signal int_flag : std_logic := '0'; |
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159 | |
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160 | signal zaehler : std_logic_vector (19 downto 0) := (others => '0'); |
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161 | signal data_cnt : integer := 0; |
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162 | signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00"; |
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163 | signal socket_cnt : std_logic_vector (2 downto 0) := "000"; |
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164 | |
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165 | signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); |
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166 | signal write_length_bytes : std_logic_vector (16 downto 0); |
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167 | |
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168 | signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); |
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169 | signal chk_recv_cntr : integer range 0 to 10000 := 0; |
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170 | |
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171 | signal next_packet_data_cnt : integer range 0 to 4095 := 0; |
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172 | signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000"; |
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173 | signal new_config_flag : std_logic := '0'; |
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174 | |
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175 | signal local_write_length : std_logic_vector (16 downto 0); |
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176 | signal local_socket_nr : std_logic_vector (2 downto 0); |
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177 | |
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178 | type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0); |
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179 | signal cmd_array : cmd_array_type; |
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180 | signal internal_cmd : std_logic := '0'; |
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181 | signal wait_for_data_flag : std_logic := '0'; |
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182 | |
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183 | signal autosend_flag : std_logic := '1'; |
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184 | |
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185 | -- -- -- |
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186 | signal led_int : std_logic_vector (7 downto 0) := X"00"; |
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187 | signal led_cnt : integer range 0 to 2**22 := 0; |
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188 | -- -- -- |
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189 | |
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190 | signal local_sd_addr : std_logic_vector (11 downto 0); |
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191 | signal local_sd_data : std_logic_vector (15 downto 0); |
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192 | |
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193 | signal data_package_type : std_logic_vector (15 downto 0) := X"0000"; |
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194 | signal data_package_length : std_logic_vector (15 downto 0) := X"0000"; |
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195 | |
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196 | |
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197 | begin |
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198 | |
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199 | --synthesis translate_off |
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200 | RST_TIME <= X"00120"; |
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201 | --synthesis translate_on |
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202 | |
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203 | |
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204 | w5300_init_proc : process (clk, int) |
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205 | begin |
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206 | |
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207 | if rising_edge (clk) then |
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208 | |
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209 | -- -- -- |
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210 | led <= led_int; |
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211 | -- -- -- |
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212 | |
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213 | -- Interrupt low |
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214 | if (int = '0') and (interrupt_ignore = '0') then |
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215 | case state_interrupt_1 is |
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216 | when IR1_01 => |
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217 | int_flag <= '1'; |
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218 | busy <= '1'; |
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219 | state_interrupt_1 <= IR1_02; |
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220 | when IR1_02 => |
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221 | state_interrupt_1 <= IR1_03; |
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222 | when IR1_03 => |
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223 | state_init <= INTERRUPT; |
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224 | socket_cnt <= "000"; |
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225 | zaehler <= X"00000"; |
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226 | count <= "000"; |
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227 | int_flag <= '0'; |
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228 | interrupt_ignore <= '1'; |
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229 | state_interrupt_1 <= IR1_04; |
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230 | when others => |
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231 | null; |
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232 | end case; |
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233 | end if; -- int = '0' |
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234 | |
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235 | if int_flag = '0' then |
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236 | case state_init is |
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237 | -- Interrupt |
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238 | when INTERRUPT => |
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239 | case state_interrupt_2 is |
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240 | when IR2_01 => |
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241 | par_addr <= W5300_IR; |
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242 | state_init <= READ_REG; |
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243 | next_state <= INTERRUPT; |
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244 | state_interrupt_2 <= IR2_02; |
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245 | when IR2_02 => |
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246 | if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt |
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247 | state_interrupt_2 <= IR2_03; |
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248 | else |
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249 | socket_cnt <= socket_cnt + 1; |
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250 | if (socket_cnt = W5300_LAST_SOCKET) then |
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251 | state_interrupt_2 <= IR2_06; |
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252 | else |
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253 | state_interrupt_2 <= IR2_02; |
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254 | end if; |
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255 | end if; |
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256 | when IR2_03 => |
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257 | par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register |
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258 | state_init <= READ_REG; |
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259 | next_state <= INTERRUPT; |
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260 | state_interrupt_2 <= IR2_04; |
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261 | when IR2_04 => |
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262 | par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; |
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263 | par_data <= data_read; -- clear Interrupts |
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264 | state_init <= WRITE_REG; |
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265 | next_state <= INTERRUPT; |
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266 | state_interrupt_2 <= IR2_05; |
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267 | when IR2_05 => |
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268 | par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; |
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269 | par_data <= X"0010"; -- CLOSE |
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270 | state_init <= WRITE_REG; |
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271 | next_state <= INTERRUPT; |
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272 | socket_cnt <= socket_cnt + 1; |
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273 | if (socket_cnt = W5300_LAST_SOCKET) then |
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274 | state_interrupt_2 <= IR2_06; |
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275 | else |
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276 | state_interrupt_2 <= IR2_01; |
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277 | end if; |
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278 | |
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279 | when IR2_06 => |
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280 | state_interrupt_1 <= IR1_01; |
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281 | state_interrupt_2 <= IR2_01; |
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282 | socket_cnt <= "000"; |
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283 | state_init <= RESET; |
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284 | end case; |
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285 | |
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286 | -- reset W5300 |
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287 | when RESET => |
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288 | busy <= '1'; |
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289 | zaehler <= zaehler + 1; |
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290 | wiz_reset <= '0'; |
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291 | if (zaehler >= X"00064") then -- wait 2µs |
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292 | wiz_reset <= '1'; |
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293 | end if; |
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294 | if (zaehler = RST_TIME) then -- wait 10ms |
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295 | zaehler <= X"00000"; |
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296 | socket_cnt <= "000"; |
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297 | count <= "000"; |
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298 | interrupt_ignore <= '0'; |
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299 | rd <= '1'; |
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300 | wr <= '1'; |
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301 | cs <= '1'; |
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302 | -- reset states |
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303 | state_write <= WR_START; |
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304 | state_init <= INIT; |
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305 | state_read_data <= RD_1; |
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306 | next_state_read_data <= RD_CMD; |
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307 | state_write_sd <= WRITE_SD_START; |
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308 | state_read_sd <= READ_SD_START; |
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309 | state_read_fl <= READ_FL_START; |
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310 | state_ping <= PING_START; |
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311 | state_read_dd <= READ_DD_START; |
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312 | state_read_dd_block <= READ_DD_BLOCK_START; |
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313 | state_send_ftu_error <= SFE_START; |
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314 | -- reset output signals |
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315 | new_config <= '0'; |
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316 | config_started_ack <= '1'; |
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317 | ping_ftu_start <= '0'; |
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318 | sd_write <= '0'; |
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319 | sd_read <= '0'; |
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320 | dd_block_start <= '0'; |
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321 | dd_block_ready <= '1'; |
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322 | dd_send_ack <= '1'; |
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323 | dd_send_ready <= '1'; |
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324 | dd_read <= '0'; |
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325 | dd_write_general <= '0'; |
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326 | fl_read <= '0'; |
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327 | ftu_error_send_ack <= '1'; |
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328 | ftu_error_send_ready <= '1'; |
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329 | -- set internal signals |
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330 | new_config_flag <= '0'; |
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331 | chk_recv_cntr <= 0; |
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332 | next_packet_data_cnt <= 0; |
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333 | internal_cmd <= '0'; |
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334 | -- -- -- |
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335 | led_int <= X"00"; |
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336 | -- -- -- |
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337 | end if; |
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338 | |
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339 | -- Init |
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340 | when INIT => |
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341 | par_addr <= W5300_MR; |
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342 | par_data <= X"0000"; |
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343 | state_init <= WRITE_REG; |
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344 | next_state <= IM; |
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345 | |
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346 | -- Interrupt Mask |
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347 | when IM => |
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348 | par_addr <= W5300_IMR; |
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349 | par_data <= X"00FF"; -- S0-S7 Interrupts |
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350 | state_init <= WRITE_REG; |
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351 | next_state <= MT; |
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352 | |
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353 | -- Memory Type |
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354 | when MT => |
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355 | par_addr <= W5300_MTYPER; |
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356 | par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer |
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357 | state_init <= WRITE_REG; |
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358 | next_state <= STX; |
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359 | |
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360 | -- Socket TX Memory Size |
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361 | when STX => |
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362 | par_data <= X"4000"; -- 64K TX for socket 0, others 0 |
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363 | |
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364 | par_addr <= W5300_TMS01R; |
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365 | state_init <= WRITE_REG; |
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366 | next_state <= STX1; |
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367 | when STX1 => |
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368 | par_data <= X"0000"; |
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369 | par_addr <= W5300_TMS23R; |
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370 | state_init <= WRITE_REG; |
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371 | next_state <= STX2; |
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372 | when STX2 => |
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373 | par_addr <= W5300_TMS45R; |
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374 | state_init <= WRITE_REG; |
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375 | next_state <= STX3; |
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376 | when STX3 => |
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377 | par_addr <= W5300_TMS67R; |
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378 | state_init <= WRITE_REG; |
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379 | next_state <= SRX; |
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380 | |
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381 | -- Socket RX Memory Size |
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382 | when SRX => |
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383 | par_data <= X"4000"; -- 64K RX for socket 0, others 0 |
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384 | |
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385 | par_addr <= W5300_RMS01R; |
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386 | state_init <= WRITE_REG; |
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387 | next_state <= SRX1; |
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388 | when SRX1 => |
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389 | par_data <= X"0000"; |
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390 | par_addr <= W5300_RMS23R; |
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391 | state_init <= WRITE_REG; |
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392 | next_state <= SRX2; |
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393 | when SRX2 => |
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394 | par_addr <= W5300_RMS45R; |
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395 | state_init <= WRITE_REG; |
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396 | next_state <= SRX3; |
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397 | when SRX3 => |
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398 | par_addr <= W5300_RMS67R; |
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399 | state_init <= WRITE_REG; |
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400 | next_state <= MAC; |
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401 | |
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402 | -- MAC |
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403 | when MAC => |
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404 | par_addr <= W5300_SHAR; |
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405 | par_data <= MAC_ADDRESS (0); |
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406 | state_init <= WRITE_REG; |
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407 | next_state <= MAC1; |
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408 | when MAC1 => |
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409 | par_addr <= W5300_SHAR + 2; |
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410 | par_data <= MAC_ADDRESS (1); |
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411 | state_init <= WRITE_REG; |
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412 | next_state <= MAC2; |
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413 | when MAC2 => |
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414 | par_addr <= W5300_SHAR + 4; |
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415 | par_data <= MAC_ADDRESS (2); |
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416 | state_init <= WRITE_REG; |
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417 | next_state <= GW; |
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418 | |
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419 | -- Gateway |
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420 | when GW => |
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421 | par_addr <= W5300_GAR; |
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422 | par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8); |
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423 | par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8); |
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424 | state_init <= WRITE_REG; |
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425 | next_state <= GW1; |
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426 | when GW1 => |
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427 | par_addr <= W5300_GAR + 2; |
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428 | par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8); |
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429 | par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8); |
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430 | state_init <= WRITE_REG; |
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431 | next_state <= SNM; |
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432 | |
---|
433 | -- Subnet Mask |
---|
434 | when SNM => |
---|
435 | par_addr <= W5300_SUBR; |
---|
436 | par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8); |
---|
437 | par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8); |
---|
438 | state_init <= WRITE_REG; |
---|
439 | next_state <= SNM1; |
---|
440 | when SNM1 => |
---|
441 | par_addr <= W5300_SUBR + 2; |
---|
442 | par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8); |
---|
443 | par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8); |
---|
444 | state_init <= WRITE_REG; |
---|
445 | next_state <= IP; |
---|
446 | -- Own IP-Address |
---|
447 | when IP => |
---|
448 | par_addr <= W5300_SIPR; |
---|
449 | par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8); |
---|
450 | par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8); |
---|
451 | state_init <= WRITE_REG; |
---|
452 | next_state <= IP1; |
---|
453 | when IP1 => |
---|
454 | par_addr <= W5300_SIPR + 2; |
---|
455 | par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8); |
---|
456 | par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8); |
---|
457 | state_init <= WRITE_REG; |
---|
458 | next_state <= SI; |
---|
459 | -- Socket Init |
---|
460 | when SI => |
---|
461 | par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; |
---|
462 | par_data <= X"0101"; -- 0x0101: ALIGN, TCP |
---|
463 | state_init <= WRITE_REG; |
---|
464 | next_state <= SI0; |
---|
465 | -- keep alive |
---|
466 | when SI0 => |
---|
467 | par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC; |
---|
468 | par_data <= X"0C00"; -- 12 * 5s = 60s |
---|
469 | state_init <= WRITE_REG; |
---|
470 | next_state <= SI1; |
---|
471 | -- Sx Interrupt Mask |
---|
472 | when SI1 => |
---|
473 | par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; |
---|
474 | par_data <= X"000A"; -- TIMEOUT, DISCON |
---|
475 | state_init <= WRITE_REG; |
---|
476 | next_state <= SI2; |
---|
477 | when SI2 => |
---|
478 | par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; |
---|
479 | par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); |
---|
480 | state_init <= WRITE_REG; |
---|
481 | next_state <= SI3; |
---|
482 | when SI3 => |
---|
483 | par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; |
---|
484 | par_data <= X"0001"; -- OPEN |
---|
485 | state_init <= WRITE_REG; |
---|
486 | next_state <= SI4; |
---|
487 | when SI4 => |
---|
488 | par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; |
---|
489 | state_init <= READ_REG; |
---|
490 | next_state <= SI5; |
---|
491 | when SI5 => |
---|
492 | if (data_read (7 downto 0) = X"13") then -- is open? |
---|
493 | state_init <= SI6; |
---|
494 | else |
---|
495 | state_init <= SI4; |
---|
496 | end if; |
---|
497 | when SI6 => |
---|
498 | par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; |
---|
499 | par_data <= X"0002"; -- LISTEN |
---|
500 | state_init <= WRITE_REG; |
---|
501 | socket_cnt <= socket_cnt + 1; |
---|
502 | if (socket_cnt = W5300_LAST_SOCKET) then |
---|
503 | socket_cnt <= "000"; |
---|
504 | next_state <= ESTABLISH; -- All Sockets open |
---|
505 | else |
---|
506 | next_state <= SI; -- Next Socket |
---|
507 | end if; |
---|
508 | -- End Socket Init |
---|
509 | |
---|
510 | when ESTABLISH => |
---|
511 | par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; |
---|
512 | state_init <= READ_REG; |
---|
513 | next_state <= EST1; |
---|
514 | when EST1 => |
---|
515 | case data_read (7 downto 0) is |
---|
516 | when X"17" => -- established |
---|
517 | if (socket_cnt = W5300_LAST_SOCKET) then |
---|
518 | socket_cnt <= "000"; |
---|
519 | busy <= '0'; |
---|
520 | state_init <= MAIN; |
---|
521 | -- -- -- |
---|
522 | config_started_ack <= '0'; |
---|
523 | dd_block_ready <= '0'; |
---|
524 | dd_send_ack <= '0'; |
---|
525 | dd_send_ready <= '0'; |
---|
526 | ftu_error_send_ack <= '0'; |
---|
527 | ftu_error_send_ready <= '0'; |
---|
528 | led_int <= X"00"; |
---|
529 | wait_for_data_flag <= '0'; |
---|
530 | -- -- -- |
---|
531 | else |
---|
532 | socket_cnt <= socket_cnt + 1; |
---|
533 | state_init <= ESTABLISH; |
---|
534 | end if; |
---|
535 | when others => |
---|
536 | state_init <= ESTABLISH; |
---|
537 | -- -- -- |
---|
538 | -- Just for fun... |
---|
539 | if (led_cnt = 1100000) then |
---|
540 | if (led_int = X"00") then |
---|
541 | led_int <= X"18"; |
---|
542 | else |
---|
543 | led_int (7 downto 4) <= led_int (6 downto 4) & '0'; |
---|
544 | led_int (3 downto 0) <= '0' & led_int (3 downto 1); |
---|
545 | end if; |
---|
546 | led_cnt <= 0; |
---|
547 | else |
---|
548 | led_cnt <= led_cnt + 1; |
---|
549 | end if; |
---|
550 | -- -- -- |
---|
551 | end case; |
---|
552 | |
---|
553 | when CONFIG => |
---|
554 | new_config <= '1'; |
---|
555 | config_started_ack <= '0'; |
---|
556 | state_init <= MAIN; |
---|
557 | |
---|
558 | -- main "loop" |
---|
559 | when MAIN => |
---|
560 | if (config_started = '1') then |
---|
561 | new_config <= '0'; |
---|
562 | config_started_ack <= '1'; |
---|
563 | end if; |
---|
564 | chk_recv_cntr <= chk_recv_cntr + 1; |
---|
565 | if (chk_recv_cntr = 1000) then |
---|
566 | chk_recv_cntr <= 0; |
---|
567 | state_init <= READ_DATA; |
---|
568 | busy <= '1'; |
---|
569 | elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then |
---|
570 | internal_cmd <= '1'; |
---|
571 | dd_send_ack <= '1'; |
---|
572 | dd_send_ready <= '0'; |
---|
573 | if (autosend_flag = '0') then |
---|
574 | state_read_dd_block <= READ_DD_BLOCK_END; |
---|
575 | end if; |
---|
576 | state_init <= READ_DD_BLOCK; |
---|
577 | elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then |
---|
578 | ftu_error_send_ack <= '1'; |
---|
579 | ftu_error_send_ready <= '0'; |
---|
580 | if (autosend_flag = '0') then |
---|
581 | state_send_ftu_error <= SFE_END; |
---|
582 | end if; |
---|
583 | state_init <= SEND_FTU_ERROR; |
---|
584 | end if; |
---|
585 | |
---|
586 | |
---|
587 | -- read dynamic data block and write it to ethernet |
---|
588 | when READ_DD_BLOCK => |
---|
589 | case state_read_dd_block is |
---|
590 | when READ_DD_BLOCK_START => |
---|
591 | dd_block_start <= '1'; |
---|
592 | dd_block_ready <= '0'; |
---|
593 | if (dd_block_start_ack = '1') then |
---|
594 | dd_block_start <= '0'; |
---|
595 | state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; |
---|
596 | end if; |
---|
597 | -- write on-time counter and tempertures to dd-block |
---|
598 | when READ_DD_BLOCK_WRITE_GENERAL => |
---|
599 | dd_write_general <= '1'; |
---|
600 | if (dd_write_general_started = '1') then |
---|
601 | dd_write_general <= '0'; |
---|
602 | state_read_dd_block <= READ_DD_BLOCK_WRITE; |
---|
603 | end if; |
---|
604 | -- write dd-block to ethernet when on-time counter and temperatures are ready |
---|
605 | when READ_DD_BLOCK_WRITE => |
---|
606 | if (dd_write_general_ready = '1') then |
---|
607 | data_package_type <= FTM_PACKAGE_TYPE_DD; |
---|
608 | data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end |
---|
609 | read_addr_state <= READ_FROM_DD_ADDR; |
---|
610 | local_sd_addr <= X"000"; -- start at address 0x000 |
---|
611 | local_write_length <= "00000" & DD_BLOCK_SIZE; |
---|
612 | state_read_dd_block <= READ_DD_BLOCK_END; |
---|
613 | next_state <= READ_DD_BLOCK; |
---|
614 | state_init <= WRITE_DATA; |
---|
615 | end if; |
---|
616 | when READ_DD_BLOCK_END => |
---|
617 | dd_block_ready <= '1'; |
---|
618 | if (internal_cmd = '1') then |
---|
619 | state_read_dd_block <= READ_DD_BLOCK_INTERN; |
---|
620 | else |
---|
621 | next_state_read_data <= RD_CMD; |
---|
622 | state_read_dd_block <= READ_DD_BLOCK_START; |
---|
623 | state_init <= READ_DATA; |
---|
624 | state_read_data <= RD_5; |
---|
625 | end if; |
---|
626 | when READ_DD_BLOCK_INTERN => |
---|
627 | if (dd_send = '0') then |
---|
628 | dd_send_ready <= '1'; |
---|
629 | dd_send_ack <= '0'; |
---|
630 | internal_cmd <= '0'; |
---|
631 | state_read_dd_block <= READ_DD_BLOCK_START; |
---|
632 | state_init <= MAIN; |
---|
633 | end if; |
---|
634 | end case; -- state_read_dd_block |
---|
635 | |
---|
636 | -- send FTU error message |
---|
637 | when SEND_FTU_ERROR => |
---|
638 | case state_send_ftu_error is |
---|
639 | when SFE_START => |
---|
640 | next_state <= SEND_FTU_ERROR; |
---|
641 | data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR; |
---|
642 | data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end |
---|
643 | read_addr_state <= READ_FTU_ERROR; |
---|
644 | local_sd_addr <= X"000"; |
---|
645 | local_write_length <= "00000" & FTU_ERROR_LENGTH; |
---|
646 | state_send_ftu_error <= SFE_END; |
---|
647 | state_init <= WRITE_DATA; |
---|
648 | when SFE_END => |
---|
649 | if (ftu_error_send = '0') then |
---|
650 | ftu_error_send_ack <= '0'; |
---|
651 | ftu_error_send_ready <= '1'; |
---|
652 | state_send_ftu_error <= SFE_START; |
---|
653 | state_init <= MAIN; |
---|
654 | end if; |
---|
655 | end case; |
---|
656 | |
---|
657 | |
---|
658 | -- read data from socket 0 |
---|
659 | when READ_DATA => |
---|
660 | case state_read_data is |
---|
661 | when RD_1 => |
---|
662 | par_addr <= W5300_S0_RX_RSR; |
---|
663 | state_init <= READ_REG; |
---|
664 | next_state <= READ_DATA; |
---|
665 | state_read_data <= RD_2; |
---|
666 | when RD_2 => |
---|
667 | socket_rx_received (31 downto 16) <= data_read; |
---|
668 | par_addr <= W5300_S0_RX_RSR + X"2"; |
---|
669 | state_init <= READ_REG; |
---|
670 | next_state <= READ_DATA; |
---|
671 | state_read_data <= RD_3; |
---|
672 | when RD_3 => |
---|
673 | socket_rx_received (15 downto 0) <= data_read; |
---|
674 | state_read_data <= RD_4; |
---|
675 | when RD_4 => |
---|
676 | if (socket_rx_received (16 downto 0) > ('0' & X"000")) then |
---|
677 | rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 |
---|
678 | state_read_data <= RD_5; |
---|
679 | else |
---|
680 | busy <= '0'; |
---|
681 | state_read_data <= RD_1; |
---|
682 | state_init <= MAIN; |
---|
683 | end if; |
---|
684 | when RD_5 => |
---|
685 | if (rx_packets_cnt > 0) then |
---|
686 | rx_packets_cnt <= rx_packets_cnt - '1'; |
---|
687 | par_addr <= W5300_S0_RX_FIFOR; |
---|
688 | state_init <= READ_REG; |
---|
689 | next_state <= READ_DATA; |
---|
690 | state_read_data <= next_state_read_data; |
---|
691 | else |
---|
692 | state_read_data <= RD_END; |
---|
693 | end if; |
---|
694 | |
---|
695 | when RD_END => |
---|
696 | state_read_data <= RD_1; |
---|
697 | if (new_config_flag = '1') then |
---|
698 | new_config_flag <= '0'; |
---|
699 | next_state <= CONFIG; |
---|
700 | else |
---|
701 | next_state <= MAIN; |
---|
702 | end if; |
---|
703 | par_addr <= W5300_S0_CR; |
---|
704 | par_data <= X"0040"; -- RECV |
---|
705 | state_init <= WRITE_REG; |
---|
706 | |
---|
707 | |
---|
708 | ------------------------- |
---|
709 | -- command handling |
---|
710 | ------------------------- |
---|
711 | |
---|
712 | -- read command (5 words) |
---|
713 | when RD_CMD => |
---|
714 | cmd_array (next_packet_data_cnt) <= data_read; |
---|
715 | next_packet_data_cnt <= next_packet_data_cnt + 1; |
---|
716 | -- look for command start |
---|
717 | if (next_packet_data_cnt = 0) then |
---|
718 | if (data_read /= CMD_START_DELIMITER) then |
---|
719 | next_packet_data_cnt <= 0; |
---|
720 | end if; |
---|
721 | end if; |
---|
722 | -- last command-word |
---|
723 | if (next_packet_data_cnt = 4) then |
---|
724 | next_packet_data_cnt <= 0; |
---|
725 | state_read_data <= RD_CMD_PARSE; |
---|
726 | else |
---|
727 | state_read_data <= RD_5; |
---|
728 | end if; |
---|
729 | |
---|
730 | -- process commands and parameters |
---|
731 | when RD_CMD_PARSE => |
---|
732 | case cmd_array (1) is |
---|
733 | |
---|
734 | when CMD_TLED => |
---|
735 | led_int <= NOT led_int; |
---|
736 | state_read_data <= RD_5; |
---|
737 | |
---|
738 | when CMD_START => |
---|
739 | case cmd_array (2) is |
---|
740 | -- start "normal" run |
---|
741 | when PAR_START_RUN => |
---|
742 | start_run <= '1'; |
---|
743 | start_run_param <= cmd_array (2); |
---|
744 | if (start_run_ack = '1') then |
---|
745 | start_run <= '0'; |
---|
746 | state_read_data <= RD_5; |
---|
747 | else |
---|
748 | state_init <= MAIN; |
---|
749 | end if; |
---|
750 | -- start run an take X events |
---|
751 | when PAR_START_X_EVNTS => |
---|
752 | next_state_read_data <= RD_X_EVNTS; |
---|
753 | wait_for_data_flag <= '1'; |
---|
754 | state_read_data <= RD_5; |
---|
755 | when others => |
---|
756 | state_read_data <= RD_5; |
---|
757 | end case; |
---|
758 | |
---|
759 | when CMD_STOP => |
---|
760 | stop_run <= '1'; |
---|
761 | if (stop_run_ack = '1') then |
---|
762 | stop_run <= '0'; |
---|
763 | state_read_data <= RD_5; |
---|
764 | else |
---|
765 | state_init <= MAIN; |
---|
766 | end if; |
---|
767 | |
---|
768 | when CMD_CRESET => |
---|
769 | crate_reset <= '1'; |
---|
770 | crate_reset_param <= cmd_array (2); |
---|
771 | if (crate_reset_ack = '1') then |
---|
772 | crate_reset <= '0'; |
---|
773 | state_read_data <= RD_5; |
---|
774 | else |
---|
775 | state_init <= MAIN; |
---|
776 | end if; |
---|
777 | |
---|
778 | when CMD_WRITE => |
---|
779 | case cmd_array (2) is |
---|
780 | -- write to address in static data block |
---|
781 | when PAR_WRITE_SD_ADDR => |
---|
782 | wait_for_data_flag <= '1'; |
---|
783 | next_state_read_data <= RD_WRITE_SD_ADDR; |
---|
784 | state_read_data <= RD_5; |
---|
785 | -- write static data block |
---|
786 | when PAR_WRITE_SD => |
---|
787 | wait_for_data_flag <= '1'; |
---|
788 | next_state_read_data <= RD_WRITE_SD_BLOCK; |
---|
789 | state_read_data <= RD_5; |
---|
790 | when others => |
---|
791 | state_read_data <= RD_5; |
---|
792 | end case; -- cmd_array (2) |
---|
793 | |
---|
794 | when CMD_READ => |
---|
795 | case cmd_array (2) is |
---|
796 | -- read from address in static data block |
---|
797 | when PAR_READ_SD_ADDR => |
---|
798 | wait_for_data_flag <= '1'; |
---|
799 | next_state_read_data <= RD_READ_SD_ADDR; |
---|
800 | state_read_data <= RD_5; |
---|
801 | -- read static data block |
---|
802 | when PAR_READ_SD => |
---|
803 | state_read_data <= RD_READ_SD_BLOCK; |
---|
804 | -- read dynamic data block |
---|
805 | when PAR_READ_DD => |
---|
806 | state_init <= READ_DD_BLOCK; |
---|
807 | state_read_data <= RD_5; |
---|
808 | when others => |
---|
809 | state_read_data <= RD_5; |
---|
810 | end case; -- cmd_array (2) |
---|
811 | |
---|
812 | when CMD_PING => |
---|
813 | state_ping <= PING_START; |
---|
814 | state_read_data <= RD_PING; |
---|
815 | |
---|
816 | when CMD_AUTOSEND => |
---|
817 | state_read_data <= RD_5; |
---|
818 | case cmd_array (2) is |
---|
819 | when PAR_AUTOSEND_EA => |
---|
820 | autosend_flag <= '1'; |
---|
821 | when PAR_AUTOSEND_DA => |
---|
822 | autosend_flag <= '0'; |
---|
823 | when others => |
---|
824 | null; |
---|
825 | end case; |
---|
826 | |
---|
827 | when others => |
---|
828 | state_read_data <= RD_5; |
---|
829 | |
---|
830 | end case; -- cmd_array (1) |
---|
831 | |
---|
832 | |
---|
833 | -- ping all FTUs and write FTU-list to ethernet |
---|
834 | when RD_PING => |
---|
835 | case state_ping is |
---|
836 | when PING_START => |
---|
837 | ping_ftu_start <= '1'; |
---|
838 | if (ping_ftu_started = '1') then |
---|
839 | ping_ftu_start <= '0'; |
---|
840 | state_ping <= PING_WAIT; |
---|
841 | else |
---|
842 | state_init <= MAIN; |
---|
843 | end if; |
---|
844 | when PING_WAIT => |
---|
845 | if (ping_ftu_ready = '1') then |
---|
846 | state_ping <= PING_WRITE_LIST; |
---|
847 | else |
---|
848 | state_init <= MAIN; |
---|
849 | end if; |
---|
850 | when PING_WRITE_LIST => |
---|
851 | state_read_data <= RD_5; |
---|
852 | data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST; |
---|
853 | data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end |
---|
854 | read_addr_state <= READ_FROM_FL_ADDR; |
---|
855 | local_sd_addr <= X"000"; --start at address 0x000 |
---|
856 | local_write_length <= "00000" & FL_BLOCK_SIZE; |
---|
857 | next_state_read_data <= RD_CMD; |
---|
858 | next_state <= READ_DATA; |
---|
859 | state_init <= WRITE_DATA; |
---|
860 | end case; |
---|
861 | |
---|
862 | -- read static data block and write it to ethernet |
---|
863 | when RD_READ_SD_BLOCK => |
---|
864 | data_package_type <= FTM_PACKAGE_TYPE_SD; |
---|
865 | data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end |
---|
866 | state_read_data <= RD_5; |
---|
867 | read_addr_state <= READ_FROM_SD_ADDR; |
---|
868 | local_sd_addr <= X"000"; -- start at address 0x000 |
---|
869 | local_write_length <= "00000" & SD_BLOCK_SIZE; |
---|
870 | next_state_read_data <= RD_CMD; |
---|
871 | next_state <= READ_DATA; |
---|
872 | state_init <= WRITE_DATA; |
---|
873 | |
---|
874 | -- read from address in static data ram and write data to ethernet |
---|
875 | when RD_READ_SD_ADDR => |
---|
876 | data_package_type <= FTM_PACKAGE_TYPE_SD_WORD; |
---|
877 | data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end |
---|
878 | state_read_data <= RD_5; |
---|
879 | read_addr_state <= READ_FROM_SD_ADDR; |
---|
880 | local_sd_addr <= data_read (11 downto 0); |
---|
881 | local_write_length <= '0' & X"0001"; -- one word will be written to ethernet |
---|
882 | next_state_read_data <= RD_CMD; |
---|
883 | wait_for_data_flag <= '0'; |
---|
884 | next_state <= READ_DATA; |
---|
885 | state_init <= WRITE_DATA; |
---|
886 | |
---|
887 | -- read static data block from ethernet and write it to static data ram |
---|
888 | when RD_WRITE_SD_BLOCK => |
---|
889 | state_read_data <= RD_5; |
---|
890 | next_packet_data_cnt <= next_packet_data_cnt + 1; |
---|
891 | local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12); |
---|
892 | local_sd_data <= data_read; |
---|
893 | next_state <= READ_DATA; |
---|
894 | state_init <= WRITE_TO_SD_ADDR; |
---|
895 | -- last word |
---|
896 | if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then |
---|
897 | next_packet_data_cnt <= 0; |
---|
898 | wait_for_data_flag <= '0'; |
---|
899 | new_config_flag <= '1'; |
---|
900 | next_state_read_data <= RD_CMD; |
---|
901 | end if; |
---|
902 | |
---|
903 | -- write to address in static data ram |
---|
904 | when RD_WRITE_SD_ADDR => |
---|
905 | state_read_data <= RD_5; |
---|
906 | next_packet_data_cnt <= next_packet_data_cnt + 1; |
---|
907 | if (next_packet_data_cnt = 0) then |
---|
908 | local_sd_addr <= data_read (11 downto 0); |
---|
909 | else |
---|
910 | local_sd_data <= data_read; |
---|
911 | next_packet_data_cnt <= 0; |
---|
912 | wait_for_data_flag <= '0'; |
---|
913 | new_config_flag <= '1'; |
---|
914 | next_state_read_data <= RD_CMD; |
---|
915 | next_state <= READ_DATA; |
---|
916 | state_init <= WRITE_TO_SD_ADDR; |
---|
917 | end if; |
---|
918 | |
---|
919 | -- read X events |
---|
920 | when RD_X_EVNTS => |
---|
921 | case state_rd_x_evnts is |
---|
922 | when RD_X_01 => |
---|
923 | start_run_num_events (31 downto 16) <= data_read; |
---|
924 | state_read_data <= RD_5; |
---|
925 | state_rd_x_evnts <= RD_X_02; |
---|
926 | when RD_X_02 => |
---|
927 | start_run_num_events (15 downto 0) <= data_read; |
---|
928 | start_run_param <= cmd_array (2); |
---|
929 | start_run <= '1'; |
---|
930 | wait_for_data_flag <= '0'; |
---|
931 | state_rd_x_evnts <= RD_X_03; |
---|
932 | when RD_X_03 => |
---|
933 | if (start_run_ack = '1') then |
---|
934 | start_run <= '0'; |
---|
935 | state_rd_x_evnts <= RD_X_01; |
---|
936 | next_state_read_data <= RD_CMD; |
---|
937 | state_read_data <= RD_5; |
---|
938 | else |
---|
939 | state_init <= MAIN; |
---|
940 | end if; |
---|
941 | end case; |
---|
942 | |
---|
943 | end case; -- state_read_data |
---|
944 | |
---|
945 | |
---|
946 | -- read FTU errors |
---|
947 | when READ_FTU_ERROR => |
---|
948 | state_init <= next_state; |
---|
949 | if (data_cnt = 0) then |
---|
950 | local_sd_data <= ftu_error_calls; |
---|
951 | else |
---|
952 | local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8)); |
---|
953 | end if; |
---|
954 | |
---|
955 | |
---|
956 | -- read from header modul |
---|
957 | when READ_FROM_HEADER_MODUL => |
---|
958 | state_init <= next_state; |
---|
959 | case header_cnt is |
---|
960 | when X"00" => |
---|
961 | local_sd_data <= data_package_type; |
---|
962 | when X"01" => |
---|
963 | local_sd_data <= data_package_length; |
---|
964 | when X"02" => |
---|
965 | local_sd_data <= header_current_state; |
---|
966 | when X"03" => |
---|
967 | local_sd_data <= header_board_id (63 DOWNTO 48); |
---|
968 | when X"04" => |
---|
969 | local_sd_data <= header_board_id (47 DOWNTO 32); |
---|
970 | when X"05" => |
---|
971 | local_sd_data <= header_board_id (31 DOWNTO 16); |
---|
972 | when X"06" => |
---|
973 | local_sd_data <= header_board_id (15 DOWNTO 0); |
---|
974 | when X"07" => |
---|
975 | local_sd_data <= header_firmware_id; |
---|
976 | when X"08" => |
---|
977 | local_sd_data <= header_trigger_counter (31 DOWNTO 16); |
---|
978 | when X"09" => |
---|
979 | local_sd_data <= header_trigger_counter (15 DOWNTO 0); |
---|
980 | when X"0A" => |
---|
981 | local_sd_data <= X"0000"; |
---|
982 | when X"0B" => |
---|
983 | local_sd_data <= header_timestamp_counter (47 DOWNTO 32); |
---|
984 | when X"0C" => |
---|
985 | local_sd_data <= header_timestamp_counter (31 DOWNTO 16); |
---|
986 | when X"0D" => |
---|
987 | local_sd_data <= header_timestamp_counter (15 DOWNTO 0); |
---|
988 | when others => |
---|
989 | null; |
---|
990 | end case; |
---|
991 | |
---|
992 | -- read from ftu list ram |
---|
993 | when READ_FROM_FL_ADDR => |
---|
994 | case state_read_fl is |
---|
995 | when READ_FL_START => |
---|
996 | if (fl_busy = '0') then |
---|
997 | fl_addr <= local_sd_addr; |
---|
998 | fl_read <= '1'; |
---|
999 | state_read_fl <= READ_FL_WAIT; |
---|
1000 | end if; |
---|
1001 | when READ_FL_WAIT => |
---|
1002 | if (fl_started = '1') then |
---|
1003 | state_read_fl <= READ_FL_END; |
---|
1004 | end if; |
---|
1005 | when READ_FL_END => |
---|
1006 | if (fl_ready = '1') then |
---|
1007 | local_sd_data <= fl_data_in; |
---|
1008 | fl_read <= '0'; |
---|
1009 | state_read_fl <= READ_FL_START; |
---|
1010 | state_init <= next_state; |
---|
1011 | end if; |
---|
1012 | end case; |
---|
1013 | |
---|
1014 | -- read from dynamic data block |
---|
1015 | when READ_FROM_DD_ADDR => |
---|
1016 | case state_read_dd is |
---|
1017 | when READ_DD_START => |
---|
1018 | if (dd_busy = '0') then |
---|
1019 | dd_addr <= local_sd_addr; |
---|
1020 | dd_read <= '1'; |
---|
1021 | state_read_dd <= READ_DD_WAIT; |
---|
1022 | end if; |
---|
1023 | when READ_DD_WAIT => |
---|
1024 | if (dd_started = '1') then |
---|
1025 | state_read_dd <= READ_DD_END; |
---|
1026 | end if; |
---|
1027 | when READ_DD_END => |
---|
1028 | if (dd_ready = '1') then |
---|
1029 | local_sd_data <= dd_data_in; |
---|
1030 | dd_read <= '0'; |
---|
1031 | state_read_dd <= READ_DD_START; |
---|
1032 | state_init <= next_state; |
---|
1033 | end if; |
---|
1034 | end case; |
---|
1035 | |
---|
1036 | -- read from static data block |
---|
1037 | when READ_FROM_SD_ADDR => |
---|
1038 | case state_read_sd is |
---|
1039 | when READ_SD_START => |
---|
1040 | if (sd_busy = '0') then |
---|
1041 | sd_addr <= local_sd_addr; |
---|
1042 | sd_read <= '1'; |
---|
1043 | state_read_sd <= READ_SD_WAIT; |
---|
1044 | end if; |
---|
1045 | when READ_SD_WAIT => |
---|
1046 | if (sd_started = '1') then |
---|
1047 | state_read_sd <= READ_SD_END; |
---|
1048 | end if; |
---|
1049 | when READ_SD_END => |
---|
1050 | if (sd_ready = '1') then |
---|
1051 | local_sd_data <= sd_data_in; |
---|
1052 | sd_read <= '0'; |
---|
1053 | state_read_sd <= READ_SD_START; |
---|
1054 | state_init <= next_state; |
---|
1055 | end if; |
---|
1056 | end case; |
---|
1057 | |
---|
1058 | -- write to static data block |
---|
1059 | when WRITE_TO_SD_ADDR => |
---|
1060 | case state_write_sd is |
---|
1061 | when WRITE_SD_START => |
---|
1062 | if (sd_busy = '0') then |
---|
1063 | sd_addr <= local_sd_addr; |
---|
1064 | sd_data_out <= local_sd_data; |
---|
1065 | sd_write <= '1'; |
---|
1066 | state_write_sd <= WRITE_SD_WAIT; |
---|
1067 | end if; |
---|
1068 | when WRITE_SD_WAIT => |
---|
1069 | if (sd_started = '1') then |
---|
1070 | sd_write <= '0'; |
---|
1071 | state_write_sd <= WRITE_SD_END; |
---|
1072 | end if; |
---|
1073 | when WRITE_SD_END => |
---|
1074 | if (sd_ready = '1') then |
---|
1075 | state_write_sd <= WRITE_SD_START; |
---|
1076 | state_init <= next_state; |
---|
1077 | end if; |
---|
1078 | end case; |
---|
1079 | |
---|
1080 | -- write to ethernet interface |
---|
1081 | when WRITE_DATA => |
---|
1082 | case state_write is |
---|
1083 | when WR_START => |
---|
1084 | state_write <= WR_LENGTH; |
---|
1085 | when WR_LENGTH => |
---|
1086 | local_socket_nr <= "000"; |
---|
1087 | next_state_tmp <= next_state; |
---|
1088 | -- Write Length: 2 := START and END of package |
---|
1089 | write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) |
---|
1090 | data_cnt <= 0; |
---|
1091 | header_cnt <= X"00"; |
---|
1092 | state_write <= WR_01; |
---|
1093 | -- Check FIFO Size |
---|
1094 | when WR_01 => |
---|
1095 | par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; |
---|
1096 | state_init <= READ_REG; |
---|
1097 | next_state <= WRITE_DATA; |
---|
1098 | state_write <= WR_02; |
---|
1099 | when WR_02 => |
---|
1100 | socket_tx_free (31 downto 16) <= data_read; |
---|
1101 | par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; |
---|
1102 | state_init <= READ_REG; |
---|
1103 | next_state <= WRITE_DATA; |
---|
1104 | state_write <= WR_03; |
---|
1105 | when WR_03 => |
---|
1106 | socket_tx_free (15 downto 0) <= data_read; |
---|
1107 | state_write <= WR_04; |
---|
1108 | when WR_04 => |
---|
1109 | if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then |
---|
1110 | state_write <= WR_01; |
---|
1111 | else |
---|
1112 | state_write <= WR_WRITE_START_DEL; |
---|
1113 | end if; |
---|
1114 | |
---|
1115 | -- write package start delimiter |
---|
1116 | when WR_WRITE_START_DEL => |
---|
1117 | par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; |
---|
1118 | par_data <= FTM_PACKAGE_START; |
---|
1119 | state_init <= WRITE_REG; |
---|
1120 | next_state <= WRITE_DATA; |
---|
1121 | state_write <= WR_GET_HEADER; |
---|
1122 | |
---|
1123 | -- get header data |
---|
1124 | when WR_GET_HEADER => |
---|
1125 | get_header <= '1'; |
---|
1126 | if (get_header_started = '1') then |
---|
1127 | get_header <= '0'; |
---|
1128 | state_write <= WR_GET_HEADER_WAIT; |
---|
1129 | end if; |
---|
1130 | |
---|
1131 | when WR_GET_HEADER_WAIT => |
---|
1132 | if (get_header_ready = '1') then |
---|
1133 | state_write <= WR_FIFO_HEADER; |
---|
1134 | end if; |
---|
1135 | |
---|
1136 | -- Fill FIFO |
---|
1137 | -- write header |
---|
1138 | when WR_FIFO_HEADER => |
---|
1139 | state_init <= READ_FROM_HEADER_MODUL; |
---|
1140 | next_state <= WRITE_DATA; |
---|
1141 | state_write <= WR_FIFO_HEADER_01; |
---|
1142 | |
---|
1143 | when WR_FIFO_HEADER_01 => |
---|
1144 | header_cnt <= header_cnt + 1; |
---|
1145 | if (header_cnt < FTM_HEADER_LENGTH) then |
---|
1146 | par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; |
---|
1147 | par_data <= local_sd_data; |
---|
1148 | state_init <= WRITE_REG; |
---|
1149 | next_state <= WRITE_DATA; |
---|
1150 | state_write <= WR_FIFO_HEADER; |
---|
1151 | else |
---|
1152 | if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then |
---|
1153 | state_write <= WR_SD_ADDR; |
---|
1154 | else |
---|
1155 | state_write <= WR_FIFO_DATA; |
---|
1156 | end if; |
---|
1157 | end if; |
---|
1158 | |
---|
1159 | -- write static data ram address (only for single address request) |
---|
1160 | when WR_SD_ADDR => |
---|
1161 | write_length_bytes <= write_length_bytes + 2; -- one extra word to write |
---|
1162 | par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; |
---|
1163 | par_data <= "0000" & local_sd_addr; |
---|
1164 | state_init <= WRITE_REG; |
---|
1165 | next_state <= WRITE_DATA; |
---|
1166 | state_write <= WR_FIFO_DATA; |
---|
1167 | |
---|
1168 | -- write data |
---|
1169 | when WR_FIFO_DATA => |
---|
1170 | state_init <= read_addr_state; |
---|
1171 | next_state <= WRITE_DATA; |
---|
1172 | state_write <= WR_FIFO_DATA_01; |
---|
1173 | |
---|
1174 | when WR_FIFO_DATA_01 => |
---|
1175 | data_cnt <= data_cnt + 1; |
---|
1176 | if (data_cnt < local_write_length) then |
---|
1177 | local_sd_addr <= local_sd_addr + 1; |
---|
1178 | par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; |
---|
1179 | par_data <= local_sd_data; |
---|
1180 | state_init <= WRITE_REG; |
---|
1181 | next_state <= WRITE_DATA; |
---|
1182 | state_write <= WR_FIFO_DATA; |
---|
1183 | else |
---|
1184 | state_write <= WR_WRITE_END_DEL; |
---|
1185 | end if; |
---|
1186 | |
---|
1187 | -- write package end delimiter |
---|
1188 | when WR_WRITE_END_DEL => |
---|
1189 | par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; |
---|
1190 | par_data <= FTM_PACKAGE_END; |
---|
1191 | state_init <= WRITE_REG; |
---|
1192 | next_state <= WRITE_DATA; |
---|
1193 | state_write <= WR_05; |
---|
1194 | |
---|
1195 | -- Send FIFO |
---|
1196 | when WR_05 => |
---|
1197 | par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; |
---|
1198 | par_data <= (0 => write_length_bytes (16), others => '0'); |
---|
1199 | state_init <= WRITE_REG; |
---|
1200 | state_write <= WR_06; |
---|
1201 | when WR_06 => |
---|
1202 | par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; |
---|
1203 | par_data <= write_length_bytes (15 downto 0); |
---|
1204 | state_init <= WRITE_REG; |
---|
1205 | state_write <= WR_07; |
---|
1206 | when WR_07 => |
---|
1207 | par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; |
---|
1208 | par_data <= X"0020"; -- Send |
---|
1209 | state_init <= WRITE_REG; |
---|
1210 | state_write <= WR_08; |
---|
1211 | when others => |
---|
1212 | state_init <= next_state_tmp; |
---|
1213 | state_write <= WR_START; |
---|
1214 | end case; |
---|
1215 | -- End WRITE_DATA |
---|
1216 | |
---|
1217 | when READ_REG => |
---|
1218 | case count is |
---|
1219 | when "000" => |
---|
1220 | cs <= '0'; |
---|
1221 | rd <= '0'; |
---|
1222 | wr <= '1'; |
---|
1223 | data <= (others => 'Z'); -- !!!!!!!!!! |
---|
1224 | count <= "001"; |
---|
1225 | addr <= par_addr; |
---|
1226 | when "001" => |
---|
1227 | count <= "010"; |
---|
1228 | when "010" => |
---|
1229 | count <= "100"; |
---|
1230 | when "100" => |
---|
1231 | data_read <= data; |
---|
1232 | count <= "110"; |
---|
1233 | when "110" => |
---|
1234 | count <= "111"; |
---|
1235 | when "111" => |
---|
1236 | cs <= '1'; |
---|
1237 | rd <= '1'; |
---|
1238 | count <= "000"; |
---|
1239 | state_init <= next_state; |
---|
1240 | when others => |
---|
1241 | null; |
---|
1242 | end case; |
---|
1243 | |
---|
1244 | when WRITE_REG => |
---|
1245 | case count is |
---|
1246 | when "000" => |
---|
1247 | cs <= '0'; |
---|
1248 | wr <= '0'; |
---|
1249 | rd <= '1'; |
---|
1250 | addr <= par_addr; |
---|
1251 | data <= par_data; |
---|
1252 | count <= "100"; |
---|
1253 | when "100" => |
---|
1254 | count <= "101"; |
---|
1255 | when "101" => |
---|
1256 | count <= "110"; |
---|
1257 | when "110" => |
---|
1258 | cs <= '1'; |
---|
1259 | wr <= '1'; |
---|
1260 | state_init <= next_state; |
---|
1261 | count <= "000"; |
---|
1262 | when others => |
---|
1263 | null; |
---|
1264 | end case; |
---|
1265 | |
---|
1266 | when others => |
---|
1267 | null; |
---|
1268 | end case; |
---|
1269 | end if; -- int_flag = '0' |
---|
1270 | |
---|
1271 | end if; -- rising_edge (clk) |
---|
1272 | |
---|
1273 | end process w5300_init_proc; |
---|
1274 | |
---|
1275 | end Behavioral; |
---|
1276 | |
---|