source: firmware/FTM/ethernet/w5300_modul.vhd@ 16318

Last change on this file since 16318 was 11485, checked in by weitzel, 14 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 52.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21LIBRARY IEEE;
22USE IEEE.STD_LOGIC_1164.all;
23USE IEEE.STD_LOGIC_ARITH.all;
24USE IEEE.STD_LOGIC_UNSIGNED.all;
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29-- Uncomment the following library declaration if instantiating
30-- any Xilinx primitives in this code.
31library UNISIM;
32use UNISIM.VComponents.all;
33
34ENTITY w5300_modul IS
35 PORT(
36 clk : IN std_logic;
37 wiz_reset : OUT std_logic := '1';
38 addr : OUT std_logic_vector (9 DOWNTO 0);
39 data : INOUT std_logic_vector (15 DOWNTO 0);
40 cs : OUT std_logic := '1';
41 wr : OUT std_logic := '1';
42 led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0');
43 rd : OUT std_logic := '1';
44 int : IN std_logic;
45 busy : OUT std_logic := '1';
46 new_config : OUT std_logic := '0';
47 config_started : IN std_logic;
48 config_started_ack : OUT std_logic := '0';
49 --
50 ping_ftu_start : OUT std_logic := '0';
51 ping_ftu_started : IN std_logic;
52 ping_ftu_ready : IN std_logic;
53 --
54 sd_addr : OUT std_logic_vector (11 DOWNTO 0);
55 sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
56 sd_data_in : IN std_logic_vector (15 DOWNTO 0);
57 sd_write : OUT std_logic := '0';
58 sd_read : OUT std_logic := '0';
59 sd_started : IN std_logic;
60 sd_ready : IN std_logic;
61 sd_busy : IN std_logic;
62 --
63 dd_block_start : OUT std_logic := '0';
64 dd_block_start_ack : IN std_logic;
65 dd_block_ready : OUT std_logic := '1';
66 dd_send : IN std_logic;
67 dd_send_ack : OUT std_logic := '1';
68 dd_send_ready : OUT std_logic := '1';
69 dd_addr : OUT std_logic_vector (11 DOWNTO 0);
70 dd_data_in : IN std_logic_vector (15 DOWNTO 0);
71 dd_read : OUT std_logic := '0';
72 dd_started : IN std_logic;
73 dd_ready : IN std_logic;
74 dd_busy : IN std_logic;
75 dd_write_general : OUT std_logic := '0';
76 dd_write_general_started : IN std_logic;
77 dd_write_general_ready : IN std_logic;
78 --
79 fl_addr : OUT std_logic_vector (11 DOWNTO 0);
80 fl_data_in : IN std_logic_vector (15 DOWNTO 0);
81 fl_read : OUT std_logic := '0';
82 fl_started : IN std_logic;
83 fl_ready : IN std_logic;
84 fl_busy : IN std_logic;
85 --
86 ftu_error_send : IN std_logic;
87 ftu_error_send_ack : OUT std_logic := '1';
88 ftu_error_send_ready : OUT std_logic := '1';
89 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
90 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
91 --
92 get_header : OUT std_logic := '0';
93 get_header_started : IN std_logic;
94 get_header_ready : IN std_logic;
95 header_board_id : IN std_logic_vector (63 DOWNTO 0);
96 header_firmware_id : IN std_logic_vector (15 DOWNTO 0);
97 header_trigger_counter : IN std_logic_vector (31 DOWNTO 0);
98 header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
99 header_current_state : IN std_logic_vector (15 DOWNTO 0);
100 --
101 start_run : OUT std_logic := '0';
102 start_run_ack : IN std_logic;
103 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
104 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0');
105 stop_run : OUT std_logic := '0';
106 stop_run_ack : IN std_logic;
107 crate_reset : OUT std_logic := '0';
108 crate_reset_ack : IN std_logic;
109 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
110 new_config_ftu : OUT std_logic := '0';
111 new_config_ftu_ack : IN std_logic;
112 new_config_ftu_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
113
114 );
115
116END w5300_modul ;
117
118architecture Behavioral of w5300_modul is
119
120 type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
121 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
122 SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR,
123 READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_DD_BLOCK, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL);
124 type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08,
125 WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL);
126 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
127 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
128 type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END);
129 type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END);
130 type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END);
131 type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END);
132 type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST);
133 type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END);
134 type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN);
135 type state_send_ftu_error_type is (SFE_START, SFE_END);
136 type state_rd_x_evnts_type is (RD_X_01, RD_X_02, RD_X_03);
137
138 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
139
140 signal par_addr : std_logic_vector (9 downto 0) := (others => '0');
141 signal par_data : std_logic_vector (15 downto 0) := (others => '0');
142 signal data_read : std_logic_vector (15 downto 0) := (others => '0');
143
144 signal state_init, next_state , next_state_tmp : state_init_type := RESET;
145 signal read_addr_state : state_init_type := RESET;
146 signal count : std_logic_vector (2 downto 0) := "000";
147 signal state_write : state_write_type := WR_START;
148 signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
149 signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
150 signal state_read_data : state_read_data_type := RD_1;
151 signal next_state_read_data : state_read_data_type := RD_CMD;
152 signal state_write_sd : state_write_sd_type := WRITE_SD_START;
153 signal state_read_sd : state_read_sd_type := READ_SD_START;
154 signal state_read_fl : state_read_fl_type := READ_FL_START;
155 signal state_ping : state_ping_type := PING_START;
156 signal state_read_dd : state_read_dd_type := READ_DD_START;
157 signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START;
158 signal state_send_ftu_error : state_send_ftu_error_type := SFE_START;
159 signal state_rd_x_evnts : state_rd_x_evnts_type := RD_X_01;
160
161 signal interrupt_ignore : std_logic := '1';
162 signal int_flag : std_logic := '0';
163
164 signal zaehler : std_logic_vector (19 downto 0) := (others => '0');
165 signal data_cnt : integer := 0;
166 signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00";
167 signal socket_cnt : std_logic_vector (2 downto 0) := "000";
168
169 signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
170 signal write_length_bytes : std_logic_vector (16 downto 0);
171
172 signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
173 signal chk_recv_cntr : integer range 0 to 10000 := 0;
174
175 signal next_packet_data_cnt : integer range 0 to 4095 := 0;
176 signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000";
177 signal new_config_flag : std_logic := '0';
178
179 signal local_write_length : std_logic_vector (16 downto 0);
180 signal local_socket_nr : std_logic_vector (2 downto 0);
181
182 type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0);
183 signal cmd_array : cmd_array_type;
184 signal internal_cmd : std_logic := '0';
185 signal wait_for_data_flag : std_logic := '0';
186
187 signal autosend_flag : std_logic := '1';
188
189 -- -- --
190 signal led_int : std_logic_vector (7 downto 0) := X"00";
191 signal led_cnt : integer range 0 to 2**22 := 0;
192 -- -- --
193
194 signal local_sd_addr : std_logic_vector (11 downto 0);
195 signal local_sd_data : std_logic_vector (15 downto 0);
196
197 signal data_package_type : std_logic_vector (15 downto 0) := X"0000";
198 signal data_package_length : std_logic_vector (15 downto 0) := X"0000";
199
200
201begin
202
203 --synthesis translate_off
204 RST_TIME <= X"00120";
205 --synthesis translate_on
206
207
208 w5300_init_proc : process (clk, int)
209 begin
210
211 if rising_edge (clk) then
212
213 -- -- --
214 led <= led_int;
215 -- -- --
216
217 -- Interrupt low
218 if (int = '0') and (interrupt_ignore = '0') then
219 case state_interrupt_1 is
220 when IR1_01 =>
221 int_flag <= '1';
222 busy <= '1';
223 state_interrupt_1 <= IR1_02;
224 when IR1_02 =>
225 state_interrupt_1 <= IR1_03;
226 when IR1_03 =>
227 state_init <= INTERRUPT;
228 socket_cnt <= "000";
229 zaehler <= X"00000";
230 count <= "000";
231 int_flag <= '0';
232 interrupt_ignore <= '1';
233 state_interrupt_1 <= IR1_04;
234 when others =>
235 null;
236 end case;
237 end if; -- int = '0'
238
239 if int_flag = '0' then
240 case state_init is
241 -- Interrupt
242 when INTERRUPT =>
243 case state_interrupt_2 is
244 when IR2_01 =>
245 par_addr <= W5300_IR;
246 state_init <= READ_REG;
247 next_state <= INTERRUPT;
248 state_interrupt_2 <= IR2_02;
249 when IR2_02 =>
250 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
251 state_interrupt_2 <= IR2_03;
252 else
253 socket_cnt <= socket_cnt + 1;
254 if (socket_cnt = W5300_LAST_SOCKET) then
255 state_interrupt_2 <= IR2_06;
256 else
257 state_interrupt_2 <= IR2_02;
258 end if;
259 end if;
260 when IR2_03 =>
261 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
262 state_init <= READ_REG;
263 next_state <= INTERRUPT;
264 state_interrupt_2 <= IR2_04;
265 when IR2_04 =>
266 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
267 par_data <= data_read; -- clear Interrupts
268 state_init <= WRITE_REG;
269 next_state <= INTERRUPT;
270 state_interrupt_2 <= IR2_05;
271 when IR2_05 =>
272 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
273 par_data <= X"0010"; -- CLOSE
274 state_init <= WRITE_REG;
275 next_state <= INTERRUPT;
276 socket_cnt <= socket_cnt + 1;
277 if (socket_cnt = W5300_LAST_SOCKET) then
278 state_interrupt_2 <= IR2_06;
279 else
280 state_interrupt_2 <= IR2_01;
281 end if;
282
283 when IR2_06 =>
284 state_interrupt_1 <= IR1_01;
285 state_interrupt_2 <= IR2_01;
286 socket_cnt <= "000";
287 state_init <= RESET;
288 end case;
289
290 -- reset W5300
291 when RESET =>
292 busy <= '1';
293 zaehler <= zaehler + 1;
294 wiz_reset <= '0';
295 if (zaehler >= X"00064") then -- wait 2µs
296 wiz_reset <= '1';
297 end if;
298 if (zaehler = RST_TIME) then -- wait 10ms
299 zaehler <= X"00000";
300 socket_cnt <= "000";
301 count <= "000";
302 interrupt_ignore <= '0';
303 rd <= '1';
304 wr <= '1';
305 cs <= '1';
306 -- reset states
307 state_write <= WR_START;
308 state_init <= INIT;
309 state_read_data <= RD_1;
310 next_state_read_data <= RD_CMD;
311 state_write_sd <= WRITE_SD_START;
312 state_read_sd <= READ_SD_START;
313 state_read_fl <= READ_FL_START;
314 state_ping <= PING_START;
315 state_read_dd <= READ_DD_START;
316 state_read_dd_block <= READ_DD_BLOCK_START;
317 state_send_ftu_error <= SFE_START;
318 -- reset output signals
319 new_config <= '0';
320 config_started_ack <= '1';
321 ping_ftu_start <= '0';
322 sd_write <= '0';
323 sd_read <= '0';
324 dd_block_start <= '0';
325 dd_block_ready <= '1';
326 dd_send_ack <= '1';
327 dd_send_ready <= '1';
328 dd_read <= '0';
329 dd_write_general <= '0';
330 fl_read <= '0';
331 ftu_error_send_ack <= '1';
332 ftu_error_send_ready <= '1';
333 --
334 start_run <= '0';
335 stop_run <= '0';
336 crate_reset <= '0';
337 new_config_ftu <= '0';
338 -- set internal signals
339 new_config_flag <= '0';
340 chk_recv_cntr <= 0;
341 next_packet_data_cnt <= 0;
342 internal_cmd <= '0';
343 -- -- --
344 led_int <= X"00";
345 -- -- --
346 end if;
347
348 -- Init
349 when INIT =>
350 par_addr <= W5300_MR;
351 par_data <= X"0000";
352 state_init <= WRITE_REG;
353 next_state <= IM;
354
355 -- Interrupt Mask
356 when IM =>
357 par_addr <= W5300_IMR;
358 par_data <= X"00FF"; -- S0-S7 Interrupts
359 state_init <= WRITE_REG;
360 next_state <= MT;
361
362 -- Memory Type
363 when MT =>
364 par_addr <= W5300_MTYPER;
365 par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer
366 state_init <= WRITE_REG;
367 next_state <= STX;
368
369 -- Socket TX Memory Size
370 when STX =>
371 par_data <= X"4000"; -- 64K TX for socket 0, others 0
372
373 par_addr <= W5300_TMS01R;
374 state_init <= WRITE_REG;
375 next_state <= STX1;
376 when STX1 =>
377 par_data <= X"0000";
378 par_addr <= W5300_TMS23R;
379 state_init <= WRITE_REG;
380 next_state <= STX2;
381 when STX2 =>
382 par_addr <= W5300_TMS45R;
383 state_init <= WRITE_REG;
384 next_state <= STX3;
385 when STX3 =>
386 par_addr <= W5300_TMS67R;
387 state_init <= WRITE_REG;
388 next_state <= SRX;
389
390 -- Socket RX Memory Size
391 when SRX =>
392 par_data <= X"4000"; -- 64K RX for socket 0, others 0
393
394 par_addr <= W5300_RMS01R;
395 state_init <= WRITE_REG;
396 next_state <= SRX1;
397 when SRX1 =>
398 par_data <= X"0000";
399 par_addr <= W5300_RMS23R;
400 state_init <= WRITE_REG;
401 next_state <= SRX2;
402 when SRX2 =>
403 par_addr <= W5300_RMS45R;
404 state_init <= WRITE_REG;
405 next_state <= SRX3;
406 when SRX3 =>
407 par_addr <= W5300_RMS67R;
408 state_init <= WRITE_REG;
409 next_state <= MAC;
410
411 -- MAC
412 when MAC =>
413 par_addr <= W5300_SHAR;
414 par_data <= MAC_ADDRESS (0);
415 state_init <= WRITE_REG;
416 next_state <= MAC1;
417 when MAC1 =>
418 par_addr <= W5300_SHAR + 2;
419 par_data <= MAC_ADDRESS (1);
420 state_init <= WRITE_REG;
421 next_state <= MAC2;
422 when MAC2 =>
423 par_addr <= W5300_SHAR + 4;
424 par_data <= MAC_ADDRESS (2);
425 state_init <= WRITE_REG;
426 next_state <= GW;
427
428 -- Gateway
429 when GW =>
430 par_addr <= W5300_GAR;
431 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8);
432 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8);
433 state_init <= WRITE_REG;
434 next_state <= GW1;
435 when GW1 =>
436 par_addr <= W5300_GAR + 2;
437 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8);
438 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8);
439 state_init <= WRITE_REG;
440 next_state <= SNM;
441
442 -- Subnet Mask
443 when SNM =>
444 par_addr <= W5300_SUBR;
445 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8);
446 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8);
447 state_init <= WRITE_REG;
448 next_state <= SNM1;
449 when SNM1 =>
450 par_addr <= W5300_SUBR + 2;
451 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8);
452 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8);
453 state_init <= WRITE_REG;
454 next_state <= IP;
455 -- Own IP-Address
456 when IP =>
457 par_addr <= W5300_SIPR;
458 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8);
459 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8);
460 state_init <= WRITE_REG;
461 next_state <= IP1;
462 when IP1 =>
463 par_addr <= W5300_SIPR + 2;
464 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8);
465 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8);
466 state_init <= WRITE_REG;
467 next_state <= SI;
468 -- Socket Init
469 when SI =>
470 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
471 par_data <= X"0101"; -- 0x0101: ALIGN, TCP
472 state_init <= WRITE_REG;
473 next_state <= SI0;
474 -- keep alive
475 when SI0 =>
476 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC;
477 par_data <= X"0C00"; -- 12 * 5s = 60s
478 state_init <= WRITE_REG;
479 next_state <= SI1;
480 -- Sx Interrupt Mask
481 when SI1 =>
482 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
483 par_data <= X"000A"; -- TIMEOUT, DISCON
484 state_init <= WRITE_REG;
485 next_state <= SI2;
486 when SI2 =>
487 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
488 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
489 state_init <= WRITE_REG;
490 next_state <= SI3;
491 when SI3 =>
492 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
493 par_data <= X"0001"; -- OPEN
494 state_init <= WRITE_REG;
495 next_state <= SI4;
496 when SI4 =>
497 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
498 state_init <= READ_REG;
499 next_state <= SI5;
500 when SI5 =>
501 if (data_read (7 downto 0) = X"13") then -- is open?
502 state_init <= SI6;
503 else
504 state_init <= SI4;
505 end if;
506 when SI6 =>
507 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
508 par_data <= X"0002"; -- LISTEN
509 state_init <= WRITE_REG;
510 socket_cnt <= socket_cnt + 1;
511 if (socket_cnt = W5300_LAST_SOCKET) then
512 socket_cnt <= "000";
513 next_state <= ESTABLISH; -- All Sockets open
514 else
515 next_state <= SI; -- Next Socket
516 end if;
517 -- End Socket Init
518
519 when ESTABLISH =>
520 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
521 state_init <= READ_REG;
522 next_state <= EST1;
523 when EST1 =>
524 case data_read (7 downto 0) is
525 when X"17" => -- established
526 if (socket_cnt = W5300_LAST_SOCKET) then
527 socket_cnt <= "000";
528 busy <= '0';
529 state_init <= MAIN;
530 -- -- --
531 config_started_ack <= '0';
532 dd_block_ready <= '0';
533 dd_send_ack <= '0';
534 dd_send_ready <= '0';
535 ftu_error_send_ack <= '0';
536 ftu_error_send_ready <= '0';
537 led_int <= X"00";
538 wait_for_data_flag <= '0';
539 -- -- --
540 else
541 socket_cnt <= socket_cnt + 1;
542 state_init <= ESTABLISH;
543 end if;
544 when others =>
545 state_init <= ESTABLISH;
546 -- -- --
547 -- Just for fun...
548 if (led_cnt = 1100000) then
549 if (led_int = X"00") then
550 led_int <= X"18";
551 else
552 led_int (7 downto 4) <= led_int (6 downto 4) & '0';
553 led_int (3 downto 0) <= '0' & led_int (3 downto 1);
554 end if;
555 led_cnt <= 0;
556 else
557 led_cnt <= led_cnt + 1;
558 end if;
559 -- -- --
560 end case;
561
562 when CONFIG =>
563 new_config <= '1';
564 config_started_ack <= '0';
565 state_init <= MAIN;
566
567 -- main "loop"
568 when MAIN =>
569 if (config_started = '1') then
570 new_config <= '0';
571 config_started_ack <= '1';
572 end if;
573 chk_recv_cntr <= chk_recv_cntr + 1;
574 if (chk_recv_cntr = 1000) then
575 chk_recv_cntr <= 0;
576 state_init <= READ_DATA;
577 busy <= '1';
578 elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then
579 internal_cmd <= '1';
580 dd_send_ack <= '1';
581 dd_send_ready <= '0';
582 if (autosend_flag = '0') then
583 state_read_dd_block <= READ_DD_BLOCK_END;
584 end if;
585 state_init <= READ_DD_BLOCK;
586 elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then
587 ftu_error_send_ack <= '1';
588 ftu_error_send_ready <= '0';
589 if (autosend_flag = '0') then
590 state_send_ftu_error <= SFE_END;
591 end if;
592 state_init <= SEND_FTU_ERROR;
593 end if;
594
595
596 -- read dynamic data block and write it to ethernet
597 when READ_DD_BLOCK =>
598 case state_read_dd_block is
599 when READ_DD_BLOCK_START =>
600 dd_block_start <= '1';
601 dd_block_ready <= '0';
602 if (dd_block_start_ack = '1') then
603 dd_block_start <= '0';
604 state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL;
605 end if;
606 -- write on-time counter and tempertures to dd-block
607 when READ_DD_BLOCK_WRITE_GENERAL =>
608 dd_write_general <= '1';
609 if (dd_write_general_started = '1') then
610 dd_write_general <= '0';
611 state_read_dd_block <= READ_DD_BLOCK_WRITE;
612 end if;
613 -- write dd-block to ethernet when on-time counter and temperatures are ready
614 when READ_DD_BLOCK_WRITE =>
615 if (dd_write_general_ready = '1') then
616 data_package_type <= FTM_PACKAGE_TYPE_DD;
617 data_package_length <= X"0" & (DD_BLOCK_SIZE + 1); -- +1 := package end
618 read_addr_state <= READ_FROM_DD_ADDR;
619 local_sd_addr <= X"000"; -- start at address 0x000
620 local_write_length <= "00000" & DD_BLOCK_SIZE;
621 state_read_dd_block <= READ_DD_BLOCK_END;
622 next_state <= READ_DD_BLOCK;
623 state_init <= WRITE_DATA;
624 end if;
625 when READ_DD_BLOCK_END =>
626 dd_block_ready <= '1';
627 if (internal_cmd = '1') then
628 state_read_dd_block <= READ_DD_BLOCK_INTERN;
629 else
630 next_state_read_data <= RD_CMD;
631 state_read_dd_block <= READ_DD_BLOCK_START;
632 state_init <= READ_DATA;
633 state_read_data <= RD_5;
634 end if;
635 when READ_DD_BLOCK_INTERN =>
636 if (dd_send = '0') then
637 dd_send_ready <= '1';
638 dd_send_ack <= '0';
639 internal_cmd <= '0';
640 state_read_dd_block <= READ_DD_BLOCK_START;
641 state_init <= MAIN;
642 end if;
643 end case; -- state_read_dd_block
644
645 -- send FTU error message
646 when SEND_FTU_ERROR =>
647 case state_send_ftu_error is
648 when SFE_START =>
649 next_state <= SEND_FTU_ERROR;
650 data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR;
651 data_package_length <= X"0" & (FTU_ERROR_LENGTH + 1); -- +1 := package end
652 read_addr_state <= READ_FTU_ERROR;
653 local_sd_addr <= X"000";
654 local_write_length <= "00000" & FTU_ERROR_LENGTH;
655 state_send_ftu_error <= SFE_END;
656 state_init <= WRITE_DATA;
657 when SFE_END =>
658 if (ftu_error_send = '0') then
659 ftu_error_send_ack <= '0';
660 ftu_error_send_ready <= '1';
661 state_send_ftu_error <= SFE_START;
662 state_init <= MAIN;
663 end if;
664 end case;
665
666
667 -- read data from socket 0
668 when READ_DATA =>
669 case state_read_data is
670 when RD_1 =>
671 par_addr <= W5300_S0_RX_RSR;
672 state_init <= READ_REG;
673 next_state <= READ_DATA;
674 state_read_data <= RD_2;
675 when RD_2 =>
676 socket_rx_received (31 downto 16) <= data_read;
677 par_addr <= W5300_S0_RX_RSR + X"2";
678 state_init <= READ_REG;
679 next_state <= READ_DATA;
680 state_read_data <= RD_3;
681 when RD_3 =>
682 socket_rx_received (15 downto 0) <= data_read;
683 state_read_data <= RD_4;
684 when RD_4 =>
685 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
686 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
687 state_read_data <= RD_5;
688 else
689 busy <= '0';
690 state_read_data <= RD_1;
691 state_init <= MAIN;
692 end if;
693 when RD_5 =>
694 if (rx_packets_cnt > 0) then
695 rx_packets_cnt <= rx_packets_cnt - '1';
696 par_addr <= W5300_S0_RX_FIFOR;
697 state_init <= READ_REG;
698 next_state <= READ_DATA;
699 state_read_data <= next_state_read_data;
700 else
701 state_read_data <= RD_END;
702 end if;
703
704 when RD_END =>
705 state_read_data <= RD_1;
706 if (new_config_flag = '1') then
707 new_config_flag <= '0';
708 next_state <= CONFIG;
709 else
710 next_state <= MAIN;
711 end if;
712 par_addr <= W5300_S0_CR;
713 par_data <= X"0040"; -- RECV
714 state_init <= WRITE_REG;
715
716
717 -------------------------
718 -- command handling
719 -------------------------
720
721 -- read command (5 words)
722 when RD_CMD =>
723 cmd_array (next_packet_data_cnt) <= data_read;
724 next_packet_data_cnt <= next_packet_data_cnt + 1;
725 -- look for command start
726 if (next_packet_data_cnt = 0) then
727 if (data_read /= CMD_START_DELIMITER) then
728 next_packet_data_cnt <= 0;
729 end if;
730 end if;
731 -- last command-word
732 if (next_packet_data_cnt = 4) then
733 next_packet_data_cnt <= 0;
734 state_read_data <= RD_CMD_PARSE;
735 else
736 state_read_data <= RD_5;
737 end if;
738
739 -- process commands and parameters
740 when RD_CMD_PARSE =>
741 case cmd_array (1) is
742
743 when CMD_TLED =>
744 led_int <= NOT led_int;
745 state_read_data <= RD_5;
746
747 when CMD_START =>
748 case cmd_array (2) is
749 -- start "normal" run
750 when PAR_START_RUN =>
751 start_run <= '1';
752 start_run_param <= cmd_array (2);
753 if (start_run_ack = '1') then
754 start_run <= '0';
755 state_read_data <= RD_5;
756 else
757 state_init <= MAIN;
758 end if;
759 -- start run an take X events
760 when PAR_START_X_EVNTS =>
761 next_state_read_data <= RD_X_EVNTS;
762 wait_for_data_flag <= '1';
763 state_read_data <= RD_5;
764 when others =>
765 state_read_data <= RD_5;
766 end case;
767
768 when CMD_STOP =>
769 stop_run <= '1';
770 if (stop_run_ack = '1') then
771 stop_run <= '0';
772 state_read_data <= RD_5;
773 else
774 state_init <= MAIN;
775 end if;
776
777 when CMD_CRESET =>
778 crate_reset <= '1';
779 crate_reset_param <= cmd_array (2);
780-- led_int <= cmd_array (2) (7 downto 0);
781 if (crate_reset_ack = '1') then
782 crate_reset <= '0';
783 state_read_data <= RD_5;
784 else
785 state_init <= MAIN;
786 end if;
787
788 when CMD_CONFIG_FTU =>
789 new_config_ftu <= '1';
790 new_config_ftu_param <= cmd_array (2);
791-- led_int <= cmd_array (2) (7 downto 0);
792 if (new_config_ftu_ack = '1') then
793 new_config_ftu <= '0';
794 state_read_data <= RD_5;
795 else
796 state_init <= MAIN;
797 end if;
798
799 when CMD_WRITE =>
800 case cmd_array (2) is
801 -- write to address in static data block
802 when PAR_WRITE_SD_ADDR =>
803 wait_for_data_flag <= '1';
804 next_state_read_data <= RD_WRITE_SD_ADDR;
805 state_read_data <= RD_5;
806 -- write static data block
807 when PAR_WRITE_SD =>
808 wait_for_data_flag <= '1';
809 next_state_read_data <= RD_WRITE_SD_BLOCK;
810 state_read_data <= RD_5;
811 when others =>
812 state_read_data <= RD_5;
813 end case; -- cmd_array (2)
814
815 when CMD_READ =>
816 case cmd_array (2) is
817 -- read from address in static data block
818 when PAR_READ_SD_ADDR =>
819 wait_for_data_flag <= '1';
820 next_state_read_data <= RD_READ_SD_ADDR;
821 state_read_data <= RD_5;
822 -- read static data block
823 when PAR_READ_SD =>
824 state_read_data <= RD_READ_SD_BLOCK;
825 -- read dynamic data block
826 when PAR_READ_DD =>
827 state_init <= READ_DD_BLOCK;
828 state_read_data <= RD_5;
829 when others =>
830 state_read_data <= RD_5;
831 end case; -- cmd_array (2)
832
833 when CMD_PING =>
834 state_ping <= PING_START;
835 state_read_data <= RD_PING;
836
837 when CMD_AUTOSEND =>
838 state_read_data <= RD_5;
839 case cmd_array (2) is
840 when PAR_AUTOSEND_EA =>
841 autosend_flag <= '1';
842 when PAR_AUTOSEND_DA =>
843 autosend_flag <= '0';
844 when others =>
845 null;
846 end case;
847
848 when others =>
849 state_read_data <= RD_5;
850
851 end case; -- cmd_array (1)
852
853
854 -- ping all FTUs and write FTU-list to ethernet
855 when RD_PING =>
856 case state_ping is
857 when PING_START =>
858 ping_ftu_start <= '1';
859 if (ping_ftu_started = '1') then
860 ping_ftu_start <= '0';
861 state_ping <= PING_WAIT;
862 else
863 state_init <= MAIN;
864 end if;
865 when PING_WAIT =>
866 if (ping_ftu_ready = '1') then
867 state_ping <= PING_WRITE_LIST;
868 else
869 state_init <= MAIN;
870 end if;
871 when PING_WRITE_LIST =>
872 state_read_data <= RD_5;
873 data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST;
874 data_package_length <= X"0" & (FL_BLOCK_SIZE + 1); -- +1 := package end
875 read_addr_state <= READ_FROM_FL_ADDR;
876 local_sd_addr <= X"000"; --start at address 0x000
877 local_write_length <= "00000" & FL_BLOCK_SIZE;
878 next_state_read_data <= RD_CMD;
879 next_state <= READ_DATA;
880 state_init <= WRITE_DATA;
881 end case;
882
883 -- read static data block and write it to ethernet
884 when RD_READ_SD_BLOCK =>
885 data_package_type <= FTM_PACKAGE_TYPE_SD;
886 data_package_length <= X"0" & (SD_BLOCK_SIZE + 1); -- +1 := package end
887 state_read_data <= RD_5;
888 read_addr_state <= READ_FROM_SD_ADDR;
889 local_sd_addr <= X"000"; -- start at address 0x000
890 local_write_length <= "00000" & SD_BLOCK_SIZE;
891 next_state_read_data <= RD_CMD;
892 next_state <= READ_DATA;
893 state_init <= WRITE_DATA;
894
895 -- read from address in static data ram and write data to ethernet
896 when RD_READ_SD_ADDR =>
897 data_package_type <= FTM_PACKAGE_TYPE_SD_WORD;
898 data_package_length <= X"0" & (SD_SINGLE_WORD_SIZE + 1); -- +1 := package end
899 state_read_data <= RD_5;
900 read_addr_state <= READ_FROM_SD_ADDR;
901 local_sd_addr <= data_read (11 downto 0);
902 local_write_length <= '0' & X"0001"; -- one word will be written to ethernet
903 next_state_read_data <= RD_CMD;
904 wait_for_data_flag <= '0';
905 next_state <= READ_DATA;
906 state_init <= WRITE_DATA;
907
908 -- read static data block from ethernet and write it to static data ram
909 when RD_WRITE_SD_BLOCK =>
910 state_read_data <= RD_5;
911 next_packet_data_cnt <= next_packet_data_cnt + 1;
912 local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12);
913 local_sd_data <= data_read;
914 next_state <= READ_DATA;
915 state_init <= WRITE_TO_SD_ADDR;
916 -- last word
917 if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then
918 next_packet_data_cnt <= 0;
919 wait_for_data_flag <= '0';
920 next_state_read_data <= RD_CMD;
921 new_config_flag <= '1';
922 end if;
923
924 -- write to address in static data ram
925 when RD_WRITE_SD_ADDR =>
926 state_read_data <= RD_5;
927 next_packet_data_cnt <= next_packet_data_cnt + 1;
928 if (next_packet_data_cnt = 0) then
929 local_sd_addr <= data_read (11 downto 0);
930 else
931 local_sd_data <= data_read;
932 next_packet_data_cnt <= 0;
933 wait_for_data_flag <= '0';
934 new_config_flag <= '1';
935 next_state_read_data <= RD_CMD;
936 next_state <= READ_DATA;
937 state_init <= WRITE_TO_SD_ADDR;
938 end if;
939
940 -- read X events
941 when RD_X_EVNTS =>
942 case state_rd_x_evnts is
943 when RD_X_01 =>
944 start_run_num_events (31 downto 16) <= data_read;
945 state_read_data <= RD_5;
946 state_rd_x_evnts <= RD_X_02;
947 when RD_X_02 =>
948 start_run_num_events (15 downto 0) <= data_read;
949 start_run_param <= cmd_array (2);
950 start_run <= '1';
951 wait_for_data_flag <= '0';
952 state_rd_x_evnts <= RD_X_03;
953 when RD_X_03 =>
954 if (start_run_ack = '1') then
955 start_run <= '0';
956 state_rd_x_evnts <= RD_X_01;
957 next_state_read_data <= RD_CMD;
958 state_read_data <= RD_5;
959 else
960 state_init <= MAIN;
961 end if;
962 end case;
963
964 end case; -- state_read_data
965
966
967 -- read FTU errors
968 when READ_FTU_ERROR =>
969 state_init <= next_state;
970 if (data_cnt = 0) then
971 local_sd_data <= ftu_error_calls;
972 else
973 local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8));
974 end if;
975
976
977 -- read from header modul
978 when READ_FROM_HEADER_MODUL =>
979 state_init <= next_state;
980 case header_cnt is
981 when X"00" =>
982 local_sd_data <= data_package_type;
983 when X"01" =>
984 local_sd_data <= data_package_length;
985 when X"02" =>
986 local_sd_data <= header_current_state;
987 when X"03" =>
988 local_sd_data <= header_board_id (63 DOWNTO 48);
989 when X"04" =>
990 local_sd_data <= header_board_id (47 DOWNTO 32);
991 when X"05" =>
992 local_sd_data <= header_board_id (31 DOWNTO 16);
993 when X"06" =>
994 local_sd_data <= header_board_id (15 DOWNTO 0);
995 when X"07" =>
996 local_sd_data <= header_firmware_id;
997 when X"08" =>
998 local_sd_data <= header_trigger_counter (31 DOWNTO 16);
999 when X"09" =>
1000 local_sd_data <= header_trigger_counter (15 DOWNTO 0);
1001 when X"0A" =>
1002 local_sd_data <= X"0000";
1003 when X"0B" =>
1004 local_sd_data <= header_timestamp_counter (47 DOWNTO 32);
1005 when X"0C" =>
1006 local_sd_data <= header_timestamp_counter (31 DOWNTO 16);
1007 when X"0D" =>
1008 local_sd_data <= header_timestamp_counter (15 DOWNTO 0);
1009 when others =>
1010 null;
1011 end case;
1012
1013 -- read from ftu list ram
1014 when READ_FROM_FL_ADDR =>
1015 case state_read_fl is
1016 when READ_FL_START =>
1017 if (fl_busy = '0') then
1018 fl_addr <= local_sd_addr;
1019 fl_read <= '1';
1020 state_read_fl <= READ_FL_WAIT;
1021 end if;
1022 when READ_FL_WAIT =>
1023 if (fl_started = '1') then
1024 state_read_fl <= READ_FL_END;
1025 end if;
1026 when READ_FL_END =>
1027 if (fl_ready = '1') then
1028 local_sd_data <= fl_data_in;
1029 fl_read <= '0';
1030 state_read_fl <= READ_FL_START;
1031 state_init <= next_state;
1032 end if;
1033 end case;
1034
1035 -- read from dynamic data block
1036 when READ_FROM_DD_ADDR =>
1037 case state_read_dd is
1038 when READ_DD_START =>
1039 if (dd_busy = '0') then
1040 dd_addr <= local_sd_addr;
1041 dd_read <= '1';
1042 state_read_dd <= READ_DD_WAIT;
1043 end if;
1044 when READ_DD_WAIT =>
1045 if (dd_started = '1') then
1046 state_read_dd <= READ_DD_END;
1047 end if;
1048 when READ_DD_END =>
1049 if (dd_ready = '1') then
1050 local_sd_data <= dd_data_in;
1051 dd_read <= '0';
1052 state_read_dd <= READ_DD_START;
1053 state_init <= next_state;
1054 end if;
1055 end case;
1056
1057 -- read from static data block
1058 when READ_FROM_SD_ADDR =>
1059 case state_read_sd is
1060 when READ_SD_START =>
1061 if (sd_busy = '0') then
1062 sd_addr <= local_sd_addr;
1063 sd_read <= '1';
1064 state_read_sd <= READ_SD_WAIT;
1065 end if;
1066 when READ_SD_WAIT =>
1067 if (sd_started = '1') then
1068 state_read_sd <= READ_SD_END;
1069 end if;
1070 when READ_SD_END =>
1071 if (sd_ready = '1') then
1072 local_sd_data <= sd_data_in;
1073 sd_read <= '0';
1074 state_read_sd <= READ_SD_START;
1075 state_init <= next_state;
1076 end if;
1077 end case;
1078
1079 -- write to static data block
1080 when WRITE_TO_SD_ADDR =>
1081 case state_write_sd is
1082 when WRITE_SD_START =>
1083 if (sd_busy = '0') then
1084 sd_addr <= local_sd_addr;
1085 sd_data_out <= local_sd_data;
1086 sd_write <= '1';
1087 state_write_sd <= WRITE_SD_WAIT;
1088 end if;
1089 when WRITE_SD_WAIT =>
1090 if (sd_started = '1') then
1091 sd_write <= '0';
1092 state_write_sd <= WRITE_SD_END;
1093 end if;
1094 when WRITE_SD_END =>
1095 if (sd_ready = '1') then
1096 state_write_sd <= WRITE_SD_START;
1097 state_init <= next_state;
1098 end if;
1099 end case;
1100
1101 -- write to ethernet interface
1102 when WRITE_DATA =>
1103 case state_write is
1104 when WR_START =>
1105 state_write <= WR_LENGTH;
1106 when WR_LENGTH =>
1107 local_socket_nr <= "000";
1108 next_state_tmp <= next_state;
1109 -- Write Length: 2 := START and END of package
1110 write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2)
1111 data_cnt <= 0;
1112 header_cnt <= X"00";
1113 state_write <= WR_01;
1114 -- Check FIFO Size
1115 when WR_01 =>
1116 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
1117 state_init <= READ_REG;
1118 next_state <= WRITE_DATA;
1119 state_write <= WR_02;
1120 when WR_02 =>
1121 socket_tx_free (31 downto 16) <= data_read;
1122 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
1123 state_init <= READ_REG;
1124 next_state <= WRITE_DATA;
1125 state_write <= WR_03;
1126 when WR_03 =>
1127 socket_tx_free (15 downto 0) <= data_read;
1128 state_write <= WR_04;
1129 when WR_04 =>
1130 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
1131 state_write <= WR_01;
1132 else
1133 state_write <= WR_WRITE_START_DEL;
1134 end if;
1135
1136 -- write package start delimiter
1137 when WR_WRITE_START_DEL =>
1138 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1139 par_data <= FTM_PACKAGE_START;
1140 state_init <= WRITE_REG;
1141 next_state <= WRITE_DATA;
1142 state_write <= WR_GET_HEADER;
1143
1144 -- get header data
1145 when WR_GET_HEADER =>
1146 get_header <= '1';
1147 if (get_header_started = '1') then
1148 get_header <= '0';
1149 state_write <= WR_GET_HEADER_WAIT;
1150 end if;
1151
1152 when WR_GET_HEADER_WAIT =>
1153 if (get_header_ready = '1') then
1154 state_write <= WR_FIFO_HEADER;
1155 end if;
1156
1157 -- Fill FIFO
1158 -- write header
1159 when WR_FIFO_HEADER =>
1160 state_init <= READ_FROM_HEADER_MODUL;
1161 next_state <= WRITE_DATA;
1162 state_write <= WR_FIFO_HEADER_01;
1163
1164 when WR_FIFO_HEADER_01 =>
1165 header_cnt <= header_cnt + 1;
1166 if (header_cnt < FTM_HEADER_LENGTH) then
1167 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1168 par_data <= local_sd_data;
1169 state_init <= WRITE_REG;
1170 next_state <= WRITE_DATA;
1171 state_write <= WR_FIFO_HEADER;
1172 else
1173 if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then
1174 state_write <= WR_SD_ADDR;
1175 else
1176 state_write <= WR_FIFO_DATA;
1177 end if;
1178 end if;
1179
1180 -- write static data ram address (only for single address request)
1181 when WR_SD_ADDR =>
1182 write_length_bytes <= write_length_bytes + 2; -- one extra word to write
1183 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1184 par_data <= "0000" & local_sd_addr;
1185 state_init <= WRITE_REG;
1186 next_state <= WRITE_DATA;
1187 state_write <= WR_FIFO_DATA;
1188
1189 -- write data
1190 when WR_FIFO_DATA =>
1191 state_init <= read_addr_state;
1192 next_state <= WRITE_DATA;
1193 state_write <= WR_FIFO_DATA_01;
1194
1195 when WR_FIFO_DATA_01 =>
1196 data_cnt <= data_cnt + 1;
1197 if (data_cnt < local_write_length) then
1198 local_sd_addr <= local_sd_addr + 1;
1199 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1200 par_data <= local_sd_data;
1201 state_init <= WRITE_REG;
1202 next_state <= WRITE_DATA;
1203 state_write <= WR_FIFO_DATA;
1204 else
1205 state_write <= WR_WRITE_END_DEL;
1206 end if;
1207
1208 -- write package end delimiter
1209 when WR_WRITE_END_DEL =>
1210 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
1211 par_data <= FTM_PACKAGE_END;
1212 state_init <= WRITE_REG;
1213 next_state <= WRITE_DATA;
1214 state_write <= WR_05;
1215
1216 -- Send FIFO
1217 when WR_05 =>
1218 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
1219 par_data <= (0 => write_length_bytes (16), others => '0');
1220 state_init <= WRITE_REG;
1221 state_write <= WR_06;
1222 when WR_06 =>
1223 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
1224 par_data <= write_length_bytes (15 downto 0);
1225 state_init <= WRITE_REG;
1226 state_write <= WR_07;
1227 when WR_07 =>
1228 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
1229 par_data <= X"0020"; -- Send
1230 state_init <= WRITE_REG;
1231 state_write <= WR_08;
1232 when others =>
1233 state_init <= next_state_tmp;
1234 state_write <= WR_START;
1235 end case;
1236 -- End WRITE_DATA
1237
1238 when READ_REG =>
1239 case count is
1240 when "000" =>
1241 cs <= '0';
1242 rd <= '0';
1243 wr <= '1';
1244 data <= (others => 'Z'); -- !!!!!!!!!!
1245 count <= "001";
1246 addr <= par_addr;
1247 when "001" =>
1248 count <= "010";
1249 when "010" =>
1250 count <= "100";
1251 when "100" =>
1252 data_read <= data;
1253 count <= "110";
1254 when "110" =>
1255 count <= "111";
1256 when "111" =>
1257 cs <= '1';
1258 rd <= '1';
1259 count <= "000";
1260 state_init <= next_state;
1261 when others =>
1262 null;
1263 end case;
1264
1265 when WRITE_REG =>
1266 case count is
1267 when "000" =>
1268 cs <= '0';
1269 wr <= '0';
1270 rd <= '1';
1271 addr <= par_addr;
1272 data <= par_data;
1273 count <= "100";
1274 when "100" =>
1275 count <= "101";
1276 when "101" =>
1277 count <= "110";
1278 when "110" =>
1279 cs <= '1';
1280 wr <= '1';
1281 state_init <= next_state;
1282 count <= "000";
1283 when others =>
1284 null;
1285 end case;
1286
1287 when others =>
1288 null;
1289 end case;
1290 end if; -- int_flag = '0'
1291
1292 end if; -- rising_edge (clk)
1293
1294 end process w5300_init_proc;
1295
1296end Behavioral;
1297
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