source: firmware/FTM/fad_broadcast/FTM_fad_broadcast.vhd@ 17497

Last change on this file since 17497 was 11485, checked in by weitzel, 14 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 10.7 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 04/13/2011
6-- Design Name:
7-- Module Name: FTM_fad_broadcast - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Broadcast of trigger ID to FAD boards
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_fad_broadcast is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus 2 enables for crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- start/stop run from central control
59 enable_ID_sending : in std_logic;
60
61 -- missing information for trigger ID
62 TIM_source : in std_logic;
63 LP_settings : in std_logic_vector(3 downto 0);
64
65 -- communication with trigger_manager
66 trigger_ID_ready : in std_logic;
67 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
68 trigger_ID_read : out std_logic
69 );
70end FTM_fad_broadcast;
71
72architecture Behavioral of FTM_fad_broadcast is
73
74 -- internal registers to store trigger ID
75 signal trigger_ID_sig : std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
76 signal TIM_source_sig : std_logic := '0';
77 signal LP_settings_sig : std_logic_vector(3 downto 0) := (others => '0');
78
79 signal tx_start_sig : std_logic := '0';
80 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
81
82 -- rx_enable and tx_enable lines from different FTM_fad_rs485_interface
83 -- initialized in corresponding interface
84 -- the signals from interface 0 are used to drive the global enables
85 signal rx_en_0_sig : STD_LOGIC;
86 signal tx_en_0_sig : STD_LOGIC;
87 signal rx_en_1_sig : STD_LOGIC;
88 signal tx_en_1_sig : STD_LOGIC;
89 signal rx_en_2_sig : STD_LOGIC;
90 signal tx_en_2_sig : STD_LOGIC;
91 signal rx_en_3_sig : STD_LOGIC;
92 signal tx_en_3_sig : STD_LOGIC;
93
94 signal tx_busy_0_sig : std_logic; -- initialized in FTM_fad_rs485_interface_0
95 signal rx_valid_0_sig : std_logic; -- initialized in FTM_fad_rs485_interface_0
96 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_0
97 signal rx_busy_0_sig : std_logic; -- initialized in FTU_fad_rs485_interface_0
98
99 signal tx_busy_1_sig : std_logic; -- initialized in FTM_fad_rs485_interface_1
100 signal rx_valid_1_sig : std_logic; -- initialized in FTM_fad_rs485_interface_1
101 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_1
102 signal rx_busy_1_sig : std_logic; -- initialized in FTU_fad_rs485_interface_1
103
104 signal tx_busy_2_sig : std_logic; -- initialized in FTM_fad_rs485_interface_2
105 signal rx_valid_2_sig : std_logic; -- initialized in FTM_fad_rs485_interface_2
106 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_2
107 signal rx_busy_2_sig : std_logic; -- initialized in FTU_fad_rs485_interface_2
108
109 signal tx_busy_3_sig : std_logic; -- initialized in FTM_fad_rs485_interface_3
110 signal rx_valid_3_sig : std_logic; -- initialized in FTM_fad_rs485_interface_3
111 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_3
112 signal rx_busy_3_sig : std_logic; -- initialized in FTU_fad_rs485_interface_3
113
114 -- signals to control and read out CRC
115 signal reset_crc_sig : std_logic;
116 signal enable_crc_sig : std_logic;
117 signal crc_data_sig : std_logic_vector (FAD_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
118 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
119 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
120
121 -- various loop counters
122 signal frame_cnt : integer range 0 to (FAD_RS485_BLOCK_WIDTH / 8) := 0;
123
124 component FTM_fad_rs485_interface
125 port(
126 clk : IN std_logic;
127 -- RS485
128 rx_d : IN std_logic;
129 rx_en : OUT std_logic;
130 tx_d : OUT std_logic;
131 tx_en : OUT std_logic;
132 -- FPGA
133 rx_data : OUT std_logic_vector (7 DOWNTO 0);
134 rx_busy : OUT std_logic := '0';
135 rx_valid : OUT std_logic := '0';
136 tx_data : IN std_logic_vector (7 DOWNTO 0);
137 tx_busy : OUT std_logic := '0';
138 tx_start : IN std_logic
139 );
140 end component;
141
142 component ucrc_par
143 generic(
144 POLYNOMIAL : std_logic_vector;
145 INIT_VALUE : std_logic_vector;
146 DATA_WIDTH : integer range 2 to 256;
147 SYNC_RESET : integer range 0 to 1
148 );
149 port(
150 clk_i : in std_logic;
151 rst_i : in std_logic;
152 clken_i : in std_logic;
153 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
154 match_o : out std_logic;
155 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
156 );
157 end component;
158
159 type FTM_fad_broadcast_StateType is (INIT, IDLE, ACK, SEND_01, SEND_02, SEND_03);
160 signal FTM_fad_broadcast_State : FTM_fad_broadcast_StateType;
161
162begin
163
164 Inst_FTM_fad_rs485_interface_0 : FTM_fad_rs485_interface -- crate 0
165 port map(
166 clk => clk_50MHz,
167 -- RS485
168 rx_d => rx_d_0,
169 rx_en => rx_en_0_sig,
170 tx_d => tx_d_0,
171 tx_en => tx_en_0_sig,
172 -- FPGA
173 rx_data => rx_data_0_sig,
174 rx_busy => rx_busy_0_sig,
175 rx_valid => rx_valid_0_sig,
176 tx_data => tx_data_sig,
177 tx_busy => tx_busy_0_sig,
178 tx_start => tx_start_sig
179 );
180
181 Inst_FTM_fad_rs485_interface_1 : FTM_fad_rs485_interface -- crate 1
182 port map(
183 clk => clk_50MHz,
184 -- RS485
185 rx_d => rx_d_1,
186 rx_en => rx_en_1_sig,
187 tx_d => tx_d_1,
188 tx_en => tx_en_1_sig,
189 -- FPGA
190 rx_data => rx_data_1_sig,
191 rx_busy => rx_busy_1_sig,
192 rx_valid => rx_valid_1_sig,
193 tx_data => tx_data_sig,
194 tx_busy => tx_busy_1_sig,
195 tx_start => tx_start_sig
196 );
197
198 Inst_FTM_fad_rs485_interface_2 : FTM_fad_rs485_interface -- crate 2
199 port map(
200 clk => clk_50MHz,
201 -- RS485
202 rx_d => rx_d_2,
203 rx_en => rx_en_2_sig,
204 tx_d => tx_d_2,
205 tx_en => tx_en_2_sig,
206 -- FPGA
207 rx_data => rx_data_2_sig,
208 rx_busy => rx_busy_2_sig,
209 rx_valid => rx_valid_2_sig,
210 tx_data => tx_data_sig,
211 tx_busy => tx_busy_2_sig,
212 tx_start => tx_start_sig
213 );
214
215 Inst_FTM_fad_rs485_interface_3 : FTM_fad_rs485_interface -- crate 3
216 port map(
217 clk => clk_50MHz,
218 -- RS485
219 rx_d => rx_d_3,
220 rx_en => rx_en_3_sig,
221 tx_d => tx_d_3,
222 tx_en => tx_en_3_sig,
223 -- FPGA
224 rx_data => rx_data_3_sig,
225 rx_busy => rx_busy_3_sig,
226 rx_valid => rx_valid_3_sig,
227 tx_data => tx_data_sig,
228 tx_busy => tx_busy_3_sig,
229 tx_start => tx_start_sig
230 );
231
232 Inst_ucrc_par : ucrc_par
233 generic map(
234 POLYNOMIAL => CRC_POLYNOMIAL,
235 INIT_VALUE => CRC_INIT_VALUE,
236 DATA_WIDTH => (FAD_RS485_BLOCK_WIDTH - 8),
237 SYNC_RESET => 1
238 )
239 port map(
240 clk_i => clk_50MHz,
241 rst_i => reset_crc_sig,
242 clken_i => enable_crc_sig,
243 data_i => crc_data_sig,
244 match_o => open,
245 crc_o => crc_sig_inv
246 );
247
248 -- Main finite state machine to control all 40 FTUs
249 FTM_fad_broadcast_FSM: process (clk_50MHz)
250 begin
251 if Rising_edge(clk_50MHz) then
252 case FTM_fad_broadcast_State is
253
254 when INIT => -- reset CRC register
255 reset_crc_sig <= '1';
256 FTM_fad_broadcast_State <= IDLE;
257
258 when IDLE => -- wait for trigger_ID_ready flag
259 reset_crc_sig <= '0';
260 enable_crc_sig <= '0';
261 trigger_ID_read <= '0';
262 if (trigger_ID_ready = '1') then
263 TIM_source_sig <= TIM_source;
264 LP_settings_sig <= LP_settings;
265 trigger_ID_sig <= trigger_ID;
266 if (enable_ID_sending = '0') then
267 FTM_fad_broadcast_State <= ACK;
268 else
269 FTM_fad_broadcast_State <= SEND_01;
270 end if;
271 end if;
272
273 when ACK => -- just acknowledge trigger ID without sending it
274 trigger_ID_read <= '1';
275 reset_crc_sig <= '0';
276 if (trigger_ID_ready = '0') then
277 FTM_fad_broadcast_State <= IDLE;
278 end if;
279
280 when SEND_01 => -- prepare CRC calculation
281 enable_crc_sig <= '1';
282 crc_data_sig <= TIM_source & LP_settings & trigger_ID(42 downto 0);
283 FTM_fad_broadcast_State <= SEND_02;
284
285 when SEND_02 => -- wait one cycle for CRC calculation
286 enable_crc_sig <= '0';
287 FTM_fad_broadcast_State <= SEND_03;
288
289 when SEND_03 => -- transmit byte by byte
290 if ( (tx_busy_0_sig = '0') and (tx_busy_1_sig = '0') and (tx_busy_2_sig = '0') and (tx_busy_3_sig = '0') ) then
291 if (frame_cnt < 6) then
292 frame_cnt <= frame_cnt + 1;
293 tx_data_sig <= crc_data_sig (7 downto 0);
294 crc_data_sig <= "00000000" & crc_data_sig ((FAD_RS485_BLOCK_WIDTH - 9) downto 8);
295 tx_start_sig <= '1';
296 FTM_fad_broadcast_State <= SEND_03;
297 elsif (frame_cnt = 6) then
298 frame_cnt <= frame_cnt + 1;
299 tx_data_sig <= crc_sig;
300 tx_start_sig <= '1';
301 FTM_fad_broadcast_State <= SEND_03;
302 else
303 frame_cnt <= 0;
304 reset_crc_sig <= '1';
305 FTM_fad_broadcast_State <= ACK;
306 end if;
307 else
308 tx_start_sig <= '0';
309 FTM_fad_broadcast_State <= SEND_03;
310 end if;
311
312 end case;
313 end if;
314 end process FTM_fad_broadcast_FSM;
315
316 rx_en <= rx_en_0_sig;
317 tx_en <= tx_en_0_sig;
318
319 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
320
321end Behavioral;
322
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