source: firmware/FTM/ftm_board.ucf @ 10067

Last change on this file since 10067 was 10067, checked in by weitzel, 10 years ago
Skeleton of FTM_top and FTM_top_tb added
File size: 16.6 KB
Line 
1########################################################
2# FTM Board
3# FACT Trigger Master
4#
5# Pin location constraints
6#
7# by Patrick Vogler
8# 18 August 2010
9########################################################
10
11
12#Clock
13#######################################################
14NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
15
16
17# Ethernet Interface
18# connection to the WIZnet W5300 ethernet controller (U37)
19# on IO-Bank 1
20#######################################################
21# data bus
22NET W_D<0>  LOC  = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300       
23NET W_D<1>  LOC  = L22 | IOSTANDARD=LVCMOS33; #
24NET W_D<2>  LOC  = K23 | IOSTANDARD=LVCMOS33; #
25NET W_D<3>  LOC  = K25 | IOSTANDARD=LVCMOS33; #
26NET W_D<4>  LOC  = K26 | IOSTANDARD=LVCMOS33; #
27NET W_D<5>  LOC  = J22 | IOSTANDARD=LVCMOS33; #
28NET W_D<6>  LOC  = J23 | IOSTANDARD=LVCMOS33; #         
29NET W_D<7>  LOC  = G23 | IOSTANDARD=LVCMOS33; #
30NET W_D<8>  LOC  = G24 | IOSTANDARD=LVCMOS33; #
31NET W_D<9>  LOC  = F24 | IOSTANDARD=LVCMOS33; #
32NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33; #
33NET W_D<11> LOC  = E24 | IOSTANDARD=LVCMOS33; #
34NET W_D<12> LOC  = E26 | IOSTANDARD=LVCMOS33; #
35NET W_D<13> LOC  = D24 | IOSTANDARD=LVCMOS33; #
36NET W_D<14> LOC  = D26 | IOSTANDARD=LVCMOS33; #
37NET W_D<15> LOC  = D25 | IOSTANDARD=LVCMOS33; #
38
39# W5300 address bus
40NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because
41NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
42NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet
43NET W_A<4> LOC  = Y25  | IOSTANDARD=LVCMOS33; #
44NET W_A<5> LOC  = Y24  | IOSTANDARD=LVCMOS33; #
45NET W_A<6> LOC  = Y23  | IOSTANDARD=LVCMOS33; #
46NET W_A<7> LOC  = W23  | IOSTANDARD=LVCMOS33; #
47NET W_A<8> LOC  = V25  | IOSTANDARD=LVCMOS33; #
48NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
49
50# W5300 control signals
51# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
52# W_CS is also routed to testpoint JP7
53NET W_CS    LOC  = T20  | IOSTANDARD=LVCMOS33; # W5300 chip select
54NET W_INT   LOC  = U22  | IOSTANDARD=LVCMOS33; # interrupt
55NET W_RD    LOC  = R20  | IOSTANDARD=LVCMOS33; # read
56NET W_WR    LOC  = P22  | IOSTANDARD=LVCMOS33; # write
57NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
58
59# W5300 buffer ready indicator
60NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
61NET W_BRDY<1>   LOC  = AC26  | IOSTANDARD=LVCMOS33; #
62NET W_BRDY<2>   LOC  = AC25  | IOSTANDARD=LVCMOS33; #
63NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
64
65# W5300 associated testpoints
66NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
67NET W_T<1>   LOC  = M21  | IOSTANDARD=LVCMOS33; #
68NET W_T<2>   LOC  = K21  | IOSTANDARD=LVCMOS33; #
69NET W_T<3>   LOC  = R19  | IOSTANDARD=LVCMOS33; #
70
71
72# SPI Interface
73# connection to the EEPROM U36 (AL25L016M) and the temperature
74# sensors U45, U46, U48 and U49 (all MAX6662)
75# on IO-Bank 1
76#######################################################
77NET S_CLK  LOC  = U20  | IOSTANDARD=LVCMOS33;  # SPI clock
78
79# EEPROM
80NET MOSI   LOC  = AA22 | IOSTANDARD=LVCMOS33;    # master out slave in
81NET MISO   LOC  = V22  | IOSTANDARD=LVCMOS33;    # master in slave out
82NET EE_CS  LOC  = G22  | IOSTANDARD=LVCMOS33;    # master out slave in
83
84# temperature sensors
85NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
86NET TS_CS<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
87NET TS_CS<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
88NET TS_CS<2>  LOC  = C25  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select2
89NET TS_CS<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
90
91
92# Trigger primitives inputs
93# on IO-Bank 2
94#######################################################
95# crate 0
96# crate A
97NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>       
98NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
99NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
100NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
101NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
102NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
103NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
104NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
105NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
106NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
107
108# crate 1
109# crate B
110NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>       
111NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
112NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
113NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
114NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
115NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
116NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
117NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
118NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
119NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
120
121# crate 2
122# crate C
123NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>       
124NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
125NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
126NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
127NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
128NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
129NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
130NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
131NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
132NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
133
134# crate 3
135# crate D
136NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>       
137NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
138NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
139NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
140NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
141NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
142NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
143NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
144NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
145NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
146
147
148# NIM inputs
149#######################################################
150# on IO-Bank 3
151NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
152NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
153NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
154NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
155NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
156NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
157
158# on IO-Bank 0
159# input pin with global clock buffer available
160NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
161
162
163# LEDs
164# on IO-Banks 0 and 3
165#######################################################
166# red
167NET LED_red<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
168NET LED_red<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
169NET LED_red<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
170NET LED_red<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
171
172# yellow
173NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
174NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
175
176# green
177NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
178NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
179
180
181# Clock conditioner LMK03000
182# on IO-Bank 3
183#######################################################
184NET CLK_Clk_Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
185NET LE_Clk_Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
186NET LD_Clk_Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
187NET DATA_Clk_Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
188NET SYNC_Clk_Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
189
190
191# various RS-485 Interfaces
192# on IO-Bank 3
193#######################################################
194# Bus 1: FTU slow control
195NET Bus1_Tx_En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
196NET Bus1_Rx_En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
197
198# crate 0
199NET Bus1_RxD_0   LOC  = K3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
200NET Bus1_TxD_0   LOC  = L3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
201
202# crate 1
203NET Bus1_RxD_1   LOC  = M2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
204NET Bus1_TxD_1   LOC  = N4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
205
206# crate 2
207NET Bus1_RxD_2   LOC  = P3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
208NET Bus1_TxD_2   LOC  = P4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
209
210# crate 3
211NET Bus1_RxD_3   LOC  = T4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
212NET Bus1_TxD_3   LOC  = T3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
213
214
215# Bus 2: Trigger-ID to FAD boards
216NET Bus2_Tx_En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
217NET Bus2_Rx_En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
218
219# crate 0
220NET Bus2_RxD_0   LOC  = L4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
221NET Bus2_TxD_0   LOC  = M3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
222
223# crate 1
224NET Bus2_RxD_1   LOC  = N2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
225NET Bus2_TxD_1   LOC  = N1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
226
227# crate 2
228NET Bus2_RxD_2   LOC  = R2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
229NET Bus2_TxD_2   LOC  = R1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
230
231# crate 3
232NET Bus2_RxD_3   LOC  = U4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
233NET Bus2_TxD_3   LOC  = U2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
234
235
236# auxiliary access
237NET Aux_Rx_D     LOC  = W3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
238NET Aux_Tx_D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
239NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
240NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
241
242# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
243NET TrID_Rx_D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
244NET TrID_Tx_D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
245
246
247# Crate-Resets
248# on IO-Bank 3
249#######################################################
250NET Crate_Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
251NET Crate_Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
252NET Crate_Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
253NET Crate_Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
254
255
256# Busy signals from the FAD boards
257# on IO-Bank 3
258#######################################################
259NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
260NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
261NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
262NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
263
264
265# NIM outputs
266# on IO-Bank 0
267# LVDS output at the FPGA followed by LVDS to NIM
268# conversion stage
269#######################################################
270# calibration
271NET Cal_NIM1_p   LOC  = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM1+
272NET Cal_NIM1_n   LOC  = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM1-
273NET Cal_NIM2_p   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2+
274NET Cal_NIM2_n   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2-
275
276# auxiliarry / spare NIM outputs
277NET NIM_Out0_p  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #  NIM_Out0+
278NET NIM_Out0_n  LOC  = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-
279NET NIM_Out1_p  LOC  = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  NIM_Out1+
280NET NIM_Out1_n  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
281
282
283# fast control signal outputs
284# LVDS output at the FPGA followed by LVDS to NIM
285# conversion stage
286#######################################################
287NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
288NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
289
290NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
291NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
292
293NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
294NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
295
296NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
297
298NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
299
300
301# LVDS calibration outputs
302# on IO-Bank 0
303#######################################################
304# to connector J13
305NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
306NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
307NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
308NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
309NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
310NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
311NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
312NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
313
314# to connector J12
315NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+   
316NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-   
317NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+   
318NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-   
319NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+   
320NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-   
321NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+   
322NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-   
323
324
325# Testpoints
326######################################################
327# Connector T7
328# IO-Bank 0
329NET TP<0> LOC  = B14 | IOSTANDARD=LVCMOS33;  #
330NET TP<1> LOC  = A14 | IOSTANDARD=LVCMOS33;  #
331NET TP<2> LOC  = C13 | IOSTANDARD=LVCMOS33;  #
332NET TP<3> LOC  = B13 | IOSTANDARD=LVCMOS33;  #
333
334# Connector T10
335# IO-Bank 0
336NET TP<4> LOC  = D13 | IOSTANDARD=LVCMOS33;  #
337NET TP<5> LOC  = C12 | IOSTANDARD=LVCMOS33;  #
338NET TP<6> LOC  = B12 | IOSTANDARD=LVCMOS33;  #
339NET TP<7> LOC  = A12 | IOSTANDARD=LVCMOS33;  #
340
341# on Connector T12
342# IO-Bank 0
343NET TP<8> LOC  = D11 | IOSTANDARD=LVCMOS33;  #
344NET TP<9> LOC  = C11 | IOSTANDARD=LVCMOS33;  #
345
346# on Connector T14
347# IO-Bank 0
348NET TP<10> LOC  = D10 | IOSTANDARD=LVCMOS33;  #
349NET TP<11> LOC  = C10 | IOSTANDARD=LVCMOS33;  #
350NET TP<12> LOC  = A10 | IOSTANDARD=LVCMOS33;  #
351NET TP<13> LOC  = B10 | IOSTANDARD=LVCMOS33;  #
352
353# on Connector T16
354# IO-Bank 0
355NET TP<14> LOC  = A9 | IOSTANDARD=LVCMOS33;  #
356NET TP<15> LOC  = B9 | IOSTANDARD=LVCMOS33;  #
357NET TP<16> LOC  = A8 | IOSTANDARD=LVCMOS33;  #
358NET TP<17> LOC  = B8 | IOSTANDARD=LVCMOS33;  #
359
360# on Connector T8
361# IO-Bank 0
362NET TP<18> LOC  = C8 | IOSTANDARD=LVCMOS33;  #
363NET TP<19> LOC  = D8 | IOSTANDARD=LVCMOS33;  #
364NET TP<20> LOC  = C6 | IOSTANDARD=LVCMOS33;  #
365NET TP<21> LOC  = B6 | IOSTANDARD=LVCMOS33;  #
366
367# on Connector T9
368# IO-Bank 0
369NET TP<22> LOC  = C7 | IOSTANDARD=LVCMOS33;  #
370NET TP<23> LOC  = B7 | IOSTANDARD=LVCMOS33;  #
371
372# on Connector T11
373# IO-Bank 3
374NET TP<24> LOC  = Y1  | IOSTANDARD=LVCMOS33;  #
375NET TP<25> LOC  = AA3 | IOSTANDARD=LVCMOS33;  #
376NET TP<26> LOC  = AA2 | IOSTANDARD=LVCMOS33;  #
377NET TP<27> LOC  = AC1 | IOSTANDARD=LVCMOS33;  #
378
379# on Connector T13
380# IO-Bank 3
381NET TP<28> LOC  = AB1 | IOSTANDARD=LVCMOS33;  #
382NET TP<29> LOC  = AC3 | IOSTANDARD=LVCMOS33;  #
383NET TP<30> LOC  = AC2 | IOSTANDARD=LVCMOS33;  #
384NET TP<31> LOC  = AD2 | IOSTANDARD=LVCMOS33;  #
385
386# on Connector T15
387NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
388NET TP_in<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
389NET TP_in<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
390
391
392# Board ID - inputs
393# local board-ID "solder programmable"
394# all on 'input only' pins
395#######################################################
396NET brd_id<0> LOC  = A13 | IOSTANDARD=LVCMOS33; #               
397NET brd_id<1> LOC  = A17 | IOSTANDARD=LVCMOS33; #               
398NET brd_id<2> LOC  = D12 | IOSTANDARD=LVCMOS33; #               
399NET brd_id<3> LOC  = N25 | IOSTANDARD=LVCMOS33; #               
400NET brd_id<4> LOC  = N26 | IOSTANDARD=LVCMOS33; #               
401NET brd_id<5> LOC  = K24 | IOSTANDARD=LVCMOS33; #               
402NET brd_id<6> LOC  = H24 | IOSTANDARD=LVCMOS33; #       
403NET brd_id<7> LOC  = Y26 | IOSTANDARD=LVCMOS33; #       
404
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