source: firmware/FTM/ftm_board.ucf@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 17.0 KB
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1########################################################
2# FTM Board
3# FACT Trigger Master
4#
5# Pin location constraints
6#
7# by Patrick Vogler, 18 August 2010
8#
9# modified by Q. Weitzel, 01 March 2011
10# (NET W_A<0> added and assigned to unconnected pin)
11########################################################
12
13
14#Clock
15#######################################################
16NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
17
18
19# Ethernet Interface
20# connection to the WIZnet W5300 ethernet controller (U37)
21# on IO-Bank 1
22#######################################################
23# data bus
24NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
25NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #
26NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #
27NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; #
28NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #
29NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; #
30NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #
31NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; #
32NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; #
33NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #
34NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #
35NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; #
36NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; #
37NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; #
38NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; #
39NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; #
40
41# W5300 address bus
42NET W_A<0> LOC = U18 | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
43NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
44NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # (see W5300 datasheet)
45NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
46NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #
47NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #
48NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #
49NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #
50NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #
51NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #
52
53# W5300 control signals
54# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
55# W_CS is also routed to testpoint JP7
56NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select
57NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt
58NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read
59NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write
60NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip
61
62# W5300 buffer ready indicator
63# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #
64# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; #
65# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; #
66# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #
67
68# W5300 associated testpoints
69# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; #
70# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #
71# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; #
72# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #
73
74
75# SPI Interface
76# connection to the EEPROM U36 (AL25L016M) and the temperature
77# sensors U45, U46, U48 and U49 (all MAX6662)
78# on IO-Bank 1
79#######################################################
80# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock
81
82# EEPROM
83# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in
84# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out
85# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in
86
87# temperature sensors
88# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO
89# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0
90# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1
91# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2
92# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3
93
94
95# Trigger primitives inputs
96# on IO-Bank 2
97#######################################################
98# crate 0
99# crate A
100NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
101NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
102NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
103NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
104NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
105NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
106NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
107NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
108NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
109NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
110
111# crate 1
112# crate B
113NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
114NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
115NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
116NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
117NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
118NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
119NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
120NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
121NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
122NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
123
124# crate 2
125# crate C
126NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
127NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
128NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
129NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
130NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
131NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
132NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
133NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
134NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
135NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
136
137# crate 3
138# crate D
139NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
140NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
141NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
142NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
143NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
144NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
145NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
146NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
147NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
148NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
149
150
151# NIM inputs
152#######################################################
153# on IO-Bank 3
154NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; #
155NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; #
156NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; #
157# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; #
158# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; #
159# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; #
160
161# on IO-Bank 0
162# input pin with global clock buffer available
163# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33;
164
165
166# LEDs
167# on IO-Banks 0 and 3
168#######################################################
169# red
170NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0
171NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
172NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
173NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3
174
175# yellow
176NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0
177NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
178
179# green
180NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
181NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
182
183
184# Clock conditioner LMK03000
185# on IO-Bank 3
186#######################################################
187NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
188NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
189NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
190NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3
191NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
192
193
194# various RS-485 Interfaces
195# on IO-Bank 3
196#######################################################
197# Bus 1: FTU slow control
198NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
199NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
200
201# crate 0
202NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
203NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
204
205# crate 1
206NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
207NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
208
209# crate 2
210NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
211NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
212
213# crate 3
214NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
215NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
216
217
218# Bus 2: Trigger-ID to FAD boards
219# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
220# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
221
222# crate 0
223# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
224# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
225
226# crate 1
227# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
228# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
229
230# crate 2
231# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
232# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
233
234# crate 3
235# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
236# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
237
238
239# auxiliary access
240# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
241# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
242# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
243# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
244
245# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
246# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
247# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
248
249
250# Crate-Resets
251# on IO-Bank 3
252#######################################################
253# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
254# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
255# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
256# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
257
258
259# Busy signals from the FAD boards
260# on IO-Bank 3
261#######################################################
262NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
263NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
264NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
265NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
266
267
268# NIM outputs
269# on IO-Bank 0
270# LVDS output at the FPGA followed by LVDS to NIM
271# conversion stage
272#######################################################
273# calibration
274# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+
275# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1-
276# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+
277# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2-
278
279# auxiliarry / spare NIM outputs
280# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+
281# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-
282# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+
283# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
284
285
286# fast control signal outputs
287# LVDS output at the FPGA followed by LVDS to NIM
288# conversion stage
289#######################################################
290# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
291# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
292
293NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
294NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
295
296NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
297NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
298
299NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2
300
301# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA
302
303
304# LVDS calibration outputs
305# on IO-Bank 0
306#######################################################
307# to connector J13
308# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
309# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
310# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
311# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
312# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
313# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
314# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
315# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
316
317# to connector J12
318# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+
319# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-
320# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+
321# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-
322# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+
323# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-
324# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+
325# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-
326
327
328# Testpoints
329######################################################
330# Connector T7
331# IO-Bank 0
332# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; #
333# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; #
334# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; #
335# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; #
336
337# Connector T10
338# IO-Bank 0
339# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; #
340# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; #
341# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; #
342# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; #
343
344# on Connector T12
345# IO-Bank 0
346# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; #
347# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; #
348
349# on Connector T14
350# IO-Bank 0
351# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; #
352# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; #
353# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; #
354# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; #
355
356# on Connector T16
357# IO-Bank 0
358# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; #
359# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; #
360# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; #
361# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; #
362
363# on Connector T8
364# IO-Bank 0
365# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; #
366# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; #
367# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; #
368# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; #
369
370# on Connector T9
371# IO-Bank 0
372# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; #
373# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; #
374
375# on Connector T11
376# IO-Bank 3
377# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; #
378# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; #
379# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; #
380# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; #
381
382# on Connector T13
383# IO-Bank 3
384# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; #
385# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; #
386# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; #
387# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; #
388
389# on Connector T15
390# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
391# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only
392# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only
393
394
395# Board ID - inputs
396# local board-ID "solder programmable"
397# all on 'input only' pins
398#######################################################
399# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; #
400# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; #
401# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; #
402# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; #
403# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; #
404# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; #
405# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; #
406# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; #
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