source: firmware/FTM/ftm_board.ucf @ 9844

Last change on this file since 9844 was 9844, checked in by vogler, 10 years ago
FTM: first version of the pin location ucf file (ftm_board.ucf) added to the repository
File size: 15.8 KB
Line 
1########################################################
2# FTM Board
3# FACT Trigger Master
4#
5# Pin location constraints
6#
7# by Patrick Vogler
8# 02 July 2010
9########################################################
10
11
12#Clock
13#######################################################
14NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK
15
16
17# Ethernet Interface
18# connection to the WIZnet W5300 ethernet controller
19# on IO-Bank 1
20#######################################################
21# data bus
22NET W_D<0>  LOC  = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300       
23NET W_D<1>  LOC  = L22 | IOSTANDARD=LVCMOS33; #
24NET W_D<2>  LOC  = K23 | IOSTANDARD=LVCMOS33; #
25NET W_D<3>  LOC  = K25 | IOSTANDARD=LVCMOS33; #
26NET W_D<4>  LOC  = K26 | IOSTANDARD=LVCMOS33; #
27NET W_D<5>  LOC  = J22 | IOSTANDARD=LVCMOS33; #
28NET W_D<6>  LOC  = J23 | IOSTANDARD=LVCMOS33; #         
29NET W_D<7>  LOC  = G23 | IOSTANDARD=LVCMOS33; #
30NET W_D<8>  LOC  = G24 | IOSTANDARD=LVCMOS33; #
31NET W_D<9>  LOC  = F24 | IOSTANDARD=LVCMOS33; #
32NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33; #
33NET W_D<11> LOC  = E24 | IOSTANDARD=LVCMOS33; #
34NET W_D<12> LOC  = E26 | IOSTANDARD=LVCMOS33; #
35NET W_D<13> LOC  = D24 | IOSTANDARD=LVCMOS33; #
36NET W_D<14> LOC  = D26 | IOSTANDARD=LVCMOS33; #
37NET W_D<15> LOC  = D25 | IOSTANDARD=LVCMOS33; #
38
39# W5300 address bus
40NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because
41NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
42NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet
43NET W_A<4> LOC  = Y25  | IOSTANDARD=LVCMOS33; #
44NET W_A<5> LOC  = Y24  | IOSTANDARD=LVCMOS33; #
45NET W_A<6> LOC  = Y23  | IOSTANDARD=LVCMOS33; #
46NET W_A<7> LOC  = W23  | IOSTANDARD=LVCMOS33; #
47NET W_A<8> LOC  = V25  | IOSTANDARD=LVCMOS33; #
48NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
49
50# W5300 controll signals
51# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
52# W_CS is also routed to testpoint JP7
53NET W_CS    LOC  = T20  | IOSTANDARD=LVCMOS33; # W5300 chip select
54NET W_INT   LOC  = U22  | IOSTANDARD=LVCMOS33; # interrupt
55NET W_RD    LOC  = R20  | IOSTANDARD=LVCMOS33; # read
56NET W_WR    LOC  = P22  | IOSTANDARD=LVCMOS33; # write
57NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
58
59# W5300
60NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
61NET W_BRDY<1>   LOC  = AC26  | IOSTANDARD=LVCMOS33; #
62NET W_BRDY<2>   LOC  = AC25  | IOSTANDARD=LVCMOS33; #
63NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
64
65# W5300
66NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
67NET W_T<1>   LOC  = M21  | IOSTANDARD=LVCMOS33; #
68NET W_T<2>   LOC  = K21  | IOSTANDARD=LVCMOS33; #
69
70
71# SPI Interface
72# connection to the EEPROM U36 (AL25L016M) and the temperature
73# sensors U45, U46, U48 and U49 (all MAX6662)
74# on IO-Bank 1
75#######################################################
76NET S_CLK  LOC  = U20  | IOSTANDARD=LVCMOS33;  # SPI clock
77
78# EEPROM
79NET MOSI   LOC  = AA22 | IOSTANDARD=LVCMOS33;    # master out slave in
80NET MISO   LOC  = V22  | IOSTANDARD=LVCMOS33;    # master in slave out
81NET EE_CS  LOC  = G22  | IOSTANDARD=LVCMOS33;    # master out slave in
82
83# temperature sensors
84NET SIO        LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
85NET TS_CS_<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
86NET TS_CS_<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
87NET TS_CS_<2>  LOC  = C25  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select2
88NET TS_CS_<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
89
90
91# Trigger primitives inputs
92# on IO-Bank 2
93#######################################################
94# crate 0
95NET Trig-Prim_0_<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; #       
96NET Trig-Prim_0_<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; #
97NET Trig-Prim_0_<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; #
98NET Trig-Prim_0_<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; #
99NET Trig-Prim_0_<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; #
100NET Trig-Prim_0_<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; #
101NET Trig-Prim_0_<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; #
102NET Trig-Prim_0_<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; #
103NET Trig-Prim_0_<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; #
104NET Trig-Prim_0_<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; #
105
106# crate 1
107NET Trig-Prim_1_<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; #       
108NET Trig-Prim_1_<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; #
109NET Trig-Prim_1_<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; #
110NET Trig-Prim_1_<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; #
111NET Trig-Prim_1_<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; #
112NET Trig-Prim_1_<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; #
113NET Trig-Prim_1_<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; #
114NET Trig-Prim_1_<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; #
115NET Trig-Prim_1_<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; #
116NET Trig-Prim_1_<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; #
117
118# crate 2
119NET Trig-Prim_2_<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; #       
120NET Trig-Prim_2_<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; #
121NET Trig-Prim_2_<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; #
122NET Trig-Prim_2_<3>  LOC  = AD21 | IOSTANDARD=LVCMOS33; #
123NET Trig-Prim_2_<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; #
124NET Trig-Prim_2_<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; #
125NET Trig-Prim_2_<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; #
126NET Trig-Prim_2_<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; #
127NET Trig-Prim_2_<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; #
128NET Trig-Prim_2_<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; #
129
130# crate 3
131NET Trig-Prim_3_<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; #       
132NET Trig-Prim_3_<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; #
133NET Trig-Prim_3_<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; #
134NET Trig-Prim_3_<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; #
135NET Trig-Prim_3_<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; #
136NET Trig-Prim_3_<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; #
137NET Trig-Prim_3_<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; #
138NET Trig-Prim_3_<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; #
139NET Trig-Prim_3_<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; #
140NET Trig-Prim_3_<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; #
141
142
143# NIM inputs
144#######################################################
145# on IO-Bank 3
146NET ext_Trig_<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
147NET ext_Trig_<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
148NET Veto          LOC  = E4  | IOSTANDARD=LVCMOS33; #
149NET NIM_In<0>     LOC  = D3  | IOSTANDARD=LVCMOS33; #
150NET NIM_In<1>     LOC  = F4  | IOSTANDARD=LVCMOS33; #
151NET NIM_In<2>     LOC  = E3  | IOSTANDARD=LVCMOS33; #
152
153# on IO-Bank 0
154NET NIM_In3/GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33; # input with global clock buffer
155                                                     # available
156
157
158# LEDs
159# on IO-Banks 0 and 3
160#######################################################
161###                                                 ###
162#          OPEN COLLECTOR OUTPUTS FOR THE LEDs        #
163###                                                 ###
164# red
165NET LED_red_<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
166NET LED_red_<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
167NET LED_red_<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3 
168NET LED_red_<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3 
169
170# yellow
171NET LED_ye_<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
172NET LED_ye_<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
173
174# green
175NET LED_gn_<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
176NET LED_gn_<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
177
178
179# Clock conditioner LMK03000
180# on IO-Bank 3
181#######################################################
182NET CLK_Clk-Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
183NET LE_Clk-Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
184NET LD_Clk-Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
185NET DATA_Clk-Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
186NET SYNC_Clk-Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
187
188
189# various RS-485 Interfaces
190# on IO-Bank 3
191#######################################################
192# Bus 1: FTU slow control
193NET Bus1_Tx-En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
194NET Bus1_Rx-En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
195
196# crate 0
197NET Bus1_RxD_0   LOC  = K3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
198NET Bus1_TxD_0   LOC  = L3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
199
200# crate 1
201NET Bus1_RxD_1   LOC  = M2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
202NET Bus1_TxD_1   LOC  = N4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
203
204# crate 2
205NET Bus1_RxD_2   LOC  = P3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
206NET Bus1_TxD_2   LOC  = P4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
207
208# crate 3
209NET Bus1_RxD_3   LOC  = T4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
210NET Bus1_TxD_3   LOC  = T3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
211
212
213# Bus 2: Trigger-ID to FAD boards
214NET Bus2_Tx-En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
215NET Bus2_Rx-En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
216
217# crate 0
218NET Bus2_RxD_0   LOC  = L4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
219NET Bus2_TxD_0   LOC  = M3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
220
221# crate 1
222NET Bus2_RxD_1   LOC  = N2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
223NET Bus2_TxD_1   LOC  = N1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
224
225# crate 2
226NET Bus2_RxD_2   LOC  = R2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
227NET Bus2_TxD_2   LOC  = R1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
228
229# crate 3
230NET Bus2_RxD_3   LOC  = U4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
231NET Bus2_TxD_3   LOC  = U2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
232
233
234# auxiliary access
235NET Aux_Rx-D     LOC  = W3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
236NET Aux_Tx-D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
237NET Aux_Rx-En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
238NET Aux_Tx-En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
239                                                                  # Trigger-ID
240
241# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
242NET TrID_Rx-D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
243NET TrID_Tx-D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
244
245
246# Crate-Resets
247# on IO-Bank 3
248#######################################################
249NET Crate-Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
250NET Crate-Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
251NET Crate-Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
252NET Crate-Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
253
254
255# Busy signals from the FAD boards
256# on IO-Bank 3
257#######################################################
258NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
259NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
260NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
261NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
262
263
264# NIM outputs
265# on IO-Bank 0
266# LVDS output at the FPGA followed by LVDS to NIM
267# conversion stage
268#######################################################
269# calibration
270NET Cal_NIM1+   LOC  = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
271NET Cal_NIM1-   LOC  = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
272NET Cal_NIM2+   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
273NET Cal_NIM2-   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
274
275# auxiliarry / spare NIM outputs
276NET NIM_Out0+  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
277NET NIM_Out0-  LOC  = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
278NET NIM_Out1+  LOC  = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
279NET NIM_Out1-  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
280
281
282# fast control signal outputs
283# LVDS output at the FPGA followed by LVDS to NIM
284# conversion stage
285#######################################################
286NET RES+       LOC  = D16  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # Reset
287NET RES-       LOC  = C15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # IO-Bank 0
288
289NET TRG+       LOC  = B15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; # Trigger
290NET TRG-       LOC  = A15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; # IO-Bank 0
291
292NET TIM_Run+   LOC  = AF25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # Time Marker
293NET TIM_Run-   LOC  = AE25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # IO-Bank 2
294NET TIM-Sel    LOC  = AD22 | IOSTANDARD=LVCMOS33;   # Time Marker selector
295                                                    # IO-Bank 2
296NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
297
298
299# LVDS calibration outputs
300# on IO-Bank 0
301#######################################################
302# to connector J13
303NET Cal_0+   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
304NET Cal_0-   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
305NET Cal_1+   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
306NET Cal_1-   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
307NET Cal_2+   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
308NET Cal_2-   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
309NET Cal_3+   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
310NET Cal_3-   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
311
312# to connector J12
313NET Cal_4+   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
314NET Cal_4-   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
315NET Cal_5+   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
316NET Cal_5-   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
317NET Cal_6+   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
318NET Cal_6-   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
319NET Cal_7+   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
320NET Cal_7-   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # 
321
322
323# Testpoints
324######################################################
325# Connector T7
326# IO-Bank 0
327NET TP<0> LOC  = B14 | IOSTANDARD=LVCMOS33;  #
328NET TP<1> LOC  = A14 | IOSTANDARD=LVCMOS33;  #
329NET TP<2> LOC  = C13 | IOSTANDARD=LVCMOS33;  #
330NET TP<3> LOC  = B13 | IOSTANDARD=LVCMOS33;  #
331
332# Connector T10
333# IO-Bank 0
334NET TP<4> LOC  = D13 | IOSTANDARD=LVCMOS33;  #
335NET TP<5> LOC  = C12 | IOSTANDARD=LVCMOS33;  #
336NET TP<6> LOC  = B12 | IOSTANDARD=LVCMOS33;  #
337NET TP<7> LOC  = A12 | IOSTANDARD=LVCMOS33;  #
338
339# on Connector T12
340# IO-Bank 0
341NET TP<8> LOC  = D11 | IOSTANDARD=LVCMOS33;  #
342NET TP<9> LOC  = C11 | IOSTANDARD=LVCMOS33;  #
343
344# on Connector T14
345# IO-Bank 0
346NET TP<10> LOC  = D10 | IOSTANDARD=LVCMOS33;  #
347NET TP<11> LOC  = C10 | IOSTANDARD=LVCMOS33;  #
348NET TP<12> LOC  = A10 | IOSTANDARD=LVCMOS33;  #
349NET TP<13> LOC  = B10 | IOSTANDARD=LVCMOS33;  #
350
351# on Connector T16
352# IO-Bank 0
353NET TP<14> LOC  = A9 | IOSTANDARD=LVCMOS33;  #
354NET TP<15> LOC  = B9 | IOSTANDARD=LVCMOS33;  #
355NET TP<16> LOC  = A8 | IOSTANDARD=LVCMOS33;  #
356NET TP<17> LOC  = B8 | IOSTANDARD=LVCMOS33;  #
357
358# on Connector T8
359# IO-Bank 0
360NET TP<18> LOC  = C8 | IOSTANDARD=LVCMOS33;  #
361NET TP<19> LOC  = D8 | IOSTANDARD=LVCMOS33;  #
362NET TP<20> LOC  = C6 | IOSTANDARD=LVCMOS33;  #
363NET TP<21> LOC  = B6 | IOSTANDARD=LVCMOS33;  #
364
365# on Connector T9
366# IO-Bank 0
367NET TP<22> LOC  = C7 | IOSTANDARD=LVCMOS33;  #
368NET TP<23> LOC  = B7 | IOSTANDARD=LVCMOS33;  #
369
370# on Connector T11
371# IO-Bank 3
372NET TP<24> LOC  = Y1  | IOSTANDARD=LVCMOS33;  #
373NET TP<25> LOC  = AA3 | IOSTANDARD=LVCMOS33;  #
374NET TP<26> LOC  = AA2 | IOSTANDARD=LVCMOS33;  #
375NET TP<27> LOC  = AC1 | IOSTANDARD=LVCMOS33;  #
376
377# on Connector T13
378# IO-Bank 3
379NET TP<28> LOC  = AB1 | IOSTANDARD=LVCMOS33;  #
380NET TP<29> LOC  = AC3 | IOSTANDARD=LVCMOS33;  #
381NET TP<30> LOC  = AC2 | IOSTANDARD=LVCMOS33;  #
382NET TP<31> LOC  = AD2 | IOSTANDARD=LVCMOS33;  #
383
384# on Connector T15
385NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
386NET TP<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
387NET TP<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
388
389
390# Board ID - inputs
391# local board-ID "solder programmable"
392# all on 'input only' pins
393#######################################################
394NET brd_id<0> LOC  = A13 | IOSTANDARD=LVCMOS33; #               
395NET brd_id<1> LOC  = A17 | IOSTANDARD=LVCMOS33; #               
396NET brd_id<2> LOC  = D12 | IOSTANDARD=LVCMOS33; #               
397NET brd_id<3> LOC  = N25 | IOSTANDARD=LVCMOS33; #               
398NET brd_id<4> LOC  = N26 | IOSTANDARD=LVCMOS33; #               
399NET brd_id<5> LOC  = K24 | IOSTANDARD=LVCMOS33; #               
400NET brd_id<6> LOC  = H24 | IOSTANDARD=LVCMOS33; #       
401NET brd_id<7> LOC  = Y26 | IOSTANDARD=LVCMOS33; #       
402
Note: See TracBrowser for help on using the repository browser.