source: firmware/FTM/ftm_definitions.vhd@ 10811

Last change on this file since 10811 was 10803, checked in by weitzel, 14 years ago
FTM: crate reset implemented
File size: 23.2 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
50--
51-- modified: Patrick Vogler, May 18 2011
52-- constants for light pulser and timing counter added
53--
54----------------------------------------------------------------------------------
55
56
57library IEEE;
58use IEEE.STD_LOGIC_1164.all;
59use IEEE.STD_LOGIC_ARITH.ALL;
60use IEEE.STD_LOGIC_UNSIGNED.ALL;
61use IEEE.NUMERIC_STD.ALL;
62
63package ftm_array_types is
64
65 -- !!! some arrays are also defined in the ftm_constants package !!!
66
67 -- data arrays for a single FTU
68 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
69 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
70 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
71 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
72 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
73
74 -- data array for clock conditioner interface
75 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
76
77 -- network array types
78 type ip_type is array (0 to 3) of integer;
79 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
80
81 -- Temperature Sensor interface
82 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
83
84end ftm_array_types;
85
86
87library IEEE;
88use IEEE.STD_LOGIC_1164.all;
89use IEEE.STD_LOGIC_ARITH.ALL;
90use IEEE.STD_LOGIC_UNSIGNED.ALL;
91-- for HDL-Designer
92-- LIBRARY FACT_FTM_lib;
93-- use FACT_FTM_lib.ftm_array_types.all;
94library ftm_definitions;
95use ftm_definitions.ftm_array_types.all;
96use IEEE.NUMERIC_STD.ALL;
97use ieee.math_real.all;
98
99package ftm_constants is
100
101 -- !!! many constants depend on each other or are defined 2x with different types !!!
102
103 constant NO_OF_CRATES : integer := 4;
104 constant NO_OF_FTUS_PER_CRATE : integer := 10;
105 constant NO_OF_FTU_ENABLE_REG : integer := 4;
106 constant NO_OF_FTU_DAC_REG : integer := 5;
107
108 --internal FPGA clock frequencies
109 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
110 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
111 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
112 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
113 constant SCALER_FREQ_DIVIDER : integer := 1;
114
115 --FTM address and firmware ID
116 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
117 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
118
119 --communication with FTUs
120 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
121 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
122 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
123 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
124 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
125 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
126 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
127
128 --broadcast to FADs
129 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
130 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
131
132 --CRC setup
133 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
134 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
135
136 --DNA identifier for simulation
137 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
138
139 -- Clock conditioner (LMK03000, National semiconductor) interface
140 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
141 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
142 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
143 constant LMK03000_REGISTER_WIDTH : integer := 32;
144 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
145 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
146 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
147 constant cc_R4_const : std_logic_vector := X"00000104";
148 constant cc_R5_const : std_logic_vector := X"00000105";
149 constant cc_R6_const : std_logic_vector := X"00000106";
150 constant cc_R7_const : std_logic_vector := X"00000107";
151
152 -- network settings Dortmund
153 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
154 -- constant NETMASK : ip_type := (255, 255, 255, 0);
155 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
156 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
157 -- constant FIRST_PORT : integer := 5000;
158
159 -- network settings Zuerich
160 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
161 constant NETMASK : ip_type := (255, 255, 248, 0);
162 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
163 constant GATEWAY : ip_type := (192, 33, 96, 1);
164 constant FIRST_PORT : integer := 5000;
165
166 -- W5300 settings
167 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
168 -- W5300 Registers
169 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
170 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
171 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
172 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
173 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
174 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
175 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
176 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
177 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
178 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
179 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
180 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
181 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
182 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
183 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
184 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
185 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
186 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
187 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
188 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
189 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
190 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
191 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
192 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
193 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
194 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
195 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
196 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
197 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
198 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
199 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
200 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
201 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
202 -- End W5300 registers
203 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
204 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
205 constant W5300_LAST_SOCKET : integer := 0;
206
207 -- Commands
208 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
209 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
210 constant CMD_READ : std_logic_vector := X"0001";
211 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
212 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
213 -- only for debugging: data_block (0) = ADDR
214 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
215 constant CMD_WRITE : std_logic_vector := X"0002";
216 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
217 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
218 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
219 -- ping all FTUs
220 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
221 -- turn automatic sending of dd-block and ftu-error-list on or off
222 constant CMD_AUTOSEND : std_logic_vector := X"0040";
223 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
224 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
225
226 -- start run / take X events
227 constant CMD_START : std_logic_vector := X"0004";
228 constant PAR_START_RUN : std_logic_vector := X"0001";
229 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
230
231 -- stop run
232 constant CMD_STOP : std_logic_vector := X"0008";
233
234 -- crate reset
235 constant CMD_CRESET : std_logic_vector := X"0020";
236 constant RESET_TIME : integer := 50; -- hold reset line for 1us (@ 50MHz clk)
237
238 -- start and end of package
239 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
240 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
241
242 -- package types
243 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
244 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
245 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
246 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
247 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
248
249 -- state types
250 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
251 constant FTM_STATE_CFG : std_logic_vector := X"0002";
252 constant FTM_STATE_RUN : std_logic_vector := X"0003";
253 constant FTM_STATE_CALIB : std_logic_vector := X"0004";
254
255 -- header length of data packages
256 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
257
258 -- FTU error message
259 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
260
261 -- FTU-list parameters
262 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
263 constant NO_OF_FTU_LIST_REG : integer := 6;
264 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
265 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
266
267 constant NO_OF_DD_RAM_REG : integer := 12;
268
269 -- Static data block
270 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
271 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
272 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
273 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
274 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
275 constant SD_FTU_NUM : integer := 40; -- number of FTUs
276 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
277 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
278 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
279 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002";
280
281 -- dynamic data block
282 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
283 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
284 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
285
286 -- addresses in static data block
287 constant SD_ADDR_general_settings : std_logic_vector := X"000";
288 constant SD_ADDR_led : std_logic_vector := X"001";
289 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
290 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
291 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
292 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
293 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
294 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
295 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
296 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
297 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
298 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
299 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
300 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
301 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
302 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
303 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
304 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
305 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
306 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
307 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
308 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
309 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
310 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
311 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
312 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
313 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
314 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
315 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
316 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
317 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
318 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
319 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
320 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
321 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
322 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
323 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
324
325
326 -- arrays for default values
327 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
328 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
329 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
330
331 -- general default values
332 -- !!! to be defined !!!
333 constant sd_block_default_array : sd_block_default_array_type := (
334 X"0080", -- SD_ADDR_general_settings -- general settings
335 --X"0010", -- SD_ADDR_general_settings -- general settings
336 X"0000", -- SD_ADDR_led -- on-board status LEDs
337 X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
338 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
339 X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
340 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
341 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
342 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
343 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
344 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
345 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
346 X"001E", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
347 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
348 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
349 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns
350 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
351 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
352 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
353 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
354 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
355 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
356 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
357 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
358 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
359 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
360 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
361 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
362 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
363 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
364 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
365 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
366 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
367 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
368 X"001F" -- -- Spare
369 );
370
371 -- default values for all FTUs
372 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
373 X"01FF", -- enables patch 0 board x crate y
374 X"01FF", -- enables patch 1 board x crate y
375 X"01FF", -- enables patch 2 board x crate y
376 X"01FF", -- enables patch 3 board x crate y
377 X"01F4", -- DAC_A board x crate y
378 X"01F4", -- DAC_B board x crate y
379 X"01F4", -- DAC_C board x crate y
380 X"01F4", -- DAC_D board x crate y
381 X"0010", -- DAC_H board x crate y
382 X"0001" -- Prescaling board x crate y
383 );
384
385 --default values for active FTU lists
386 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
387 X"0001",
388 X"0000",
389 X"0000",
390 X"0000"
391 );
392
393 --======================================================================================
394 -- Constants for Light pulser interface width (8ns+value*4ns)
395 --======================================================================================
396 -- constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
397 -- constant width_PLC : integer := 6; -- counter width pulse duration
398 constant FLD_PULSE_LENGTH : integer := 12;
399 constant FLD_MIN_FREQ_DIV : integer := 25;
400 constant FLD_FD_MULT : integer := 50;
401 constant FLD_FD_MAX_RANGE : integer := 64;
402
403 -- Timing counter
404 constant TC_WIDTH : integer := 48;
405 constant PRECOUNT_WIDTH : integer := 8;
406 constant PRECOUNT_DIVIDER : integer := 50;
407
408 --======================================================================================
409 -- Constants for calibration and pedestal triggers generation
410 --======================================================================================
411 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
412 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
413 constant MS_PERIOD : real := 0.001;
414 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
415 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
416 --======================================================================================
417
418 --======================================================================================
419 -- Constants for trigger and TIM signals width (8ns+value*4ns)
420 --======================================================================================
421 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
422 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
423 --======================================================================================
424
425end ftm_constants;
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