source: firmware/FTM/ftm_definitions.vhd@ 11654

Last change on this file since 11654 was 11654, checked in by weitzel, 13 years ago
two new status states introduced for FTM to indicate lock status of clock conditioner
File size: 25.2 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
50--
51-- modified: Patrick Vogler, May 18 2011
52-- constants for light pulser and timing counter added
53--
54-- modified: Patrick Vogler, May 26 2011
55-- constants for a simpler Lightpulser Interface "Basic Version" added
56--
57-- qw 16.06.: network settings for La Palma added
58--
59-- qw 29.06.: changeover to firmware v2 -> FTU reconfiguration possible during run
60--
61-- kw 10.06.: added CMD_CONFIG_FTU
62--
63-- pv 21.07.: new lightpulser firmware to reduce LED current and light output
64-- changeover to firmware v3
65--
66-- pv 25.07.: new constants for lightpulser firmware
67-- new clock conditioner interface: data only sent during configuration,
68-- when changed
69-- changeover to firmware v4
70--
71-- qw 27.07.: two new status states introduced to indicate the lock state of the
72-- clock conditioner -> changeover to firmware v5
73----------------------------------------------------------------------------------
74
75
76library IEEE;
77use IEEE.STD_LOGIC_1164.all;
78use IEEE.STD_LOGIC_ARITH.ALL;
79use IEEE.STD_LOGIC_UNSIGNED.ALL;
80use IEEE.NUMERIC_STD.ALL;
81
82package ftm_array_types is
83
84 -- !!! some arrays are also defined in the ftm_constants package !!!
85
86 -- data arrays for a single FTU
87 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
88 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
89 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
90 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
91 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
92
93 -- data array for clock conditioner interface
94 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
95
96 -- network array types
97 type ip_type is array (0 to 3) of integer;
98 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
99
100 -- Temperature Sensor interface
101 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
102
103end ftm_array_types;
104
105
106library IEEE;
107use IEEE.STD_LOGIC_1164.all;
108use IEEE.STD_LOGIC_ARITH.ALL;
109use IEEE.STD_LOGIC_UNSIGNED.ALL;
110-- for HDL-Designer
111-- LIBRARY FACT_FTM_lib;
112-- use FACT_FTM_lib.ftm_array_types.all;
113library ftm_definitions;
114use ftm_definitions.ftm_array_types.all;
115use IEEE.NUMERIC_STD.ALL;
116use ieee.math_real.all;
117
118package ftm_constants is
119
120 -- !!! many constants depend on each other or are defined 2x with different types !!!
121
122 constant NO_OF_CRATES : integer := 4;
123 constant NO_OF_FTUS_PER_CRATE : integer := 10;
124 constant NO_OF_FTU_ENABLE_REG : integer := 4;
125 constant NO_OF_FTU_DAC_REG : integer := 5;
126
127 --internal FPGA clock frequencies
128 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
129 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
130 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
131 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
132 constant SCALER_FREQ_DIVIDER : integer := 1;
133
134 --FTM address and firmware ID
135 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
136 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000101"; -- firmware version
137
138 --communication with FTUs
139 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
140 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
141 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
142 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
143 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
144 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
145 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
146
147 --broadcast to FADs
148 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
149 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
150
151 --CRC setup
152 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
153 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
154
155 --DNA identifier for simulation
156 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
157
158 -- Clock conditioner (LMK03000, National semiconductor) interface
159 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
160 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
161 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
162 constant LMK03000_REGISTER_WIDTH : integer := 32;
163 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
164 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
165 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
166 constant cc_R4_const : std_logic_vector := X"00000104";
167 constant cc_R5_const : std_logic_vector := X"00000105";
168 constant cc_R6_const : std_logic_vector := X"00000106";
169 constant cc_R7_const : std_logic_vector := X"00000107";
170
171 -- network settings Dortmund
172 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
173 -- constant NETMASK : ip_type := (255, 255, 255, 0);
174 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
175 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
176 -- constant FIRST_PORT : integer := 5000;
177
178 -- network settings Zuerich, for backup/test FTM
179 -- constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
180 -- constant NETMASK : ip_type := (255, 255, 248, 0);
181 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 246); --registered as ftmboard1.ethz.ch
182 -- constant GATEWAY : ip_type := (192, 33, 96, 1);
183 -- constant FIRST_PORT : integer := 5000;
184
185 -- network settings La Palma (internal subnet), for FTM in camera
186 constant MAC_ADDRESS : mac_type := (X"FAC7", X"1FAD", X"1102");
187 constant NETMASK : ip_type := (255, 255, 255, 0);
188 constant IP_ADDRESS : ip_type := (10, 0, 100, 140);
189 constant GATEWAY : ip_type := (10, 0, 100, 1);
190 constant FIRST_PORT : integer := 5000;
191
192 -- W5300 settings
193 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
194 -- W5300 Registers
195 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
196 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
197 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
198 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
199 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
200 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
201 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
202 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
203 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
204 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
205 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
206 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
207 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
208 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
209 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
210 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
211 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
212 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
213 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
214 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
215 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
216 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
217 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
218 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
219 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
220 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
221 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
222 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
223 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
224 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
225 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
226 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
227 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
228 -- End W5300 registers
229 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
230 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
231 constant W5300_LAST_SOCKET : integer := 0;
232
233 -- Commands
234 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
235 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
236 constant CMD_READ : std_logic_vector := X"0001";
237 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
238 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
239 -- only for debugging: data_block (0) = ADDR
240 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
241 constant CMD_WRITE : std_logic_vector := X"0002";
242 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
243 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
244 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
245 -- ping all FTUs
246 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
247 -- turn automatic sending of dd-block and ftu-error-list on or off
248 constant CMD_AUTOSEND : std_logic_vector := X"0040";
249 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
250 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
251
252 -- start run / take X events
253 constant CMD_START : std_logic_vector := X"0004";
254 constant PAR_START_RUN : std_logic_vector := X"0001";
255 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
256
257 -- stop run
258 constant CMD_STOP : std_logic_vector := X"0008";
259
260 -- crate reset
261 constant CMD_CRESET : std_logic_vector := X"0020";
262 constant RESET_TIME : integer := 50; -- hold reset line for 1us (@ 50MHz clk)
263
264 -- configure one ftu
265 constant CMD_CONFIG_FTU : std_logic_vector := X"0080";
266
267 -- start and end of package
268 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
269 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
270
271 -- package types
272 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
273 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
274 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
275 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
276 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
277
278 -- state types
279 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
280 constant FTM_STATE_CFG : std_logic_vector := X"0002";
281 constant FTM_STATE_RUN : std_logic_vector := X"0003";
282 --constant FTM_STATE_CALIB : std_logic_vector := X"0004";
283 constant FTM_STATE_IDLE_NOT_LOCKED : std_logic_vector := X"2711";
284 constant FTM_STATE_RUN_NOT_LOCKED : std_logic_vector := X"2713";
285
286 -- header length of data packages
287 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
288
289 -- FTU error message
290 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
291
292 -- FTU-list parameters
293 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
294 constant NO_OF_FTU_LIST_REG : integer := 6;
295 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
296 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
297
298 constant NO_OF_DD_RAM_REG : integer := 12;
299
300 -- Static data block
301 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
302 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
303 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
304 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
305 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
306 constant SD_FTU_NUM : integer := 40; -- number of FTUs
307 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
308 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
309 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
310 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002";
311
312 -- dynamic data block
313 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
314 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
315 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
316
317 -- addresses in static data block
318 constant SD_ADDR_general_settings : std_logic_vector := X"000";
319 constant SD_ADDR_led : std_logic_vector := X"001";
320 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
321 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
322 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
323 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
324 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
325 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
326 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
327 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
328 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
329 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
330 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
331 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
332 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
333 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
334 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
335 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
336 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
337 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
338 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
339 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
340 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
341 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
342 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
343 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
344 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
345 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
346 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
347 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
348 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
349 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
350 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
351 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
352 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
353 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
354 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
355
356
357 -- arrays for default values
358 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
359 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
360 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
361
362 -- general default values
363 -- !!! to be defined !!!
364 constant sd_block_default_array : sd_block_default_array_type := (
365 X"0080", -- SD_ADDR_general_settings -- general settings
366 --X"0010", -- SD_ADDR_general_settings -- general settings
367 X"0000", -- SD_ADDR_led -- on-board status LEDs
368 X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
369 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
370 X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
371 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
372 X"8020", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
373 X"4001", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
374 X"0000", -- SD_ADDR_lp1_delay -- light pulser 1 delay
375 X"0000", -- SD_ADDR_lp2_delay -- light pulser 2 delay
376 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
377 X"0014", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
378 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
379 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
380 X"00F8", -- SD_ADDR_dead_time -- dead time, 8ns + 4x248ns = 1000ns
381 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
382 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
383 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
384 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
385 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
386 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
387 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
388 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
389 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
390 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
391 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
392 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
393 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
394 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
395 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
396 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
397 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
398 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
399 X"001F" -- -- Spare
400 );
401
402 -- default values for all FTUs
403 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
404 X"01FF", -- enables patch 0 board x crate y
405 X"01FF", -- enables patch 1 board x crate y
406 X"01FF", -- enables patch 2 board x crate y
407 X"01FF", -- enables patch 3 board x crate y
408 X"01F4", -- DAC_A board x crate y
409 X"01F4", -- DAC_B board x crate y
410 X"01F4", -- DAC_C board x crate y
411 X"01F4", -- DAC_D board x crate y
412 X"0010", -- DAC_H board x crate y
413 X"0001" -- Prescaling board x crate y
414 );
415
416 --default values for active FTU lists
417 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
418 X"0000",
419 X"0000",
420 X"0000",
421 X"0000"
422 );
423
424 --======================================================================================
425 -- Constants for Light pulser interface width (8ns+value*4ns)
426 --======================================================================================
427 -- constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
428 -- constant width_PLC : integer := 6; -- counter width pulse duration
429 -- constant FLD_PULSE_LENGTH : integer := 12;
430 -- constant FLD_MIN_FREQ_DIV : integer := 25;
431 -- constant FLD_FD_MULT : integer := 50;
432 -- constant FLD_FD_MAX_RANGE : integer := 64;
433
434 -- --------------------------------------------------------------------------------------
435 -- Lightpulser Basic Version
436 -- --------------------------------------------------------------------------------------
437 constant FLD_PULSE_LENGTH_Pulse : integer := 2; -- 40ns pulse @ 50MHz, instead of 3: 60ns pulse @ 50MHz
438 constant FLD_PULSE_LENGTH_FM : integer := 3; -- 60ns pulse @ 50MHz
439 constant FLD_MIN_FREQ_DIV_BASIC : integer := 25; -- before 25 (8 inbetween)
440 constant FLD_FD_MULT_BASIC : integer := 10; -- before 10 (8 inbetween)
441 constant FLD_FD_MAX_RANGE_BASIC : integer := 127;-- before 64 (128 inbetween)
442
443 -- Timing counter
444 constant TC_WIDTH : integer := 48;
445 constant PRECOUNT_WIDTH : integer := 8;
446 constant PRECOUNT_DIVIDER : integer := 50;
447
448 --======================================================================================
449 -- Constants for calibration and pedestal triggers generation
450 --======================================================================================
451 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
452 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
453 constant MS_PERIOD : real := 0.001;
454 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
455 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
456 --======================================================================================
457
458 --======================================================================================
459 -- Constants for trigger and TIM signals width (8ns+value*4ns)
460 --======================================================================================
461 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
462 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
463 --======================================================================================
464
465end ftm_constants;
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