---------------------------------------------------------------------------------- -- Company: ETH Zurich, Institute for Particle Physics -- Engineer: Q. Weitzel -- -- Create Date: February 2011 -- Design Name: -- Module Name: ftm_definitions -- Project Name: -- Target Devices: -- Tool versions: -- Description: library file for FTM design -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- modified: Patrick Vogler, February 17 2011 -- merged with library file from Dortmund, Q. Weitzel, February 24, 2011 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- use IEEE.NUMERIC_STD.ALL; package ftm_array_types is -- !!! some arrays are also defined in the ftm_constants package !!! -- data arrays for a single FTU type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0); type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0); type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0); type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10; -- data array for clock conditioner interface type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0); -- network array types type ip_type is array (0 to 3) of integer; type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); end ftm_array_types; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library ftm_definitions; use ftm_definitions.ftm_array_types.all; -- use IEEE.NUMERIC_STD.ALL; package ftm_constants is -- !!! many constants depend on each other or are defined 2x with different types !!! constant NO_OF_CRATES : integer := 4; constant NO_OF_FTUS_PER_CRATE : integer := 10; constant NO_OF_FTU_ENABLE_REG : integer := 4; constant NO_OF_FTU_DAC_REG : integer := 5; --internal FPGA clock frequencies constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz --FTM address and firmware ID constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version --communication with FTUs constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods) constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!! constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@" --CRC setup constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111"; --DNA identifier for simulation constant DNA_FOR_SIM : bit_vector := X"01710000E0000501"; -- Clock conditioner (LMK03000, National semiconductor) interface constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000"; constant LMK03000_REGISTER_WIDTH : integer := 32; constant LMK03000_REGISTER_COUNT : integer := 9; -- number of registers to be programmed in the LMK03000 including reset -- network settings Dortmund -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0"); -- constant NETMASK : ip_type := (255, 255, 255, 0); -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118); -- constant GATEWAY : ip_type := (129, 217, 160, 1); -- constant FIRST_PORT : integer := 5000; -- network settings Zuerich constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101"); constant NETMASK : ip_type := (255, 255, 248, 0); constant IP_ADDRESS : ip_type := (192, 33, 99, 246); constant GATEWAY : ip_type := (192, 33, 96, 1); constant FIRST_PORT : integer := 5000; -- W5300 settings constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset -- W5300 Registers constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; -- End W5300 registers constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words constant W5300_LAST_SOCKET : integer := 0; -- Commands constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@" constant CMD_TLED : std_logic_vector := X"C000"; -- only a test constant CMD_READ : std_logic_vector := X"0001"; constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block -- only for debugging: data_block (0) = ADDR constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block constant CMD_WRITE : std_logic_vector := X"0002"; constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram -- ping all FTUs constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs -- FTU-list parameters constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) =249 constant NO_OF_FTU_LIST_REG : integer := 6; constant FTU_LIST_RAM_OFFSET : integer := 16#009#; constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; -- Static data block constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#; constant STATIC_RAM_ADDR_WIDTH : integer := 12; constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block constant SD_FTU_NUM : integer := 40; -- number of FTUs constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block -- addresses in static data block constant SD_ADDR_general_settings : std_logic_vector := X"000"; constant SD_ADDR_led : std_logic_vector := X"001"; constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002"; constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003"; constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004"; constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005"; constant SD_ADDR_lp1_delay : std_logic_vector := X"006"; constant SD_ADDR_lp2_delay : std_logic_vector := X"007"; constant SD_ADDR_coin_n_p : std_logic_vector := X"008"; constant SD_ADDR_coin_n_c : std_logic_vector := X"009"; constant SD_ADDR_trigger_delay : std_logic_vector := X"00A"; constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B"; constant SD_ADDR_dead_time : std_logic_vector := X"00C"; constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D"; constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E"; constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F"; constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010"; constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011"; constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012"; constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013"; constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014"; constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015"; constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016"; constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017"; constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018"; constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019"; constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A"; constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B"; constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C"; constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2"; constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3"; constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#; -- arrays for default values type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0); type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0); -- general default values -- !!! to be defined !!! constant sd_block_default_array : sd_block_default_array_type := ( X"0000", -- SD_ADDR_general_settings -- general settings X"0000", -- SD_ADDR_led -- on-board status LEDs X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics) X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration) X"000A", -- SD_ADDR_trigger_delay -- trigger delay X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay X"000C", -- SD_ADDR_dead_time -- dead time X"000D", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 X"000E", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 X"000F", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16 X"0010", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0 X"0011", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16 X"0012", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0 X"0013", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16 X"0014", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0 X"0015", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16 X"0016", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0 X"0017", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16 X"0018", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0 X"0019", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16 X"001A", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0 X"001B", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16 X"001C", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0 X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics) X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration) X"001F" -- -- Spare ); -- default values for all FTUs constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := ( X"01FF", -- enables patch 0 board x crate y X"01FF", -- enables patch 1 board x crate y X"01FF", -- enables patch 2 board x crate y X"01FF", -- enables patch 3 board x crate y X"01F4", -- DAC_A board x crate y X"01F4", -- DAC_B board x crate y X"01F4", -- DAC_C board x crate y X"01F4", -- DAC_D board x crate y X"0010", -- DAC_H board x crate y X"0001" -- Prescaling board x crate y ); end ftm_constants;