1 | ----------------------------------------------------------------------------------
|
---|
2 | -- Company: ETH Zurich, Institute for Particle Physics
|
---|
3 | -- Engineer: Q. Weitzel
|
---|
4 | --
|
---|
5 | -- Create Date: February 2011
|
---|
6 | -- Design Name:
|
---|
7 | -- Module Name: ftm_definitions
|
---|
8 | -- Project Name:
|
---|
9 | -- Target Devices:
|
---|
10 | -- Tool versions:
|
---|
11 | -- Description: library file for FTM design
|
---|
12 | --
|
---|
13 | -- Dependencies:
|
---|
14 | --
|
---|
15 | -- Revision:
|
---|
16 | -- Revision 0.01 - File Created
|
---|
17 | -- Additional Comments:
|
---|
18 | --
|
---|
19 | -- modified: Patrick Vogler, February 17 2011
|
---|
20 | ----------------------------------------------------------------------------------
|
---|
21 |
|
---|
22 |
|
---|
23 | library IEEE;
|
---|
24 | use IEEE.STD_LOGIC_1164.all;
|
---|
25 | use IEEE.STD_LOGIC_ARITH.ALL;
|
---|
26 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
---|
27 | -- use IEEE.NUMERIC_STD.ALL;
|
---|
28 |
|
---|
29 | package ftm_array_types is
|
---|
30 |
|
---|
31 | -- data arrays for a single FTU
|
---|
32 | type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
|
---|
33 | type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
|
---|
34 | type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
|
---|
35 | type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
|
---|
36 | type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
|
---|
37 |
|
---|
38 | -- data array for clock conditioner interface
|
---|
39 | type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0);
|
---|
40 |
|
---|
41 | end ftm_array_types;
|
---|
42 |
|
---|
43 |
|
---|
44 | library IEEE;
|
---|
45 | use IEEE.STD_LOGIC_1164.all;
|
---|
46 | use IEEE.STD_LOGIC_ARITH.ALL;
|
---|
47 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
---|
48 | -- use IEEE.NUMERIC_STD.ALL;
|
---|
49 |
|
---|
50 | package ftm_constants is
|
---|
51 |
|
---|
52 | constant NO_OF_CRATES : integer := 4;
|
---|
53 | constant NO_OF_FTUS_PER_CRATE : integer := 10;
|
---|
54 | constant NO_OF_FTU_ENABLE_REG : integer := 4;
|
---|
55 | constant NO_OF_FTU_DAC_REG : integer := 5;
|
---|
56 | constant NO_OF_FTU_LIST_REG : integer := 6;
|
---|
57 |
|
---|
58 | --internal FPGA clock frequencies
|
---|
59 | constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
|
---|
60 | constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
|
---|
61 |
|
---|
62 | --FTM address and firmware ID
|
---|
63 | constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
|
---|
64 | constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
|
---|
65 |
|
---|
66 | --communication with FTUs
|
---|
67 | constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
|
---|
68 | constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
|
---|
69 | constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
|
---|
70 | constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
|
---|
71 | constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
|
---|
72 |
|
---|
73 | --CRC setup
|
---|
74 | constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
|
---|
75 | constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
|
---|
76 |
|
---|
77 | --DNA identifier for simulation
|
---|
78 | constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";
|
---|
79 |
|
---|
80 | --RAM address offsets and widths
|
---|
81 | constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
|
---|
82 | constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
|
---|
83 | constant STATIC_RAM_ADDR_WIDTH : integer := 12;
|
---|
84 | constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
|
---|
85 | constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
|
---|
86 |
|
---|
87 |
|
---|
88 |
|
---|
89 | -- Clock conditioner (LMK03000, National semiconductor) interface
|
---|
90 | constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
|
---|
91 | constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
|
---|
92 | -- value to be written to R0 of the LMK03000 to perform a reset
|
---|
93 | -- see LMK03000 datasheet
|
---|
94 | constant LMK03000_REGISTER_WIDTH : integer := 32;
|
---|
95 | constant LMK03000_REGISTER_COUNT : integer := 9; -- number of registers to
|
---|
96 | -- be programmed in the
|
---|
97 | -- LMK03000 including reset
|
---|
98 |
|
---|
99 |
|
---|
100 |
|
---|
101 |
|
---|
102 |
|
---|
103 | end ftm_constants;
|
---|