source: firmware/FTM/ftm_definitions.vhd@ 10179

Last change on this file since 10179 was 10179, checked in by vogler, 11 years ago
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21----------------------------------------------------------------------------------
22
23
24library IEEE;
25use IEEE.STD_LOGIC_1164.all;
26use IEEE.STD_LOGIC_ARITH.ALL;
27use IEEE.STD_LOGIC_UNSIGNED.ALL;
28-- use IEEE.NUMERIC_STD.ALL;
29
30package ftm_array_types is
31
32 -- !!! some arrays are also defined in the ftm_constants package !!!
33
34 -- data arrays for a single FTU
35 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
36 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
37 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
38 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
39 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
40
41 -- data array for clock conditioner interface
42 type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0);
43
44 -- network array types
45 type ip_type is array (0 to 3) of integer;
46 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
47
48end ftm_array_types;
49
50
51library IEEE;
52use IEEE.STD_LOGIC_1164.all;
53use IEEE.STD_LOGIC_ARITH.ALL;
54use IEEE.STD_LOGIC_UNSIGNED.ALL;
55library ftm_definitions;
56use ftm_definitions.ftm_array_types.all;
57-- use IEEE.NUMERIC_STD.ALL;
58
59package ftm_constants is
60
61 -- !!! many constants depend on each other or are defined 2x with different types !!!
62
63 constant NO_OF_CRATES : integer := 4;
64 constant NO_OF_FTUS_PER_CRATE : integer := 10;
65 constant NO_OF_FTU_ENABLE_REG : integer := 4;
66 constant NO_OF_FTU_DAC_REG : integer := 5;
67
68 --internal FPGA clock frequencies
69 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
70 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
71
72 --FTM address and firmware ID
73 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
74 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
75
76 --communication with FTUs
77 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
78 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
79 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
80 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
81 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
82
83 --CRC setup
84 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
85 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
86
87 --DNA identifier for simulation
88 constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";
89
90 -- Clock conditioner (LMK03000, National semiconductor) interface
91 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
92 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
93 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
94 constant LMK03000_REGISTER_WIDTH : integer := 32;
95 constant LMK03000_REGISTER_COUNT : integer := 9; -- number of registers to be programmed in the LMK03000 including reset
96
97 -- network settings Dortmund
98 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
99 -- constant NETMASK : ip_type := (255, 255, 255, 0);
100 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
101 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
102 -- constant FIRST_PORT : integer := 5000;
103
104 -- network settings Zuerich
105 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
106 constant NETMASK : ip_type := (255, 255, 248, 0);
107 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
108 constant GATEWAY : ip_type := (192, 33, 96, 1);
109 constant FIRST_PORT : integer := 5000;
110
111 -- W5300 settings
112 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
113 -- W5300 Registers
114 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
115 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
116 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
117 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
118 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
119 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
120 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
121 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
122 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
123 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
124 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
125 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
126 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
127 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
128 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
129 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
130 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
131 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
132 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
133 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
134 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
135 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
136 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
137 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
138 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
139 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
140 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
141 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
142 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
143 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
144 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
145 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
146 -- End W5300 registers
147 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
148 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
149 constant W5300_LAST_SOCKET : integer := 0;
150
151 -- Commands
152 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
153 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
154 constant CMD_READ : std_logic_vector := X"0001";
155 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
156 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
157 -- only for debugging: data_block (0) = ADDR
158 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
159 constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block
160 constant CMD_WRITE : std_logic_vector := X"0002";
161 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
162 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
163 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram
164 -- ping all FTUs
165 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
166
167 -- FTU-list parameters
168 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) =249
169 constant NO_OF_FTU_LIST_REG : integer := 6;
170 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
171 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
172
173 -- Static data block
174 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
175 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
176 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
177 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
178 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
179 constant SD_FTU_NUM : integer := 40; -- number of FTUs
180 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
181 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
182 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
183
184 -- addresses in static data block
185 constant SD_ADDR_general_settings : std_logic_vector := X"000";
186 constant SD_ADDR_led : std_logic_vector := X"001";
187 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
188 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
189 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
190 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
191 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
192 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
193 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
194 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
195 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
196 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
197 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
198 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
199 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
200 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
201 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
202 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
203 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
204 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
205 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
206 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
207 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
208 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
209 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
210 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
211 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
212 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
213 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
214 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
215 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
216 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
217 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
218 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
219
220 -- arrays for default values
221 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
222 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
223
224 -- general default values
225 -- !!! to be defined !!!
226 constant sd_block_default_array : sd_block_default_array_type := (
227 X"0000", -- SD_ADDR_general_settings -- general settings
228 X"0000", -- SD_ADDR_led -- on-board status LEDs
229 X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
230 X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
231 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
232 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
233 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
234 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
235 X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
236 X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
237 X"000A", -- SD_ADDR_trigger_delay -- trigger delay
238 X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay
239 X"000C", -- SD_ADDR_dead_time -- dead time
240 X"000D", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
241 X"000E", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
242 X"000F", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
243 X"0010", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
244 X"0011", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
245 X"0012", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
246 X"0013", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
247 X"0014", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
248 X"0015", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
249 X"0016", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
250 X"0017", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
251 X"0018", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
252 X"0019", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
253 X"001A", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
254 X"001B", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
255 X"001C", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
256 X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics)
257 X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration)
258 X"001F" -- -- Spare
259 );
260
261 -- default values for all FTUs
262 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
263 X"01FF", -- enables patch 0 board x crate y
264 X"01FF", -- enables patch 1 board x crate y
265 X"01FF", -- enables patch 2 board x crate y
266 X"01FF", -- enables patch 3 board x crate y
267 X"01F4", -- DAC_A board x crate y
268 X"01F4", -- DAC_B board x crate y
269 X"01F4", -- DAC_C board x crate y
270 X"01F4", -- DAC_D board x crate y
271 X"0010", -- DAC_H board x crate y
272 X"0001" -- Prescaling board x crate y
273 );
274
275end ftm_constants;
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