source: firmware/FTM/ftm_definitions.vhd@ 10229

Last change on this file since 10229 was 10229, checked in by vogler, 10 years ago
constant for Lightpulser interface added
File size: 16.7 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24----------------------------------------------------------------------------------
25
26
27library IEEE;
28use IEEE.STD_LOGIC_1164.all;
29use IEEE.STD_LOGIC_ARITH.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31-- use IEEE.NUMERIC_STD.ALL;
32
33package ftm_array_types is
34
35 -- !!! some arrays are also defined in the ftm_constants package !!!
36
37 -- data arrays for a single FTU
38 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
39 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
40 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
41 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
42 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
43
44 -- data array for clock conditioner interface
45 type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0);
46
47 -- network array types
48 type ip_type is array (0 to 3) of integer;
49 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
50
51end ftm_array_types;
52
53
54library IEEE;
55use IEEE.STD_LOGIC_1164.all;
56use IEEE.STD_LOGIC_ARITH.ALL;
57use IEEE.STD_LOGIC_UNSIGNED.ALL;
58-- for HDL-Designer
59-- LIBRARY FACT_FTM_lib;
60-- use FACT_FTM_lib.ftm_array_types.all;
61library ftm_definitions;
62use ftm_definitions.ftm_array_types.all;
63use IEEE.NUMERIC_STD.ALL;
64
65package ftm_constants is
66
67 -- !!! many constants depend on each other or are defined 2x with different types !!!
68
69 constant NO_OF_CRATES : integer := 4;
70 constant NO_OF_FTUS_PER_CRATE : integer := 10;
71 constant NO_OF_FTU_ENABLE_REG : integer := 4;
72 constant NO_OF_FTU_DAC_REG : integer := 5;
73
74 --internal FPGA clock frequencies
75 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
76 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
77 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
78
79 --FTM address and firmware ID
80 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
81 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
82
83 --communication with FTUs
84 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
85 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
86 -- constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
87 -- constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
88 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
89 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
90 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
91
92 --CRC setup
93 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
94 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
95
96 --DNA identifier for simulation
97 constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";
98
99 -- Clock conditioner (LMK03000, National semiconductor) interface
100 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
101 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
102 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
103 constant LMK03000_REGISTER_WIDTH : integer := 32;
104 constant LMK03000_REGISTER_COUNT : integer := 9; -- number of registers to be programmed in the LMK03000 including reset
105
106 -- network settings Dortmund
107 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
108 -- constant NETMASK : ip_type := (255, 255, 255, 0);
109 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
110 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
111 -- constant FIRST_PORT : integer := 5000;
112
113 -- network settings Zuerich
114 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
115 constant NETMASK : ip_type := (255, 255, 248, 0);
116 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
117 constant GATEWAY : ip_type := (192, 33, 96, 1);
118 constant FIRST_PORT : integer := 5000;
119
120 -- W5300 settings
121 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
122 -- W5300 Registers
123 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
124 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
125 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
126 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
127 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
128 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
129 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
130 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
131 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
132 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
133 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
134 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
135 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
136 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
137 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
138 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
139 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
140 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
141 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
142 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
143 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
144 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
145 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
146 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
147 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
148 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
149 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
150 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
151 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
152 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
153 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
154 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
155 -- End W5300 registers
156 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
157 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
158 constant W5300_LAST_SOCKET : integer := 0;
159
160 -- Commands
161 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
162 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
163 constant CMD_READ : std_logic_vector := X"0001";
164 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
165 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
166 -- only for debugging: data_block (0) = ADDR
167 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
168 constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block
169 constant CMD_WRITE : std_logic_vector := X"0002";
170 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
171 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
172 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram
173 -- ping all FTUs
174 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
175
176 -- FTU-list parameters
177 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
178 constant NO_OF_FTU_LIST_REG : integer := 6;
179 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
180 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
181
182 -- Static data block
183 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
184 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
185 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
186 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
187 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
188 constant SD_FTU_NUM : integer := 40; -- number of FTUs
189 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
190 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
191 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
192
193 -- dynamic data block
194 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"008"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block
195
196 -- addresses in static data block
197 constant SD_ADDR_general_settings : std_logic_vector := X"000";
198 constant SD_ADDR_led : std_logic_vector := X"001";
199 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
200 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
201 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
202 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
203 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
204 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
205 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
206 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
207 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
208 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
209 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
210 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
211 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
212 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
213 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
214 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
215 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
216 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
217 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
218 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
219 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
220 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
221 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
222 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
223 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
224 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
225 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
226 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
227 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
228 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
229 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
230 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
231 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
232 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
233
234 -- arrays for default values
235 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
236 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
237 type sd_block_activeFTUlist_default_array_type is array (0 to (NO_OF_CRATES - 1)) of std_logic_vector (15 downto 0);
238
239 -- general default values
240 -- !!! to be defined !!!
241 constant sd_block_default_array : sd_block_default_array_type := (
242 X"0000", -- SD_ADDR_general_settings -- general settings
243 X"0000", -- SD_ADDR_led -- on-board status LEDs
244 X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
245 X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
246 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
247 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
248 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
249 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
250 X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
251 X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
252 X"000A", -- SD_ADDR_trigger_delay -- trigger delay
253 X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay
254 X"000C", -- SD_ADDR_dead_time -- dead time
255 X"000D", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
256 X"000E", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
257 X"000F", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
258 X"0010", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
259 X"0011", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
260 X"0012", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
261 X"0013", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
262 X"0014", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
263 X"0015", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
264 X"0016", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
265 X"0017", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
266 X"0018", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
267 X"0019", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
268 X"001A", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
269 X"001B", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
270 X"001C", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
271 X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics)
272 X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration)
273 X"001F" -- -- Spare
274 );
275
276 -- default values for all FTUs
277 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
278 X"01FF", -- enables patch 0 board x crate y
279 X"01FF", -- enables patch 1 board x crate y
280 X"01FF", -- enables patch 2 board x crate y
281 X"01FF", -- enables patch 3 board x crate y
282 X"01F4", -- DAC_A board x crate y
283 X"01F4", -- DAC_B board x crate y
284 X"01F4", -- DAC_C board x crate y
285 X"01F4", -- DAC_D board x crate y
286 X"0010", -- DAC_H board x crate y
287 X"0001" -- Prescaling board x crate y
288 );
289
290 --default values for active FTU lists
291 constant sd_block_activeFTUlist_default_array : sd_block_activeFTUlist_default_array_type := (
292 X"0001",
293 X"0000",
294 X"0000",
295 X"0000"
296 );
297
298 -- Light pulser interface
299 constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
300 constant width_PLC : integer := 6; -- counter width pulse duration
301
302end ftm_constants;
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