1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: ETH Zurich, Institute for Particle Physics |
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3 | -- Engineer: Q. Weitzel |
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4 | -- |
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5 | -- Create Date: February 2011 |
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6 | -- Design Name: |
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7 | -- Module Name: ftm_definitions |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: library file for FTM design |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | -- modified: Patrick Vogler, February 17 2011 |
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20 | -- merged with library file from Dortmund, Q. Weitzel, February 24, 2011 |
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21 | -- |
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22 | -- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...), |
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23 | -- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined |
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24 | ---------------------------------------------------------------------------------- |
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25 | |
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26 | |
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27 | library IEEE; |
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28 | use IEEE.STD_LOGIC_1164.all; |
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29 | use IEEE.STD_LOGIC_ARITH.ALL; |
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30 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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31 | -- use IEEE.NUMERIC_STD.ALL; |
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32 | |
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33 | package ftm_array_types is |
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34 | |
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35 | -- !!! some arrays are also defined in the ftm_constants package !!! |
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36 | |
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37 | -- data arrays for a single FTU |
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38 | type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0); |
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39 | type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0); |
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40 | type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0); |
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41 | type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0); |
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42 | type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10; |
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43 | |
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44 | -- data array for clock conditioner interface |
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45 | type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0); |
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46 | |
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47 | -- network array types |
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48 | type ip_type is array (0 to 3) of integer; |
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49 | type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); |
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50 | |
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51 | end ftm_array_types; |
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52 | |
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53 | |
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54 | library IEEE; |
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55 | use IEEE.STD_LOGIC_1164.all; |
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56 | use IEEE.STD_LOGIC_ARITH.ALL; |
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57 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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58 | -- for HDL-Designer |
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59 | -- LIBRARY FACT_FTM_lib; |
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60 | -- use FACT_FTM_lib.ftm_array_types.all; |
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61 | library ftm_definitions; |
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62 | use ftm_definitions.ftm_array_types.all; |
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63 | use IEEE.NUMERIC_STD.ALL; |
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64 | |
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65 | package ftm_constants is |
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66 | |
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67 | -- !!! many constants depend on each other or are defined 2x with different types !!! |
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68 | |
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69 | constant NO_OF_CRATES : integer := 4; |
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70 | constant NO_OF_FTUS_PER_CRATE : integer := 10; |
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71 | constant NO_OF_FTU_ENABLE_REG : integer := 4; |
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72 | constant NO_OF_FTU_DAC_REG : integer := 5; |
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73 | |
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74 | --internal FPGA clock frequencies |
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75 | constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz |
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76 | constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz |
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77 | constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1 |
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78 | |
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79 | --FTM address and firmware ID |
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80 | constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 |
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81 | constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version |
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82 | |
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83 | --communication with FTUs |
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84 | constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case |
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85 | constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods) |
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86 | -- constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation |
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87 | -- constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation |
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88 | constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!! |
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89 | constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol |
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90 | constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@" |
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91 | |
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92 | --CRC setup |
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93 | constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT |
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94 | constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111"; |
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95 | |
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96 | --DNA identifier for simulation |
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97 | constant DNA_FOR_SIM : bit_vector := X"01710000E0000501"; |
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98 | |
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99 | -- Clock conditioner (LMK03000, National semiconductor) interface |
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100 | constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz |
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101 | -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet |
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102 | constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000"; |
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103 | constant LMK03000_REGISTER_WIDTH : integer := 32; |
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104 | constant LMK03000_REGISTER_COUNT : integer := 9; -- number of registers to be programmed in the LMK03000 including reset |
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105 | |
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106 | -- network settings Dortmund |
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107 | -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0"); |
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108 | -- constant NETMASK : ip_type := (255, 255, 255, 0); |
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109 | -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118); |
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110 | -- constant GATEWAY : ip_type := (129, 217, 160, 1); |
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111 | -- constant FIRST_PORT : integer := 5000; |
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112 | |
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113 | -- network settings Zuerich |
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114 | constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101"); |
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115 | constant NETMASK : ip_type := (255, 255, 248, 0); |
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116 | constant IP_ADDRESS : ip_type := (192, 33, 99, 246); |
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117 | constant GATEWAY : ip_type := (192, 33, 96, 1); |
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118 | constant FIRST_PORT : integer := 5000; |
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119 | |
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120 | -- W5300 settings |
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121 | constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset |
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122 | -- W5300 Registers |
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123 | constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0'); |
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124 | constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0"; |
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125 | constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2"; |
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126 | constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4"; |
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127 | constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8"; |
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128 | constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10"; |
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129 | constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; |
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130 | constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; |
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131 | constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; |
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132 | constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; |
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133 | constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; |
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134 | constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; |
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135 | constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24"; |
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136 | constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26"; |
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137 | constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28"; |
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138 | constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A"; |
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139 | constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C"; |
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140 | constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E"; |
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141 | constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30"; |
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142 | constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0"; |
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143 | constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2"; |
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144 | constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4"; |
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145 | constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6"; |
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146 | constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8"; |
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147 | constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A"; |
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148 | constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; |
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149 | constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; |
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150 | constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; |
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151 | constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; |
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152 | constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28"; |
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153 | constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E"; |
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154 | constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30"; |
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155 | -- End W5300 registers |
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156 | constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes |
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157 | constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words |
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158 | constant W5300_LAST_SOCKET : integer := 0; |
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159 | |
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160 | -- Commands |
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161 | constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@" |
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162 | constant CMD_TLED : std_logic_vector := X"C000"; -- only a test |
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163 | constant CMD_READ : std_logic_vector := X"0001"; |
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164 | constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block |
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165 | constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block |
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166 | -- only for debugging: data_block (0) = ADDR |
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167 | constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block |
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168 | constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block |
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169 | constant CMD_WRITE : std_logic_vector := X"0002"; |
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170 | constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block |
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171 | -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA |
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172 | constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram |
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173 | -- ping all FTUs |
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174 | constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs |
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175 | |
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176 | -- FTU-list parameters |
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177 | constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249 |
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178 | constant NO_OF_FTU_LIST_REG : integer := 6; |
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179 | constant FTU_LIST_RAM_OFFSET : integer := 16#009#; |
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180 | constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; |
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181 | |
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182 | -- Static data block |
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183 | constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data |
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184 | constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data |
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185 | constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#; |
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186 | constant STATIC_RAM_ADDR_WIDTH : integer := 12; |
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187 | constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block |
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188 | constant SD_FTU_NUM : integer := 40; -- number of FTUs |
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189 | constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists |
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190 | constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) |
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191 | constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block |
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192 | |
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193 | -- dynamic data block |
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194 | constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"008"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block |
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195 | |
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196 | -- addresses in static data block |
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197 | constant SD_ADDR_general_settings : std_logic_vector := X"000"; |
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198 | constant SD_ADDR_led : std_logic_vector := X"001"; |
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199 | constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002"; |
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200 | constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003"; |
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201 | constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004"; |
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202 | constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005"; |
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203 | constant SD_ADDR_lp1_delay : std_logic_vector := X"006"; |
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204 | constant SD_ADDR_lp2_delay : std_logic_vector := X"007"; |
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205 | constant SD_ADDR_coin_n_p : std_logic_vector := X"008"; |
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206 | constant SD_ADDR_coin_n_c : std_logic_vector := X"009"; |
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207 | constant SD_ADDR_trigger_delay : std_logic_vector := X"00A"; |
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208 | constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B"; |
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209 | constant SD_ADDR_dead_time : std_logic_vector := X"00C"; |
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210 | constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D"; |
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211 | constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E"; |
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212 | constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F"; |
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213 | constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010"; |
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214 | constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011"; |
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215 | constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012"; |
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216 | constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013"; |
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217 | constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014"; |
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218 | constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015"; |
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219 | constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016"; |
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220 | constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017"; |
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221 | constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018"; |
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222 | constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019"; |
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223 | constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A"; |
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224 | constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B"; |
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225 | constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C"; |
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226 | constant SD_ADDR_coin_win_p : std_logic_vector := X"01D"; |
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227 | constant SD_ADDR_coin_win_c : std_logic_vector := X"01E"; |
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228 | constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; |
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229 | constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; |
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230 | constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2"; |
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231 | constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3"; |
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232 | constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#; |
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233 | |
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234 | -- arrays for default values |
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235 | type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0); |
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236 | type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0); |
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237 | type sd_block_activeFTUlist_default_array_type is array (0 to (NO_OF_CRATES - 1)) of std_logic_vector (15 downto 0); |
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238 | |
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239 | -- general default values |
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240 | -- !!! to be defined !!! |
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241 | constant sd_block_default_array : sd_block_default_array_type := ( |
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242 | X"0000", -- SD_ADDR_general_settings -- general settings |
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243 | X"0000", -- SD_ADDR_led -- on-board status LEDs |
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244 | X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency |
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245 | X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers |
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246 | X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude |
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247 | X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude |
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248 | X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay |
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249 | X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay |
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250 | X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics) |
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251 | X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration) |
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252 | X"000A", -- SD_ADDR_trigger_delay -- trigger delay |
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253 | X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay |
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254 | X"000C", -- SD_ADDR_dead_time -- dead time |
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255 | X"000D", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 |
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256 | X"000E", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 |
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257 | X"000F", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16 |
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258 | X"0010", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0 |
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259 | X"0011", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16 |
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260 | X"0012", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0 |
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261 | X"0013", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16 |
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262 | X"0014", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0 |
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263 | X"0015", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16 |
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264 | X"0016", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0 |
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265 | X"0017", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16 |
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266 | X"0018", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0 |
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267 | X"0019", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16 |
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268 | X"001A", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0 |
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269 | X"001B", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16 |
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270 | X"001C", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0 |
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271 | X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics) |
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272 | X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration) |
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273 | X"001F" -- -- Spare |
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274 | ); |
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275 | |
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276 | -- default values for all FTUs |
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277 | constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := ( |
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278 | X"01FF", -- enables patch 0 board x crate y |
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279 | X"01FF", -- enables patch 1 board x crate y |
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280 | X"01FF", -- enables patch 2 board x crate y |
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281 | X"01FF", -- enables patch 3 board x crate y |
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282 | X"01F4", -- DAC_A board x crate y |
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283 | X"01F4", -- DAC_B board x crate y |
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284 | X"01F4", -- DAC_C board x crate y |
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285 | X"01F4", -- DAC_D board x crate y |
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286 | X"0010", -- DAC_H board x crate y |
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287 | X"0001" -- Prescaling board x crate y |
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288 | ); |
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289 | |
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290 | --default values for active FTU lists |
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291 | constant sd_block_activeFTUlist_default_array : sd_block_activeFTUlist_default_array_type := ( |
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292 | X"0001", |
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293 | X"0000", |
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294 | X"0000", |
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295 | X"0000" |
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296 | ); |
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297 | |
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298 | -- Light pulser interface |
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299 | constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns |
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300 | constant width_PLC : integer := 6; -- counter width pulse duration |
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301 | |
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302 | end ftm_constants; |
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