source: firmware/FTM/ftm_definitions.vhd@ 10697

Last change on this file since 10697 was 10639, checked in by weitzel, 14 years ago
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
File size: 22.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
50--
51----------------------------------------------------------------------------------
52
53
54library IEEE;
55use IEEE.STD_LOGIC_1164.all;
56use IEEE.STD_LOGIC_ARITH.ALL;
57use IEEE.STD_LOGIC_UNSIGNED.ALL;
58use IEEE.NUMERIC_STD.ALL;
59
60package ftm_array_types is
61
62 -- !!! some arrays are also defined in the ftm_constants package !!!
63
64 -- data arrays for a single FTU
65 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
66 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
67 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
68 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
69 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
70
71 -- data array for clock conditioner interface
72 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
73
74 -- network array types
75 type ip_type is array (0 to 3) of integer;
76 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
77
78 -- Temperature Sensor interface
79 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
80
81end ftm_array_types;
82
83
84library IEEE;
85use IEEE.STD_LOGIC_1164.all;
86use IEEE.STD_LOGIC_ARITH.ALL;
87use IEEE.STD_LOGIC_UNSIGNED.ALL;
88-- for HDL-Designer
89-- LIBRARY FACT_FTM_lib;
90-- use FACT_FTM_lib.ftm_array_types.all;
91library ftm_definitions;
92use ftm_definitions.ftm_array_types.all;
93use IEEE.NUMERIC_STD.ALL;
94use ieee.math_real.all;
95
96package ftm_constants is
97
98 -- !!! many constants depend on each other or are defined 2x with different types !!!
99
100 constant NO_OF_CRATES : integer := 4;
101 constant NO_OF_FTUS_PER_CRATE : integer := 10;
102 constant NO_OF_FTU_ENABLE_REG : integer := 4;
103 constant NO_OF_FTU_DAC_REG : integer := 5;
104
105 --internal FPGA clock frequencies
106 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
107 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
108 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
109 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
110 constant SCALER_FREQ_DIVIDER : integer := 1;
111
112 --FTM address and firmware ID
113 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
114 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
115
116 --communication with FTUs
117 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
118 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
119 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
120 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
121 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
122 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
123 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
124
125 --broadcast to FADs
126 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
127 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
128
129 --CRC setup
130 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
131 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
132
133 --DNA identifier for simulation
134 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
135
136 -- Clock conditioner (LMK03000, National semiconductor) interface
137 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
138 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
139 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
140 constant LMK03000_REGISTER_WIDTH : integer := 32;
141 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
142 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
143 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
144 constant cc_R4_const : std_logic_vector := X"00000104";
145 constant cc_R5_const : std_logic_vector := X"00000105";
146 constant cc_R6_const : std_logic_vector := X"00000106";
147 constant cc_R7_const : std_logic_vector := X"00000107";
148
149 -- network settings Dortmund
150 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
151 -- constant NETMASK : ip_type := (255, 255, 255, 0);
152 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
153 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
154 -- constant FIRST_PORT : integer := 5000;
155
156 -- network settings Zuerich
157 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
158 constant NETMASK : ip_type := (255, 255, 248, 0);
159 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
160 constant GATEWAY : ip_type := (192, 33, 96, 1);
161 constant FIRST_PORT : integer := 5000;
162
163 -- W5300 settings
164 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
165 -- W5300 Registers
166 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
167 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
168 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
169 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
170 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
171 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
172 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
173 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
174 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
175 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
176 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
177 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
178 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
179 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
180 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
181 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
182 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
183 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
184 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
185 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
186 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
187 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
188 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
189 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
190 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
191 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
192 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
193 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
194 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
195 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
196 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
197 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
198 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
199 -- End W5300 registers
200 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
201 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
202 constant W5300_LAST_SOCKET : integer := 0;
203
204 -- Commands
205 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
206 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
207 constant CMD_READ : std_logic_vector := X"0001";
208 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
209 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
210 -- only for debugging: data_block (0) = ADDR
211 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
212 constant CMD_WRITE : std_logic_vector := X"0002";
213 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
214 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
215 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
216 -- ping all FTUs
217 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
218 -- turn automatic sending of dd-block and ftu-error-list on or off
219 constant CMD_AUTOSEND : std_logic_vector := X"0040";
220 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
221 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
222
223 -- start run / take X events
224 constant CMD_START : std_logic_vector := X"0004";
225 constant PAR_START_RUN : std_logic_vector := X"0001";
226 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
227
228 -- stop run
229 constant CMD_STOP : std_logic_vector := X"0008";
230
231 -- crate reset
232 constant CMD_CRESET : std_logic_vector := X"0020";
233
234 -- start and end of package
235 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
236 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
237
238 -- package types
239 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
240 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
241 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
242 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
243 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
244
245 -- state types
246 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
247 constant FTM_STATE_CFG : std_logic_vector := X"0002";
248 constant FTM_STATE_RUN : std_logic_vector := X"0003";
249 constant FTM_STATE_CALIB : std_logic_vector := X"0004";
250
251 -- header length of data packages
252 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
253
254 -- FTU error message
255 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
256
257 -- FTU-list parameters
258 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
259 constant NO_OF_FTU_LIST_REG : integer := 6;
260 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
261 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
262
263 constant NO_OF_DD_RAM_REG : integer := 12;
264
265 -- Static data block
266 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
267 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
268 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
269 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
270 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
271 constant SD_FTU_NUM : integer := 40; -- number of FTUs
272 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
273 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
274 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
275 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002";
276
277 -- dynamic data block
278 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
279 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
280 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
281
282 -- addresses in static data block
283 constant SD_ADDR_general_settings : std_logic_vector := X"000";
284 constant SD_ADDR_led : std_logic_vector := X"001";
285 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
286 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
287 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
288 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
289 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
290 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
291 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
292 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
293 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
294 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
295 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
296 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
297 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
298 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
299 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
300 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
301 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
302 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
303 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
304 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
305 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
306 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
307 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
308 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
309 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
310 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
311 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
312 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
313 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
314 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
315 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
316 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
317 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
318 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
319 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
320
321
322 -- arrays for default values
323 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
324 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
325 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
326
327 -- general default values
328 -- !!! to be defined !!!
329 constant sd_block_default_array : sd_block_default_array_type := (
330 X"0080", -- SD_ADDR_general_settings -- general settings
331 --X"0010", -- SD_ADDR_general_settings -- general settings
332 X"0000", -- SD_ADDR_led -- on-board status LEDs
333 X"03FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
334 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
335 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
336 X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
337 X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
338 X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
339 X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay
340 X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay
341 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
342 X"001E", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
343 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
344 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
345 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns
346 --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns
347 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
348 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
349 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
350 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
351 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
352 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
353 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
354 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
355 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
356 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
357 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
358 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
359 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
360 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
361 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
362 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
363 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
364 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
365 X"001F" -- -- Spare
366 );
367
368 -- default values for all FTUs
369 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
370 X"01FF", -- enables patch 0 board x crate y
371 X"01FF", -- enables patch 1 board x crate y
372 X"01FF", -- enables patch 2 board x crate y
373 X"01FF", -- enables patch 3 board x crate y
374 X"01F4", -- DAC_A board x crate y
375 X"01F4", -- DAC_B board x crate y
376 X"01F4", -- DAC_C board x crate y
377 X"01F4", -- DAC_D board x crate y
378 X"0010", -- DAC_H board x crate y
379 X"0001" -- Prescaling board x crate y
380 );
381
382 --default values for active FTU lists
383 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
384 X"0001",
385 X"0000",
386 X"0000",
387 X"0000"
388 );
389
390 -- Light pulser interface
391 constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
392 constant width_PLC : integer := 6; -- counter width pulse duration
393
394 -- Timing counter
395 -- constant tc_width : integer := 48; -- width (number of bits) of timing counter
396 -- constant zero : unsigned (tc_width - 1 downto 0) := (others => '0');
397
398 --======================================================================================
399 -- Constants for calibration and pedestal triggers generation
400 --======================================================================================
401 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
402 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
403 constant MS_PERIOD : real := 0.001;
404 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
405 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
406 --======================================================================================
407
408 --======================================================================================
409 -- Constants for trigger and TIM signals width (8ns+value*4ns)
410 --======================================================================================
411 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
412 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
413 --======================================================================================
414
415end ftm_constants;
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