source: firmware/FTM/ftm_definitions.vhd@ 11184

Last change on this file since 11184 was 10879, checked in by weitzel, 14 years ago
FTM: new light pulser interface, new timing constraint in .ucf file
File size: 23.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
50--
51-- modified: Patrick Vogler, May 18 2011
52-- constants for light pulser and timing counter added
53--
54-- modified: Patrick Vogler, May 26 2011
55-- constants for a simpler Lightpulser Interface "Basic Version" added
56
57----------------------------------------------------------------------------------
58
59
60library IEEE;
61use IEEE.STD_LOGIC_1164.all;
62use IEEE.STD_LOGIC_ARITH.ALL;
63use IEEE.STD_LOGIC_UNSIGNED.ALL;
64use IEEE.NUMERIC_STD.ALL;
65
66package ftm_array_types is
67
68 -- !!! some arrays are also defined in the ftm_constants package !!!
69
70 -- data arrays for a single FTU
71 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
72 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
73 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
74 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
75 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
76
77 -- data array for clock conditioner interface
78 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
79
80 -- network array types
81 type ip_type is array (0 to 3) of integer;
82 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
83
84 -- Temperature Sensor interface
85 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
86
87end ftm_array_types;
88
89
90library IEEE;
91use IEEE.STD_LOGIC_1164.all;
92use IEEE.STD_LOGIC_ARITH.ALL;
93use IEEE.STD_LOGIC_UNSIGNED.ALL;
94-- for HDL-Designer
95-- LIBRARY FACT_FTM_lib;
96-- use FACT_FTM_lib.ftm_array_types.all;
97library ftm_definitions;
98use ftm_definitions.ftm_array_types.all;
99use IEEE.NUMERIC_STD.ALL;
100use ieee.math_real.all;
101
102package ftm_constants is
103
104 -- !!! many constants depend on each other or are defined 2x with different types !!!
105
106 constant NO_OF_CRATES : integer := 4;
107 constant NO_OF_FTUS_PER_CRATE : integer := 10;
108 constant NO_OF_FTU_ENABLE_REG : integer := 4;
109 constant NO_OF_FTU_DAC_REG : integer := 5;
110
111 --internal FPGA clock frequencies
112 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
113 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
114 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
115 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
116 constant SCALER_FREQ_DIVIDER : integer := 1;
117
118 --FTM address and firmware ID
119 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
120 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version
121
122 --communication with FTUs
123 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
124 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
125 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
126 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
127 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
128 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
129 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
130
131 --broadcast to FADs
132 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
133 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
134
135 --CRC setup
136 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
137 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
138
139 --DNA identifier for simulation
140 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
141
142 -- Clock conditioner (LMK03000, National semiconductor) interface
143 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
144 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
145 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
146 constant LMK03000_REGISTER_WIDTH : integer := 32;
147 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
148 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
149 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
150 constant cc_R4_const : std_logic_vector := X"00000104";
151 constant cc_R5_const : std_logic_vector := X"00000105";
152 constant cc_R6_const : std_logic_vector := X"00000106";
153 constant cc_R7_const : std_logic_vector := X"00000107";
154
155 -- network settings Dortmund
156 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
157 -- constant NETMASK : ip_type := (255, 255, 255, 0);
158 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
159 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
160 -- constant FIRST_PORT : integer := 5000;
161
162 -- network settings Zuerich
163 constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
164 constant NETMASK : ip_type := (255, 255, 248, 0);
165 constant IP_ADDRESS : ip_type := (192, 33, 99, 246);
166 constant GATEWAY : ip_type := (192, 33, 96, 1);
167 constant FIRST_PORT : integer := 5000;
168
169 -- W5300 settings
170 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
171 -- W5300 Registers
172 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
173 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
174 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
175 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
176 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
177 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
178 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
179 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
180 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
181 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
182 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
183 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
184 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
185 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
186 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
187 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
188 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
189 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
190 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
191 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
192 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
193 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
194 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
195 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
196 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
197 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
198 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
199 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
200 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
201 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
202 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
203 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
204 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
205 -- End W5300 registers
206 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
207 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
208 constant W5300_LAST_SOCKET : integer := 0;
209
210 -- Commands
211 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
212 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
213 constant CMD_READ : std_logic_vector := X"0001";
214 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
215 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
216 -- only for debugging: data_block (0) = ADDR
217 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
218 constant CMD_WRITE : std_logic_vector := X"0002";
219 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
220 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
221 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
222 -- ping all FTUs
223 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
224 -- turn automatic sending of dd-block and ftu-error-list on or off
225 constant CMD_AUTOSEND : std_logic_vector := X"0040";
226 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
227 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
228
229 -- start run / take X events
230 constant CMD_START : std_logic_vector := X"0004";
231 constant PAR_START_RUN : std_logic_vector := X"0001";
232 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
233
234 -- stop run
235 constant CMD_STOP : std_logic_vector := X"0008";
236
237 -- crate reset
238 constant CMD_CRESET : std_logic_vector := X"0020";
239 constant RESET_TIME : integer := 50; -- hold reset line for 1us (@ 50MHz clk)
240
241 -- start and end of package
242 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
243 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
244
245 -- package types
246 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
247 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
248 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
249 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
250 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
251
252 -- state types
253 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
254 constant FTM_STATE_CFG : std_logic_vector := X"0002";
255 constant FTM_STATE_RUN : std_logic_vector := X"0003";
256 constant FTM_STATE_CALIB : std_logic_vector := X"0004";
257
258 -- header length of data packages
259 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
260
261 -- FTU error message
262 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
263
264 -- FTU-list parameters
265 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
266 constant NO_OF_FTU_LIST_REG : integer := 6;
267 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
268 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
269
270 constant NO_OF_DD_RAM_REG : integer := 12;
271
272 -- Static data block
273 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
274 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
275 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
276 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
277 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
278 constant SD_FTU_NUM : integer := 40; -- number of FTUs
279 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
280 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
281 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
282 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002";
283
284 -- dynamic data block
285 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
286 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
287 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
288
289 -- addresses in static data block
290 constant SD_ADDR_general_settings : std_logic_vector := X"000";
291 constant SD_ADDR_led : std_logic_vector := X"001";
292 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
293 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
294 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
295 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
296 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
297 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
298 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
299 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
300 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
301 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
302 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
303 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
304 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
305 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
306 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
307 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
308 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
309 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
310 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
311 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
312 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
313 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
314 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
315 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
316 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
317 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
318 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
319 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
320 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
321 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
322 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
323 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
324 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
325 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
326 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
327
328
329 -- arrays for default values
330 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
331 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
332 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
333
334 -- general default values
335 -- !!! to be defined !!!
336 constant sd_block_default_array : sd_block_default_array_type := (
337 X"0080", -- SD_ADDR_general_settings -- general settings
338 --X"0010", -- SD_ADDR_general_settings -- general settings
339 X"0000", -- SD_ADDR_led -- on-board status LEDs
340 X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
341 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
342 X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
343 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
344 X"8020", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
345 X"4001", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
346 X"0000", -- SD_ADDR_lp1_delay -- light pulser 1 delay
347 X"0000", -- SD_ADDR_lp2_delay -- light pulser 2 delay
348 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
349 X"001E", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
350 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
351 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
352 X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns
353 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
354 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
355 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
356 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
357 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
358 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
359 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
360 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
361 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
362 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
363 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
364 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
365 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
366 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
367 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
368 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
369 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
370 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
371 X"001F" -- -- Spare
372 );
373
374 -- default values for all FTUs
375 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
376 X"01FF", -- enables patch 0 board x crate y
377 X"01FF", -- enables patch 1 board x crate y
378 X"01FF", -- enables patch 2 board x crate y
379 X"01FF", -- enables patch 3 board x crate y
380 X"01F4", -- DAC_A board x crate y
381 X"01F4", -- DAC_B board x crate y
382 X"01F4", -- DAC_C board x crate y
383 X"01F4", -- DAC_D board x crate y
384 X"0010", -- DAC_H board x crate y
385 X"0001" -- Prescaling board x crate y
386 );
387
388 --default values for active FTU lists
389 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
390 X"0001",
391 X"0000",
392 X"0000",
393 X"0000"
394 );
395
396 --======================================================================================
397 -- Constants for Light pulser interface width (8ns+value*4ns)
398 --======================================================================================
399 -- constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
400 -- constant width_PLC : integer := 6; -- counter width pulse duration
401 -- constant FLD_PULSE_LENGTH : integer := 12;
402 -- constant FLD_MIN_FREQ_DIV : integer := 25;
403 -- constant FLD_FD_MULT : integer := 50;
404 -- constant FLD_FD_MAX_RANGE : integer := 64;
405
406 -- --------------------------------------------------------------------------------------
407 -- Lightpulser Basic Version
408 -- --------------------------------------------------------------------------------------
409 constant FLD_PULSE_LENGTH_BASIC : integer := 3; -- 60ns pulse @ 50MHz
410 constant FLD_MIN_FREQ_DIV_BASIC : integer := 25;
411 constant FLD_FD_MULT_BASIC : integer := 10;
412 constant FLD_FD_MAX_RANGE_BASIC : integer := 64;
413
414 -- Timing counter
415 constant TC_WIDTH : integer := 48;
416 constant PRECOUNT_WIDTH : integer := 8;
417 constant PRECOUNT_DIVIDER : integer := 50;
418
419 --======================================================================================
420 -- Constants for calibration and pedestal triggers generation
421 --======================================================================================
422 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
423 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
424 constant MS_PERIOD : real := 0.001;
425 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
426 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
427 --======================================================================================
428
429 --======================================================================================
430 -- Constants for trigger and TIM signals width (8ns+value*4ns)
431 --======================================================================================
432 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
433 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
434 --======================================================================================
435
436end ftm_constants;
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