source: firmware/FTM/ftm_definitions.vhd@ 11612

Last change on this file since 11612 was 11541, checked in by weitzel, 13 years ago
FTM IP changed
File size: 24.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: February 2011
6-- Design Name:
7-- Module Name: ftm_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: library file for FTM design
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19-- modified: Patrick Vogler, February 17 2011
20-- merged with library file from Dortmund, Q. Weitzel, February 24, 2011
21--
22-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...),
23-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined
24--
25-- modified: Quirin Weitzel, March 14 2011
26-- second merger with library file from dortmund (changes below)
27-- kw 01.03.: added array sd_block_default_ftu_active_list (type and defaults)
28-- kw 02.03.: added DD_BLOCK_SIZE_GENERAL (on-time counter + temperatures), changed DD_BLOCK_SIZE to 0x010 for testing
29-- kw 03.03.: added FTM_HEADER_LENGTH
30--
31-- modified: Quirin Weitzel, March 14 2011
32-- third merger with library file from dortmund (changes below)
33-- kw 22.03.: added FTU_ERROR_LENGTH
34-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA
35--
36---kw 11.04.: added SD_ADDR_ftu_prescaling_0
37--
38-- modified: Quirin Weitzel, April 20 2011
39-- next merger with library file from dortmund (changes below)
40-- kw 14.04.: added sensor_array_type (temperature sensors)
41-- changed CMD_AUTOSEND to X"0040"
42-- added "start run / take X events", "stop run", "crate reset"
43-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004
44-- added FTM_PACKAGE_START and FTM_PACKAGE_END
45-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter)
46-- changed FTM_HEADER_LENGTH to 0x0E
47-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE
48--
49-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive)
50--
51-- modified: Patrick Vogler, May 18 2011
52-- constants for light pulser and timing counter added
53--
54-- modified: Patrick Vogler, May 26 2011
55-- constants for a simpler Lightpulser Interface "Basic Version" added
56--
57-- qw 16.06.: network settings for La Palma added
58--
59-- qw 29.06.: changeover to firmware v2 -> FTU reconfiguration possible during run
60--
61-- kw 10.06.: added CMD_CONFIG_FTU
62--
63-- pv 21.07.: new lightpulser firmware to reduce LED current and light output
64-- changeover to firmware v3
65--
66----------------------------------------------------------------------------------
67
68
69library IEEE;
70use IEEE.STD_LOGIC_1164.all;
71use IEEE.STD_LOGIC_ARITH.ALL;
72use IEEE.STD_LOGIC_UNSIGNED.ALL;
73use IEEE.NUMERIC_STD.ALL;
74
75package ftm_array_types is
76
77 -- !!! some arrays are also defined in the ftm_constants package !!!
78
79 -- data arrays for a single FTU
80 type FTU_enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
81 type FTU_dac_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
82 type FTU_rate_array_type is array (0 to 4) of std_logic_vector(31 downto 0);
83 type active_FTU_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
84 type FTU_answer_array_type is array (0 to 3) of integer range 0 to 10;
85
86 -- data array for clock conditioner interface
87 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0);
88
89 -- network array types
90 type ip_type is array (0 to 3) of integer;
91 type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
92
93 -- Temperature Sensor interface
94 type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
95
96end ftm_array_types;
97
98
99library IEEE;
100use IEEE.STD_LOGIC_1164.all;
101use IEEE.STD_LOGIC_ARITH.ALL;
102use IEEE.STD_LOGIC_UNSIGNED.ALL;
103-- for HDL-Designer
104-- LIBRARY FACT_FTM_lib;
105-- use FACT_FTM_lib.ftm_array_types.all;
106library ftm_definitions;
107use ftm_definitions.ftm_array_types.all;
108use IEEE.NUMERIC_STD.ALL;
109use ieee.math_real.all;
110
111package ftm_constants is
112
113 -- !!! many constants depend on each other or are defined 2x with different types !!!
114
115 constant NO_OF_CRATES : integer := 4;
116 constant NO_OF_FTUS_PER_CRATE : integer := 10;
117 constant NO_OF_FTU_ENABLE_REG : integer := 4;
118 constant NO_OF_FTU_DAC_REG : integer := 5;
119
120 --internal FPGA clock frequencies
121 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz
122 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz
123 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1
124 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1
125 constant SCALER_FREQ_DIVIDER : integer := 1;
126
127 --FTM address and firmware ID
128 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
129 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000011"; -- firmware version
130
131 --communication with FTUs
132 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
133 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods)
134 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation
135 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation
136 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!!
137 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol
138 constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@"
139
140 --broadcast to FADs
141 constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case
142 constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID
143
144 --CRC setup
145 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT
146 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
147
148 --DNA identifier for simulation
149 constant DNA_FOR_SIM : bit_vector := X"01710000F0000501";
150
151 -- Clock conditioner (LMK03000, National semiconductor) interface
152 constant MICROWIRE_CLK_FREQUENCY : integer := 2000000; -- 2 MHz
153 -- value to be written to R0 of the LMK03000 to perform a reset, see LMK03000 datasheet
154 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000";
155 constant LMK03000_REGISTER_WIDTH : integer := 32;
156 constant LMK03000_REGISTER_COUNT : integer := 15; -- number of registers to be programmed in the LMK03000 including reset
157 constant cc_R2_const : std_logic_vector := X"00000102"; -- unused
158 constant cc_R3_const : std_logic_vector := X"00000103"; -- channels
159 constant cc_R4_const : std_logic_vector := X"00000104";
160 constant cc_R5_const : std_logic_vector := X"00000105";
161 constant cc_R6_const : std_logic_vector := X"00000106";
162 constant cc_R7_const : std_logic_vector := X"00000107";
163
164 -- network settings Dortmund
165 -- constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"95A0");
166 -- constant NETMASK : ip_type := (255, 255, 255, 0);
167 -- constant IP_ADDRESS : ip_type := (129, 217, 160, 118);
168 -- constant GATEWAY : ip_type := (129, 217, 160, 1);
169 -- constant FIRST_PORT : integer := 5000;
170
171 -- network settings Zuerich, for backup/test FTM
172 -- constant MAC_ADDRESS : mac_type := (X"FAC7", X"0FAD", X"1101");
173 -- constant NETMASK : ip_type := (255, 255, 248, 0);
174 -- constant IP_ADDRESS : ip_type := (192, 33, 99, 246); --registered as ftmboard1.ethz.ch
175 -- constant GATEWAY : ip_type := (192, 33, 96, 1);
176 -- constant FIRST_PORT : integer := 5000;
177
178 -- network settings La Palma (internal subnet), for FTM in camera
179 constant MAC_ADDRESS : mac_type := (X"FAC7", X"1FAD", X"1102");
180 constant NETMASK : ip_type := (255, 255, 255, 0);
181 constant IP_ADDRESS : ip_type := (10, 0, 100, 140);
182 constant GATEWAY : ip_type := (10, 0, 100, 1);
183 constant FIRST_PORT : integer := 5000;
184
185 -- W5300 settings
186 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
187 -- W5300 Registers
188 constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
189 constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
190 constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
191 constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
192 constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
193 constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
194 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
195 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
196 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
197 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
198 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
199 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
200 constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
201 constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
202 constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
203 constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
204 constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
205 constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
206 constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
207 constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
208 constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
209 constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
210 constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
211 constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
212 constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
213 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
214 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
215 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";
216 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
217 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
218 constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
219 constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
220 constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
221 -- End W5300 registers
222 constant W5300_TX_FIFO_SIZE_8B : integer := 65536; -- Socket TX FIFO-Size in Bytes
223 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
224 constant W5300_LAST_SOCKET : integer := 0;
225
226 -- Commands
227 constant CMD_START_DELIMITER : std_logic_vector := X"0040"; -- "@"
228 constant CMD_TLED : std_logic_vector := X"C000"; -- only a test
229 constant CMD_READ : std_logic_vector := X"0001";
230 constant PAR_READ_SD : std_logic_vector := X"0001"; -- read static data block
231 constant PAR_READ_DD : std_logic_vector := X"0002"; -- read dynamic data block
232 -- only for debugging: data_block (0) = ADDR
233 constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block
234 constant CMD_WRITE : std_logic_vector := X"0002";
235 constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block
236 -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA
237 constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram
238 -- ping all FTUs
239 constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs
240 -- turn automatic sending of dd-block and ftu-error-list on or off
241 constant CMD_AUTOSEND : std_logic_vector := X"0040";
242 constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending
243 constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending
244
245 -- start run / take X events
246 constant CMD_START : std_logic_vector := X"0004";
247 constant PAR_START_RUN : std_logic_vector := X"0001";
248 constant PAR_START_X_EVNTS : std_logic_vector := X"0002";
249
250 -- stop run
251 constant CMD_STOP : std_logic_vector := X"0008";
252
253 -- crate reset
254 constant CMD_CRESET : std_logic_vector := X"0020";
255 constant RESET_TIME : integer := 50; -- hold reset line for 1us (@ 50MHz clk)
256
257 -- configure one ftu
258 constant CMD_CONFIG_FTU : std_logic_vector := X"0080";
259
260 -- start and end of package
261 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
262 constant FTM_PACKAGE_END : std_logic_vector := X"04FE";
263
264 -- package types
265 constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001";
266 constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002";
267 constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003";
268 constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004";
269 constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005";
270
271 -- state types
272 constant FTM_STATE_IDLE : std_logic_vector := X"0001";
273 constant FTM_STATE_CFG : std_logic_vector := X"0002";
274 constant FTM_STATE_RUN : std_logic_vector := X"0003";
275 --constant FTM_STATE_CALIB : std_logic_vector := X"0004";
276
277 -- header length of data packages
278 constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E";
279
280 -- FTU error message
281 constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29
282
283 -- FTU-list parameters
284 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249
285 constant NO_OF_FTU_LIST_REG : integer := 6;
286 constant FTU_LIST_RAM_OFFSET : integer := 16#009#;
287 constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12;
288
289 constant NO_OF_DD_RAM_REG : integer := 12;
290
291 -- Static data block
292 constant SD_BLOCK_SIZE_GENERAL : integer := 32; -- X"20" -- static data block size without FTU data
293 constant SD_FTU_BASE_ADDR : std_logic_vector := X"020"; -- beginning of FTU data
294 constant STATIC_RAM_CFG_FTU_OFFSET : integer := 16#020#;
295 constant STATIC_RAM_ADDR_WIDTH : integer := 12;
296 constant SD_FTU_DATA_SIZE : integer := 10; -- X"00A" -- size of one FTU data block
297 constant SD_FTU_NUM : integer := 40; -- number of FTUs
298 constant SD_FTU_ACTIVE_BASE_ADDR : std_logic_vector := X"1B0"; -- beginning of active FTU lists
299 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3)
300 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block
301 constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002";
302
303 -- dynamic data block
304 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block
305 constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data
306 constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12;
307
308 -- addresses in static data block
309 constant SD_ADDR_general_settings : std_logic_vector := X"000";
310 constant SD_ADDR_led : std_logic_vector := X"001";
311 constant SD_ADDR_lp_pt_freq : std_logic_vector := X"002";
312 constant SD_ADDR_lp_pt_ratio : std_logic_vector := X"003";
313 constant SD_ADDR_lp1_amplitude : std_logic_vector := X"004";
314 constant SD_ADDR_lp2_amplitude : std_logic_vector := X"005";
315 constant SD_ADDR_lp1_delay : std_logic_vector := X"006";
316 constant SD_ADDR_lp2_delay : std_logic_vector := X"007";
317 constant SD_ADDR_coin_n_p : std_logic_vector := X"008";
318 constant SD_ADDR_coin_n_c : std_logic_vector := X"009";
319 constant SD_ADDR_trigger_delay : std_logic_vector := X"00A";
320 constant SD_ADDR_timemarker_delay : std_logic_vector := X"00B";
321 constant SD_ADDR_dead_time : std_logic_vector := X"00C";
322 constant SD_ADDR_cc_R0_HI : std_logic_vector := X"00D";
323 constant SD_ADDR_cc_R0_LO : std_logic_vector := X"00E";
324 constant SD_ADDR_cc_R1_HI : std_logic_vector := X"00F";
325 constant SD_ADDR_cc_R1_LO : std_logic_vector := X"010";
326 constant SD_ADDR_cc_R8_HI : std_logic_vector := X"011";
327 constant SD_ADDR_cc_R8_LO : std_logic_vector := X"012";
328 constant SD_ADDR_cc_R9_HI : std_logic_vector := X"013";
329 constant SD_ADDR_cc_R9_LO : std_logic_vector := X"014";
330 constant SD_ADDR_cc_R11_HI : std_logic_vector := X"015";
331 constant SD_ADDR_cc_R11_LO : std_logic_vector := X"016";
332 constant SD_ADDR_cc_R13_HI : std_logic_vector := X"017";
333 constant SD_ADDR_cc_R13_LO : std_logic_vector := X"018";
334 constant SD_ADDR_cc_R14_HI : std_logic_vector := X"019";
335 constant SD_ADDR_cc_R14_LO : std_logic_vector := X"01A";
336 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B";
337 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C";
338 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D";
339 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E";
340 constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029";
341 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0";
342 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1";
343 constant SD_ADDR_ftu_active_cr2 : std_logic_vector := X"1B2";
344 constant SD_ADDR_ftu_active_cr3 : std_logic_vector := X"1B3";
345 constant STATIC_RAM_ACT_FTU_OFFSET : integer := 16#1B0#;
346
347
348 -- arrays for default values
349 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0);
350 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0);
351 type sd_block_default_ftu_active_list_type is array (0 to (SD_FTU_ACTIVE_NUM - 1)) of std_logic_vector (15 downto 0);
352
353 -- general default values
354 -- !!! to be defined !!!
355 constant sd_block_default_array : sd_block_default_array_type := (
356 X"0080", -- SD_ADDR_general_settings -- general settings
357 --X"0010", -- SD_ADDR_general_settings -- general settings
358 X"0000", -- SD_ADDR_led -- on-board status LEDs
359 X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
360 --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency
361 X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
362 --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers
363 X"8020", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude
364 X"4001", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude
365 X"0000", -- SD_ADDR_lp1_delay -- light pulser 1 delay
366 X"0000", -- SD_ADDR_lp2_delay -- light pulser 2 delay
367 X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics)
368 X"0014", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration)
369 X"0000", -- SD_ADDR_trigger_delay -- trigger delay
370 X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay
371 X"00F8", -- SD_ADDR_dead_time -- dead time, 8ns + 4x248ns = 1000ns
372 X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16
373 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0
374 X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16
375 X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0
376 X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16
377 X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0
378 X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16
379 X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0
380 X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16
381 X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0
382 X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16
383 X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0
384 X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16
385 X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0
386 X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16
387 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0
388 X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns
389 X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns
390 X"001F" -- -- Spare
391 );
392
393 -- default values for all FTUs
394 constant sd_block_ftu_default_array : sd_block_ftu_default_array_type := (
395 X"01FF", -- enables patch 0 board x crate y
396 X"01FF", -- enables patch 1 board x crate y
397 X"01FF", -- enables patch 2 board x crate y
398 X"01FF", -- enables patch 3 board x crate y
399 X"01F4", -- DAC_A board x crate y
400 X"01F4", -- DAC_B board x crate y
401 X"01F4", -- DAC_C board x crate y
402 X"01F4", -- DAC_D board x crate y
403 X"0010", -- DAC_H board x crate y
404 X"0001" -- Prescaling board x crate y
405 );
406
407 --default values for active FTU lists
408 constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := (
409 X"0000",
410 X"0000",
411 X"0000",
412 X"0000"
413 );
414
415 --======================================================================================
416 -- Constants for Light pulser interface width (8ns+value*4ns)
417 --======================================================================================
418 -- constant low_PLC : integer := 16; -- minimal pulse duration in units of 4 ns
419 -- constant width_PLC : integer := 6; -- counter width pulse duration
420 -- constant FLD_PULSE_LENGTH : integer := 12;
421 -- constant FLD_MIN_FREQ_DIV : integer := 25;
422 -- constant FLD_FD_MULT : integer := 50;
423 -- constant FLD_FD_MAX_RANGE : integer := 64;
424
425 -- --------------------------------------------------------------------------------------
426 -- Lightpulser Basic Version
427 -- --------------------------------------------------------------------------------------
428 constant FLD_PULSE_LENGTH_Pulse : integer := 2; -- 40ns pulse @ 50MHz, instead of 3: 60ns pulse @ 50MHz
429 constant FLD_PULSE_LENGTH_FM : integer := 3; -- 60ns pulse @ 50MHz
430 constant FLD_MIN_FREQ_DIV_BASIC : integer := 8; -- before 25
431 constant FLD_FD_MULT_BASIC : integer := 8; -- before 10
432 constant FLD_FD_MAX_RANGE_BASIC : integer := 128;-- before 64
433
434 -- Timing counter
435 constant TC_WIDTH : integer := 48;
436 constant PRECOUNT_WIDTH : integer := 8;
437 constant PRECOUNT_DIVIDER : integer := 50;
438
439 --======================================================================================
440 -- Constants for calibration and pedestal triggers generation
441 --======================================================================================
442 constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0;
443 constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ;
444 constant MS_PERIOD : real := 0.001;
445 constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD))));
446 constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD);
447 --======================================================================================
448
449 --======================================================================================
450 -- Constants for trigger and TIM signals width (8ns+value*4ns)
451 --======================================================================================
452 constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10;
453 constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0;
454 --======================================================================================
455
456end ftm_constants;
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