source: firmware/FTM/ftu_control/FTM_ftu_control.vhd@ 10694

Last change on this file since 10694 was 10418, checked in by weitzel, 14 years ago
New FTM firmare: dna, fad_broadcast, FTU error messages, rates readout
File size: 52.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 17:54:04 02/02/2011
6-- Design Name:
7-- Module Name: FTM_ftu_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Communication of FTM with the 40 FTU boards of the FACT camera
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_ftu_control is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus enables for FTU crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- FTU crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- FTU crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- FTU crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- FTU crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- commands from FTM main control
59 new_config : in std_logic;
60 ping_all : in std_logic;
61 read_rates : in std_logic;
62
63 -- answers to FTM main control
64 read_rates_started : out std_logic := '0';
65 read_rates_done : out std_logic := '0';
66 new_config_started : out std_logic := '0';
67 new_config_done : out std_logic := '0';
68 ping_all_started : out std_logic := '0';
69 ping_all_done : out std_logic := '0';
70
71 -- active FTU lists
72 ftu_active_cr0 : in std_logic_vector (15 downto 0);
73 ftu_active_cr1 : in std_logic_vector (15 downto 0);
74 ftu_active_cr2 : in std_logic_vector (15 downto 0);
75 ftu_active_cr3 : in std_logic_vector (15 downto 0);
76
77 --error message interface to ethernet control
78 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
79 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
80 ftu_error_send : out std_logic := '0';
81 ftu_error_send_ack : in std_logic;
82 ftu_error_send_ready : in std_logic;
83
84 -- communication with static (config) RAM
85 -- this RAM is only read by FTU_control
86 static_RAM_busy : in std_logic;
87 static_RAM_started : in std_logic;
88 static_RAM_ready : in std_logic;
89 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
90 read_static_RAM : out std_logic := '0';
91 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
92
93 -- communication with dynamic RAM (e.g. rates)
94 -- this RAM is only written by FTU_control
95 dynamic_RAM_busy : in std_logic;
96 dynamic_RAM_started : in std_logic;
97 dynamic_RAM_ready : in std_logic;
98 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
99 write_dynamic_RAM : out std_logic := '0';
100 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
101
102 -- communication with FTU-list RAM
103 -- this RAM is only written by FTU_control
104 FTUlist_RAM_busy : in std_logic;
105 FTUlist_RAM_started : in std_logic;
106 FTUlist_RAM_ready : in std_logic;
107 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
108 write_FTUlist_RAM : out std_logic := '0';
109 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
110
111 );
112end FTM_ftu_control;
113
114architecture Behavioral of FTM_ftu_control is
115
116 -- list of active FTUs, read out from static RAM before starting to contact FTUs
117 signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
118 --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0'));
119
120 -- signals to count the number of responding FTUs (per crate and total) in case of a ping
121 signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
122 signal no_of_FTU_answer_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE) := 0;
123
124 -- FTU configuration data, read out from static RAM (board by board)
125 signal FTU_dac_array_RAM_sig : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
126 signal FTU_enable_array_RAM_sig : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
127 signal FTU_prescaling_RAM_sig : std_logic_vector(15 downto 0) := (others => '0');
128
129 -- signals for receiver of FTU communication
130 signal rec_reset_sig : std_logic := '0'; -- reset
131 signal rec_data_sig : std_logic_vector (7 DOWNTO 0);
132 signal rec_block_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTM_ftu_rs485_receiver
133 signal rec_valid_sig : std_logic; -- initialized in FTM_ftu_rs485_receiver
134
135 -- select signal to multiplex the different crates
136 signal sel_crate_sig : STD_LOGIC_VECTOR (2 downto 0) := "111";
137
138 -- global signals after multiplexer
139 signal rx_en_sig : std_logic := '0';
140 signal tx_en_sig : std_logic := '0';
141 signal rx_valid_sig : std_logic := '0';
142 signal tx_busy_sig : std_logic := '0';
143 signal tx_start_sig : std_logic := '0';
144 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
145 signal rx_busy_sig : std_logic := '0';
146 signal start_int_sig : std_logic := '0';
147
148 -- signals for interpreter of FTU communication
149 signal FTU_brd_add_sig : std_logic_vector (5 DOWNTO 0) := (others => '0');
150 signal FTU_command_sig : std_logic_vector (7 DOWNTO 0) := (others => '1');
151 signal FTU_answer_ok_sig : std_logic; -- initialized in interpreter
152 signal FTU_dac_array_sig : FTU_dac_array_type; -- initialized in interpreter
153 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter
154 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter
155 signal FTU_overflow_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
156 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
157 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
158 signal FTU_dna_sig : std_logic_vector(63 downto 0); -- initialized in interpreter
159
160 -- rx_enable and tx_enable lines from different FTM_ftu_rs485_interface
161 -- initialized in corresponding interface
162 signal rx_en_0_sig : STD_LOGIC;
163 signal tx_en_0_sig : STD_LOGIC;
164 signal rx_en_1_sig : STD_LOGIC;
165 signal tx_en_1_sig : STD_LOGIC;
166 signal rx_en_2_sig : STD_LOGIC;
167 signal tx_en_2_sig : STD_LOGIC;
168 signal rx_en_3_sig : STD_LOGIC;
169 signal tx_en_3_sig : STD_LOGIC;
170
171 signal tx_start_0_sig : std_logic := '0';
172 signal tx_data_0_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
173 signal tx_busy_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
174 signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
175 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0
176 signal rx_busy_0_sig : std_logic; -- initialized in FTU_rs485_interface_0
177
178 signal tx_start_1_sig : std_logic := '0';
179 signal tx_data_1_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
180 signal tx_busy_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
181 signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
182 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1
183 signal rx_busy_1_sig : std_logic; -- initialized in FTU_rs485_interface_1
184
185 signal tx_start_2_sig : std_logic := '0';
186 signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
187 signal tx_busy_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
188 signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
189 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2
190 signal rx_busy_2_sig : std_logic; -- initialized in FTU_rs485_interface_2
191
192 signal tx_start_3_sig : std_logic := '0';
193 signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
194 signal tx_busy_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
195 signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
196 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3
197 signal rx_busy_3_sig : std_logic; -- initialized in FTU_rs485_interface_3
198
199 -- signals to control and read out CRC
200 signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter
201 signal reset_crc_sig : std_logic;
202 signal enable_crc_sig : std_logic;
203 signal crc_data_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
204 signal reset_crc_from_FSM_sig : std_logic := '0';
205 signal reset_crc_from_interpreter_sig : std_logic;
206 signal enable_crc_from_FSM_sig : std_logic := '0';
207 signal enable_crc_from_interpreter_sig : std_logic;
208 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
209 signal crc_data_from_FSM_sig_cp : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
210 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
211 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
212
213 -- various loop counters
214 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;
215 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0;
216 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0;
217 signal FTU_register_cnt : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) := 0;
218 signal FTU_command_cnt : integer range 0 to 3 := 0;
219 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0;
220 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0;
221 signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0;
222 signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0;
223
224 -- counter to define timeout and number of retries
225 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
226 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
227
228 --Zwischenrechnungen
229 signal FTU_cnt_offset_sig : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0;
230 signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0;
231
232 component FTM_ftu_rs485_interface
233 port(
234 clk : IN std_logic;
235 -- RS485
236 rx_d : IN std_logic;
237 rx_en : OUT std_logic;
238 tx_d : OUT std_logic;
239 tx_en : OUT std_logic;
240 -- FPGA
241 rx_data : OUT std_logic_vector (7 DOWNTO 0);
242 rx_busy : OUT std_logic := '0';
243 rx_valid : OUT std_logic := '0';
244 tx_data : IN std_logic_vector (7 DOWNTO 0);
245 tx_busy : OUT std_logic := '0';
246 tx_start : IN std_logic
247 );
248 end component;
249
250 component FTM_ftu_rs485_receiver
251 port(
252 rec_clk : in std_logic;
253 rec_reset : in std_logic;
254 --rx_busy : in std_logic;
255 rec_din : in std_logic_vector(7 downto 0);
256 rec_den : in std_logic;
257 rec_dout : out std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
258 rec_valid : out std_logic := '0'
259 );
260 end component;
261
262 component FTM_ftu_rs485_interpreter
263 port(
264 clk : IN std_logic;
265 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0);
266 block_valid : IN std_logic;
267 crc : IN std_logic_vector(7 downto 0);
268 FTU_brd_add : IN std_logic_vector(5 downto 0);
269 FTU_command : IN std_logic_vector(7 downto 0);
270 reset_crc : OUT std_logic := '0';
271 enable_crc : OUT std_logic := '0';
272 FTU_answer_ok : OUT std_logic := '0';
273 FTU_dac_array : OUT FTU_dac_array_type;
274 FTU_enable_array : OUT FTU_enable_array_type;
275 FTU_rate_array : OUT FTU_rate_array_type;
276 FTU_overflow : OUT std_logic_vector(7 downto 0);
277 FTU_prescaling : OUT std_logic_vector(7 downto 0);
278 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
279 FTU_dna : OUT std_logic_vector(63 downto 0)
280 );
281 end component;
282
283 component ucrc_par
284 generic(
285 POLYNOMIAL : std_logic_vector;
286 INIT_VALUE : std_logic_vector;
287 DATA_WIDTH : integer range 2 to 256;
288 SYNC_RESET : integer range 0 to 1
289 );
290 port(
291 clk_i : in std_logic;
292 rst_i : in std_logic;
293 clken_i : in std_logic;
294 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
295 match_o : out std_logic;
296 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
297 );
298 end component;
299
300 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
301 PING, PING_END, FTU_LIST,
302 SEND_ERROR_1, SEND_ERROR_2,
303 RATES, RATES_1, RATES_2, RATES_3,
304 DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3,
305 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
306 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
307 PING_1, PING_2, PING_3, PING_END_1, PING_END_2, PING_END_3,
308 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3);
309 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
310 signal after_error_State : FTM_ftu_rs485_control_StateType;
311
312begin
313
314 Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0
315 port map(
316 clk => clk_50MHz,
317 -- RS485
318 rx_d => rx_d_0,
319 rx_en => rx_en_0_sig,
320 tx_d => tx_d_0,
321 tx_en => tx_en_0_sig,
322 -- FPGA
323 rx_data => rx_data_0_sig,
324 rx_busy => rx_busy_0_sig,
325 rx_valid => rx_valid_0_sig,
326 tx_data => tx_data_0_sig,
327 tx_busy => tx_busy_0_sig,
328 tx_start => tx_start_0_sig
329 );
330
331 Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1
332 port map(
333 clk => clk_50MHz,
334 -- RS485
335 rx_d => rx_d_1,
336 rx_en => rx_en_1_sig,
337 tx_d => tx_d_1,
338 tx_en => tx_en_1_sig,
339 -- FPGA
340 rx_data => rx_data_1_sig,
341 rx_busy => rx_busy_1_sig,
342 rx_valid => rx_valid_1_sig,
343 tx_data => tx_data_1_sig,
344 tx_busy => tx_busy_1_sig,
345 tx_start => tx_start_1_sig
346 );
347
348 Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2
349 port map(
350 clk => clk_50MHz,
351 -- RS485
352 rx_d => rx_d_2,
353 rx_en => rx_en_2_sig,
354 tx_d => tx_d_2,
355 tx_en => tx_en_2_sig,
356 -- FPGA
357 rx_data => rx_data_2_sig,
358 rx_busy => rx_busy_2_sig,
359 rx_valid => rx_valid_2_sig,
360 tx_data => tx_data_2_sig,
361 tx_busy => tx_busy_2_sig,
362 tx_start => tx_start_2_sig
363 );
364
365 Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3
366 port map(
367 clk => clk_50MHz,
368 -- RS485
369 rx_d => rx_d_3,
370 rx_en => rx_en_3_sig,
371 tx_d => tx_d_3,
372 tx_en => tx_en_3_sig,
373 -- FPGA
374 rx_data => rx_data_3_sig,
375 rx_busy => rx_busy_3_sig,
376 rx_valid => rx_valid_3_sig,
377 tx_data => tx_data_3_sig,
378 tx_busy => tx_busy_3_sig,
379 tx_start => tx_start_3_sig
380 );
381
382 Inst_FTM_ftu_rs485_receiver : FTM_ftu_rs485_receiver
383 port map(
384 rec_clk => clk_50MHz,
385 rec_reset => rec_reset_sig,
386 --rx_busy =>,
387 rec_din => rec_data_sig,
388 rec_den => rx_valid_sig,
389 rec_dout => rec_block_sig,
390 rec_valid => rec_valid_sig
391 );
392
393 Inst_FTM_ftu_rs485_interpreter : FTM_ftu_rs485_interpreter
394 port map(
395 clk => clk_50MHz,
396 data_block => rec_block_sig,
397 block_valid => start_int_sig,
398 crc => crc_sig,
399 FTU_brd_add => FTU_brd_add_sig,
400 FTU_command => FTU_command_sig,
401 reset_crc => reset_crc_from_interpreter_sig,
402 enable_crc => enable_crc_from_interpreter_sig,
403 FTU_answer_ok => FTU_answer_ok_sig,
404 FTU_dac_array => FTU_dac_array_sig,
405 FTU_enable_array => FTU_enable_array_sig,
406 FTU_rate_array => FTU_rate_array_sig,
407 FTU_overflow => FTU_overflow_sig,
408 FTU_prescaling => FTU_prescaling_sig,
409 FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
410 FTU_dna => FTU_dna_sig
411 );
412
413 Inst_ucrc_par : ucrc_par
414 generic map(
415 POLYNOMIAL => CRC_POLYNOMIAL,
416 INIT_VALUE => CRC_INIT_VALUE,
417 DATA_WIDTH => (FTU_RS485_BLOCK_WIDTH - 8),
418 SYNC_RESET => 1
419 )
420 port map(
421 clk_i => clk_50MHz,
422 rst_i => reset_crc_sig,
423 clken_i => enable_crc_sig,
424 data_i => crc_data_sig,
425 match_o => open,
426 crc_o => crc_sig_inv
427 );
428
429 -- Main finite state machine to control all 40 FTUs
430 FTM_ftu_rs485_control_FSM: process (clk_50MHz)
431 begin
432 if Rising_edge(clk_50MHz) then
433 case FTM_ftu_rs485_control_State is
434
435 when INIT => -- reset CRC register
436 reset_crc_from_FSM_sig <= '1';
437 FTM_ftu_rs485_control_State <= IDLE;
438
439 when IDLE => -- wait for command from outside
440 sel_crate_sig <= "111";
441 sel_crc_input_source_sig <= '0';
442 reset_crc_from_FSM_sig <= '0';
443 enable_crc_from_FSM_sig <= '0';
444 new_config_done <= '0';
445 ping_all_done <= '0';
446 read_rates_done <= '0';
447 if (new_config = '1') then
448 new_config_started <= '1';
449 ping_all_started <= '0';
450 read_rates_started <= '0';
451 FTM_ftu_rs485_control_State <= ACTIVE_LIST;
452 elsif (new_config = '0' and ping_all = '1') then
453 new_config_started <= '0';
454 ping_all_started <= '1';
455 read_rates_started <= '0';
456 rec_reset_sig <= '1';
457 FTM_ftu_rs485_control_State <= PING;
458 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then
459 new_config_started <= '0';
460 ping_all_started <= '0';
461 read_rates_started <= '1';
462 FTM_ftu_rs485_control_State <= RATES;
463 else
464 new_config_started <= '0';
465 ping_all_started <= '0';
466 read_rates_started <= '0';
467 FTM_ftu_rs485_control_State <= IDLE;
468 end if;
469
470 when ACTIVE_LIST => -- copy active FTU list from inputs to array
471 active_FTU_array_sig(0) <= ftu_active_cr0;
472 active_FTU_array_sig(1) <= ftu_active_cr1;
473 active_FTU_array_sig(2) <= ftu_active_cr2;
474 active_FTU_array_sig(3) <= ftu_active_cr3;
475 FTM_ftu_rs485_control_State <= READ_CONFIG;
476
477-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list
478-- if (active_FTU_list_cnt < NO_OF_CRATES) then
479-- active_FTU_list_cnt <= active_FTU_list_cnt + 1;
480-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1;
481-- else
482-- active_FTU_list_cnt <= 0;
483-- FTM_ftu_rs485_control_State <= READ_CONFIG;
484-- end if;
485
486-- when ACTIVE_LIST_1 =>
487-- if (static_RAM_busy = '0') then
488-- read_static_RAM <= '1';
489-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH);
490-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2;
491-- end if;
492
493-- when ACTIVE_LIST_2 =>
494-- if (static_RAM_started = '1') then
495-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;
496-- end if;
497
498-- when ACTIVE_LIST_3 =>
499-- if (static_RAM_ready = '1') then
500-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;
501-- read_static_RAM <= '0';
502-- FTM_ftu_rs485_control_State <= ACTIVE_LIST;
503-- end if;
504
505 when READ_CONFIG => -- read configuration of FTUs (one by one)
506 if (crate_cnt < NO_OF_CRATES) then
507 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
508 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
509 if (FTU_register_cnt < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1)) then
510 FTU_register_cnt <= FTU_register_cnt + 1;
511 FTM_ftu_rs485_control_State <= READ_CONFIG_1;
512 else
513 FTU_cnt <= FTU_cnt + 1;
514 FTU_register_cnt <= 0;
515 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
516 rec_reset_sig <= '1';
517 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
518 else
519 FTM_ftu_rs485_control_State <= READ_CONFIG;
520 end if;
521 end if;
522 else
523 crate_cnt <= crate_cnt + 1;
524 FTU_cnt <= 0;
525 FTM_ftu_rs485_control_State <= READ_CONFIG;
526 end if;
527 else
528 crate_cnt <= 0;
529 new_config_started <= '0';
530 new_config_done <= '1';
531 sel_crate_sig <= "111";
532 FTM_ftu_rs485_control_State <= IDLE;
533 end if;
534
535 when READ_CONFIG_1 =>
536 if (static_RAM_busy = '0') then
537 read_static_RAM <= '1';
538 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
539 crate_cnt * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
540 FTU_cnt * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
541 (FTU_register_cnt - 1), STATIC_RAM_ADDR_WIDTH);
542 FTM_ftu_rs485_control_State <= READ_CONFIG_2;
543 end if;
544
545 when READ_CONFIG_2 =>
546 if (static_RAM_started = '1') then
547 FTM_ftu_rs485_control_State <= READ_CONFIG_3;
548 end if;
549
550 when READ_CONFIG_3 =>
551 if (static_RAM_ready = '1') then
552 if ((FTU_register_cnt - 1) < NO_OF_FTU_ENABLE_REG) then
553 FTU_enable_array_RAM_sig(FTU_register_cnt - 1) <= data_static_RAM;
554 elsif ((FTU_register_cnt - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
555 FTU_dac_array_RAM_sig((FTU_register_cnt - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
556 elsif ((FTU_register_cnt - 1) = (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
557 FTU_prescaling_RAM_sig <= data_static_RAM;
558 end if;
559 read_static_RAM <= '0';
560 FTM_ftu_rs485_control_State <= READ_CONFIG;
561 end if;
562
563 when TRANSMIT_CONFIG => -- send configuration to FTUs (one by one)
564 rec_reset_sig <= '0';
565 if (FTU_command_cnt = 0) then -- DACs
566 FTU_command_cnt <= FTU_command_cnt + 1;
567 enable_crc_from_FSM_sig <= '1';
568 crc_data_from_FSM_sig <= "00000000"
569 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
570 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
571 & "00000000"
572 & FTU_dac_array_RAM_sig(4)(15 downto 8) & FTU_dac_array_RAM_sig(4)(7 downto 0)
573 & FTU_dac_array_RAM_sig(3)(15 downto 8) & FTU_dac_array_RAM_sig(3)(7 downto 0)
574 & FTU_dac_array_RAM_sig(2)(15 downto 8) & FTU_dac_array_RAM_sig(2)(7 downto 0)
575 & FTU_dac_array_RAM_sig(1)(15 downto 8) & FTU_dac_array_RAM_sig(1)(7 downto 0)
576 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0)
577 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
578 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
579 & FTU_RS485_START_DELIM;
580 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
581 FTU_command_sig <= "00000000";
582 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
583 elsif (FTU_command_cnt = 1) then -- enables
584 FTU_command_cnt <= FTU_command_cnt + 1;
585 enable_crc_from_FSM_sig <= '1';
586 crc_data_from_FSM_sig <= "00000000"
587 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
588 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
589 & "00000000" & "00000000" & "00000000"
590 & FTU_enable_array_RAM_sig(3)(15 downto 8) & FTU_enable_array_RAM_sig(3)(7 downto 0)
591 & FTU_enable_array_RAM_sig(2)(15 downto 8) & FTU_enable_array_RAM_sig(2)(7 downto 0)
592 & FTU_enable_array_RAM_sig(1)(15 downto 8) & FTU_enable_array_RAM_sig(1)(7 downto 0)
593 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0)
594 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
595 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
596 & FTU_RS485_START_DELIM;
597 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
598 FTU_command_sig <= "00000011";
599 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
600 elsif (FTU_command_cnt = 2) then -- prescaling
601 FTU_command_cnt <= FTU_command_cnt + 1;
602 enable_crc_from_FSM_sig <= '1';
603 crc_data_from_FSM_sig <= "00000000"
604 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
605 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
606 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
607 & "00000000" & "00000000" & "00000000" & "00000000"
608 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0)
609 & "00000110" & FIRMWARE_ID & FTM_ADDRESS
610 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
611 & FTU_RS485_START_DELIM;
612 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
613 FTU_command_sig <= "00000110";
614 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
615 else
616 FTU_command_cnt <= 0;
617 enable_crc_from_FSM_sig <= '0';
618 FTM_ftu_rs485_control_State <= READ_CONFIG;
619 end if;
620
621 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation
622 enable_crc_from_FSM_sig <= '0';
623 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
624 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
625
626 when TRANSMIT_CONFIG_2 => -- transmit byte by byte
627 if (tx_busy_sig = '0') then
628 if (frame_cnt < 27) then
629 frame_cnt <= frame_cnt + 1;
630 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
631 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
632 tx_start_sig <= '1';
633 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
634 elsif (frame_cnt = 27) then
635 frame_cnt <= frame_cnt + 1;
636 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
637 tx_data_sig <= crc_sig;
638 tx_start_sig <= '1';
639 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
640 else
641 frame_cnt <= 0;
642 reset_crc_from_FSM_sig <= '1';
643 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
644 end if;
645 else
646 tx_start_sig <= '0';
647 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
648 end if;
649
650 when TRANSMIT_CONFIG_3 => -- wait for FTU answer
651 reset_crc_from_FSM_sig <= '0';
652 if (FTU_answer_ok_sig = '1') then
653 timeout_cnt <= 0;
654 retry_cnt <= 0;
655 sel_crc_input_source_sig <= '0';
656 if (retry_cnt = 0) then -- no errors
657 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
658 else -- send error message and move to next command;
659 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
660 after_error_State <= TRANSMIT_CONFIG;
661 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
662 end if;
663 else
664 if (timeout_cnt < FTU_RS485_TIMEOUT) then
665 timeout_cnt <= timeout_cnt + 1;
666 sel_crc_input_source_sig <= '1';
667 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
668 else
669 timeout_cnt <= 0;
670 sel_crc_input_source_sig <= '0';
671 rec_reset_sig <= '1';
672 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
673 retry_cnt <= retry_cnt + 1;
674 FTU_command_cnt <= FTU_command_cnt - 1; -- try this command again
675 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
676 else
677 retry_cnt <= 0;
678 FTU_command_cnt <= FTU_command_cnt; -- send error message and move to next command
679 ftu_error_calls <= (others => '0');
680 after_error_State <= TRANSMIT_CONFIG;
681 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
682 end if;
683 end if;
684 end if;
685
686 when SEND_ERROR_1 => -- send an error message
687 ftu_error_send <= '1';
688 if (ftu_error_send_ack = '1') then
689 ftu_error_send <= '0';
690 FTM_ftu_rs485_control_State <= SEND_ERROR_2;
691 end if;
692
693 when SEND_ERROR_2 =>
694 if (ftu_error_send_ready = '1') then
695 FTM_ftu_rs485_control_State <= after_error_state;
696 end if;
697
698 when PING => -- ping all FTUs
699 rec_reset_sig <= '0';
700 if (crate_cnt < NO_OF_CRATES) then
701 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
702 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
703 FTU_cnt <= FTU_cnt + 1;
704 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
705 enable_crc_from_FSM_sig <= '1';
706 crc_data_from_FSM_sig <= "00000000"
707 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
708 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
709 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
710 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
711 & "00000101" & FIRMWARE_ID & FTM_ADDRESS
712 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
713 & FTU_RS485_START_DELIM;
714 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
715 FTU_command_sig <= "00000101";
716 FTM_ftu_rs485_control_State <= PING_1;
717 else
718 FTM_ftu_rs485_control_State <= PING;
719 end if;
720 else
721 crate_cnt <= crate_cnt + 1;
722 FTU_cnt <= 0;
723 FTM_ftu_rs485_control_State <= PING;
724 end if;
725 else
726 crate_cnt <= 0;
727 FTM_ftu_rs485_control_State <= PING_END;
728 end if;
729
730 when PING_1 => -- wait one cycle for CRC calculation
731 enable_crc_from_FSM_sig <= '0';
732 rec_reset_sig <= '1';
733 FTM_ftu_rs485_control_State <= PING_2;
734
735 when PING_2 => -- transmit byte by byte
736 rec_reset_sig <= '0';
737 if (tx_busy_sig = '0') then
738 if (frame_cnt < 27) then
739 frame_cnt <= frame_cnt + 1;
740 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
741 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
742 tx_start_sig <= '1';
743 FTM_ftu_rs485_control_State <= PING_2;
744 elsif (frame_cnt = 27) then
745 frame_cnt <= frame_cnt + 1;
746 tx_data_sig <= crc_sig;
747 tx_start_sig <= '1';
748 FTM_ftu_rs485_control_State <= PING_2;
749 else
750 frame_cnt <= 0;
751 reset_crc_from_FSM_sig <= '1';
752 FTM_ftu_rs485_control_State <= PING_3;
753 end if;
754 else
755 tx_start_sig <= '0';
756 FTM_ftu_rs485_control_State <= PING_2;
757 end if;
758
759 when PING_3 => -- wait for FTU answer
760 reset_crc_from_FSM_sig <= '0';
761 if (FTU_answer_ok_sig = '1') then
762 FTU_answer_array_sig(crate_cnt) <= FTU_answer_array_sig(crate_cnt) + 1;
763 no_of_FTU_answer_sig <= no_of_FTU_answer_sig + 1;
764 timeout_cnt <= 0;
765 sel_crc_input_source_sig <= '0';
766 FTM_ftu_rs485_control_State <= FTU_LIST;
767 else
768 if (timeout_cnt < FTU_RS485_TIMEOUT) then
769 timeout_cnt <= timeout_cnt + 1;
770 sel_crc_input_source_sig <= '1';
771 FTM_ftu_rs485_control_State <= PING_3;
772 else
773 timeout_cnt <= 0;
774 sel_crc_input_source_sig <= '0';
775 rec_reset_sig <= '1';
776 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
777 retry_cnt <= retry_cnt + 1;
778 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
779 FTM_ftu_rs485_control_State <= PING;
780 else
781 FTU_cnt <= FTU_cnt; -- move on
782 FTM_ftu_rs485_control_State <= FTU_LIST;
783 end if;
784 end if;
785 end if;
786
787 when FTU_LIST => -- fill FTU-list for actual FTU
788 rec_reset_sig <= '0';
789 if (FTU_list_reg_cnt < NO_OF_FTU_LIST_REG) then
790 FTU_list_reg_cnt <= FTU_list_reg_cnt + 1;
791 FTM_ftu_rs485_control_State <= FTU_LIST_1;
792 else
793 FTU_list_reg_cnt <= 0;
794 retry_cnt <= 0;
795 FTM_ftu_rs485_control_State <= PING;
796 end if;
797
798 when FTU_LIST_1 =>
799 if (FTUlist_RAM_busy = '0') then
800 write_FTUlist_RAM <= '1';
801 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
802 (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) +
803 ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) +
804 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
805 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
806 if ((FTU_list_reg_cnt - 1) = 0) then
807 data_FTUlist_RAM <= "000000" & conv_std_logic_vector((retry_cnt + 1),2) & "00" & FTU_brd_add_sig;
808 elsif ((FTU_list_reg_cnt - 1) = 1) then
809 data_FTUlist_RAM <= FTU_dna_sig(63 downto 48);
810 elsif ((FTU_list_reg_cnt - 1) = 2) then
811 data_FTUlist_RAM <= FTU_dna_sig(47 downto 32);
812 elsif ((FTU_list_reg_cnt - 1) = 3) then
813 data_FTUlist_RAM <= FTU_dna_sig(31 downto 16);
814 elsif ((FTU_list_reg_cnt - 1) = 4) then
815 data_FTUlist_RAM <= FTU_dna_sig(15 downto 0);
816 elsif ((FTU_list_reg_cnt - 1) = 5) then
817 data_FTUlist_RAM <= "00000000" & FTU_crc_error_cnt_sig;
818 end if;
819 else
820 data_FTUlist_RAM <= (others => '0');
821 end if;
822 FTM_ftu_rs485_control_State <= FTU_LIST_2;
823 end if;
824
825 when FTU_LIST_2 =>
826 if (FTUlist_RAM_started = '1') then
827 write_FTUlist_RAM <= '0';
828 FTM_ftu_rs485_control_State <= FTU_LIST_3;
829 end if;
830
831 when FTU_LIST_3 =>
832 if (FTUlist_RAM_ready = '1') then
833 FTM_ftu_rs485_control_State <= FTU_LIST;
834 end if;
835
836 when PING_END => -- add final ping statistics to FTU-list
837 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then
838 FTU_list_header_cnt <= FTU_list_header_cnt + 1;
839 FTM_ftu_rs485_control_State <= PING_END_1;
840 else
841 FTU_list_header_cnt <= 0;
842 ping_all_started <= '0';
843 ping_all_done <= '1';
844 sel_crate_sig <= "111";
845 FTU_answer_array_sig(0) <= 0;
846 FTU_answer_array_sig(1) <= 0;
847 FTU_answer_array_sig(2) <= 0;
848 FTU_answer_array_sig(3) <= 0;
849 no_of_FTU_answer_sig <= 0;
850 FTM_ftu_rs485_control_State <= IDLE;
851 end if;
852
853 when PING_END_1 =>
854 if (FTUlist_RAM_busy = '0') then
855 write_FTUlist_RAM <= '1';
856 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
857 if ((FTU_list_header_cnt - 1) = 0) then
858 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16);
859 elsif ((FTU_list_header_cnt - 1) < 5) then
860 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16);
861 elsif ((FTU_list_header_cnt - 1) < 9) then
862 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6);
863 end if;
864 FTM_ftu_rs485_control_State <= PING_END_2;
865 end if;
866
867 when PING_END_2 =>
868 if (FTUlist_RAM_started = '1') then
869 write_FTUlist_RAM <= '0';
870 FTM_ftu_rs485_control_State <= PING_END_3;
871 end if;
872
873 when PING_END_3 =>
874 if (FTUlist_RAM_ready = '1') then
875 FTM_ftu_rs485_control_State <= PING_END;
876 end if;
877
878 when RATES => -- read all FTU rates
879 rec_reset_sig <= '0';
880 if (crate_cnt < NO_OF_CRATES) then
881 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
882 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
883 FTU_cnt <= FTU_cnt + 1;
884 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
885 enable_crc_from_FSM_sig <= '1';
886 crc_data_from_FSM_sig <= "00000000"
887 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
888 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
889 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
890 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
891 & "00000010" & FIRMWARE_ID & FTM_ADDRESS
892 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
893 & FTU_RS485_START_DELIM;
894 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
895 FTU_command_sig <= "00000010";
896 FTM_ftu_rs485_control_State <= RATES_1;
897 else
898 FTM_ftu_rs485_control_State <= RATES;
899 end if;
900 else
901 crate_cnt <= crate_cnt + 1;
902 FTU_cnt <= 0;
903 FTM_ftu_rs485_control_State <= RATES;
904 end if;
905 else
906 crate_cnt <= 0;
907 read_rates_started <= '0';
908 read_rates_done <= '1';
909 sel_crate_sig <= "111";
910 FTM_ftu_rs485_control_State <= IDLE;
911 end if;
912
913 when RATES_1 => -- wait one cycle for CRC calculation
914 enable_crc_from_FSM_sig <= '0';
915 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
916 FTM_ftu_rs485_control_State <= RATES_2;
917
918 when RATES_2 => -- transmit byte by byte
919 if (tx_busy_sig = '0') then
920 if (frame_cnt < 27) then
921 frame_cnt <= frame_cnt + 1;
922 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
923 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
924 tx_start_sig <= '1';
925 FTM_ftu_rs485_control_State <= RATES_2;
926 elsif (frame_cnt = 27) then
927 frame_cnt <= frame_cnt + 1;
928 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
929 tx_data_sig <= crc_sig;
930 tx_start_sig <= '1';
931 FTM_ftu_rs485_control_State <= RATES_2;
932 else
933 frame_cnt <= 0;
934 reset_crc_from_FSM_sig <= '1';
935 FTM_ftu_rs485_control_State <= RATES_3;
936 end if;
937 else
938 tx_start_sig <= '0';
939 FTM_ftu_rs485_control_State <= RATES_2;
940 end if;
941
942 when RATES_3 => -- wait for FTU answer
943 reset_crc_from_FSM_sig <= '0';
944 if (FTU_answer_ok_sig = '1') then
945 timeout_cnt <= 0;
946 sel_crc_input_source_sig <= '0';
947 --FTM_ftu_rs485_control_State <= RATES;
948 if (retry_cnt = 0) then -- no errors
949 FTM_ftu_rs485_control_State <= DD_RAM;
950 else -- send error message and move to next command;
951 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
952 after_error_State <= DD_RAM;
953 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
954 end if;
955 else
956 if (timeout_cnt < FTU_RS485_TIMEOUT) then
957 timeout_cnt <= timeout_cnt + 1;
958 sel_crc_input_source_sig <= '1';
959 FTM_ftu_rs485_control_State <= RATES_3;
960 else
961 timeout_cnt <= 0;
962 sel_crc_input_source_sig <= '0';
963 rec_reset_sig <= '1';
964 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
965 retry_cnt <= retry_cnt + 1;
966 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
967 FTM_ftu_rs485_control_State <= RATES;
968 else
969 --retry_cnt <= 0;
970 FTU_cnt <= FTU_cnt; -- move on
971 ftu_error_calls <= (others => '0');
972 after_error_State <= DD_RAM;
973 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
974 end if;
975 end if;
976 end if;
977
978 when DD_RAM => -- write rates of actual FTU to DD RAM
979 rec_reset_sig <= '0';
980 if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then
981 DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1;
982 FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG);
983 crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG);
984 FTM_ftu_rs485_control_State <= DD_RAM_1;
985 else
986 DD_RAM_reg_cnt <= 0;
987 retry_cnt <= 0;
988 FTM_ftu_rs485_control_State <= RATES;
989 end if;
990
991 when DD_RAM_1 =>
992 if (dynamic_RAM_busy = '0') then
993 write_dynamic_RAM <= '1';
994 addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
995 crate_cnt_offset_sig +
996 --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) +
997 --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
998 FTU_cnt_offset_sig +
999 (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1000 if ( (retry_cnt < FTU_RS485_NO_OF_RETRY)
1001 and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG))
1002 and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then
1003 if ((DD_RAM_reg_cnt - 1) = 0) then
1004 data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16);
1005 elsif ((DD_RAM_reg_cnt - 1) = 1) then
1006 data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0);
1007 elsif ((DD_RAM_reg_cnt - 1) = 2) then
1008 data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16);
1009 elsif ((DD_RAM_reg_cnt - 1) = 3) then
1010 data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0);
1011 elsif ((DD_RAM_reg_cnt - 1) = 4) then
1012 data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16);
1013 elsif ((DD_RAM_reg_cnt - 1) = 5) then
1014 data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0);
1015 elsif ((DD_RAM_reg_cnt - 1) = 6) then
1016 data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16);
1017 elsif ((DD_RAM_reg_cnt - 1) = 7) then
1018 data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0);
1019 elsif ((DD_RAM_reg_cnt - 1) = 8) then
1020 data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16);
1021 elsif ((DD_RAM_reg_cnt - 1) = 9) then
1022 data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0);
1023 elsif ((DD_RAM_reg_cnt - 1) = 10) then
1024 data_dynamic_RAM <= "00000000" & FTU_overflow_sig;
1025 elsif ((DD_RAM_reg_cnt - 1) = 11) then
1026 data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig;
1027-- elsif ((DD_RAM_reg_cnt - 1) = 10) then
1028-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1029-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1030-- FTU_cnt_offset_sig +
1031-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1032-- elsif ((DD_RAM_reg_cnt - 1) = 11) then
1033-- --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH);
1034-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1035-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1036-- FTU_cnt_offset_sig +
1037-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1038 end if;
1039 else
1040 data_dynamic_RAM <= (others => '0');
1041 end if;
1042 FTM_ftu_rs485_control_State <= DD_RAM_2;
1043 end if;
1044
1045 when DD_RAM_2 =>
1046 if (dynamic_RAM_started = '1') then
1047 write_dynamic_RAM <= '0';
1048 FTM_ftu_rs485_control_State <= DD_RAM_3;
1049 end if;
1050
1051 when DD_RAM_3 =>
1052 if (dynamic_RAM_ready = '1') then
1053 FTM_ftu_rs485_control_State <= DD_RAM;
1054 end if;
1055
1056 end case;
1057 end if;
1058 end process FTM_ftu_rs485_control_FSM;
1059
1060 -- Process to multiplex the different crate buses
1061 sel_crate_process: process (sel_crate_sig,
1062 rx_en_0_sig, rx_en_1_sig, rx_en_2_sig, rx_en_3_sig,
1063 tx_en_0_sig, tx_en_1_sig, tx_en_2_sig, tx_en_3_sig,
1064 rx_valid_0_sig, rx_valid_1_sig, rx_valid_2_sig, rx_valid_3_sig,
1065 rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
1066 tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
1067 rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig,
1068 tx_start_sig, tx_data_sig)
1069 begin
1070 case sel_crate_sig is
1071 when "000" => -- crate 0
1072 rx_en_sig <= rx_en_0_sig;
1073 tx_en_sig <= tx_en_0_sig;
1074 rx_valid_sig <= rx_valid_0_sig;
1075 rec_data_sig <= rx_data_0_sig;
1076 tx_busy_sig <= tx_busy_0_sig;
1077 rx_busy_sig <= rx_busy_0_sig;
1078 tx_start_0_sig <= tx_start_sig;
1079 tx_start_1_sig <= '0';
1080 tx_start_2_sig <= '0';
1081 tx_start_3_sig <= '0';
1082 tx_data_0_sig <= tx_data_sig;
1083 tx_data_1_sig <= (others => '0');
1084 tx_data_2_sig <= (others => '0');
1085 tx_data_3_sig <= (others => '0');
1086 when "001" => -- crate 1
1087 rx_en_sig <= rx_en_1_sig;
1088 tx_en_sig <= tx_en_1_sig;
1089 rx_valid_sig <= rx_valid_1_sig;
1090 rec_data_sig <= rx_data_1_sig;
1091 tx_busy_sig <= tx_busy_1_sig;
1092 rx_busy_sig <= rx_busy_1_sig;
1093 tx_start_0_sig <= '0';
1094 tx_start_1_sig <= tx_start_sig;
1095 tx_start_2_sig <= '0';
1096 tx_start_3_sig <= '0';
1097 tx_data_0_sig <= (others => '0');
1098 tx_data_1_sig <= tx_data_sig;
1099 tx_data_2_sig <= (others => '0');
1100 tx_data_3_sig <= (others => '0');
1101 when "010" => -- crate 2
1102 rx_en_sig <= rx_en_2_sig;
1103 tx_en_sig <= tx_en_2_sig;
1104 rx_valid_sig <= rx_valid_2_sig;
1105 rec_data_sig <= rx_data_2_sig;
1106 tx_busy_sig <= tx_busy_2_sig;
1107 rx_busy_sig <= rx_busy_2_sig;
1108 tx_start_0_sig <= '0';
1109 tx_start_1_sig <= '0';
1110 tx_start_2_sig <= tx_start_sig;
1111 tx_start_3_sig <= '0';
1112 tx_data_0_sig <= (others => '0');
1113 tx_data_1_sig <= (others => '0');
1114 tx_data_2_sig <= tx_data_sig;
1115 tx_data_3_sig <= (others => '0');
1116 when "011" => -- crate 3
1117 rx_en_sig <= rx_en_3_sig;
1118 tx_en_sig <= tx_en_3_sig;
1119 rx_valid_sig <= rx_valid_3_sig;
1120 rec_data_sig <= rx_data_3_sig;
1121 tx_busy_sig <= tx_busy_3_sig;
1122 rx_busy_sig <= rx_busy_3_sig;
1123 tx_start_0_sig <= '0';
1124 tx_start_1_sig <= '0';
1125 tx_start_2_sig <= '0';
1126 tx_start_3_sig <= tx_start_sig;
1127 tx_data_0_sig <= (others => '0');
1128 tx_data_1_sig <= (others => '0');
1129 tx_data_2_sig <= (others => '0');
1130 tx_data_3_sig <= tx_data_sig;
1131 when others => -- no crate specified
1132 rx_en_sig <= '0';
1133 tx_en_sig <= '0';
1134 rx_valid_sig <= '0';
1135 rec_data_sig <= (others => '0');
1136 tx_busy_sig <= '0';
1137 rx_busy_sig <= '0';
1138 tx_start_0_sig <= '0';
1139 tx_start_1_sig <= '0';
1140 tx_start_2_sig <= '0';
1141 tx_start_3_sig <= '0';
1142 tx_data_0_sig <= (others => '0');
1143 tx_data_1_sig <= (others => '0');
1144 tx_data_2_sig <= (others => '0');
1145 tx_data_3_sig <= (others => '0');
1146 end case;
1147 end process;
1148
1149 -- Process to select the CRC input source (FSM or interpreter)
1150 sel_crc_cource_process : process (sel_crc_input_source_sig,
1151 reset_crc_from_interpreter_sig, reset_crc_from_FSM_sig,
1152 enable_crc_from_interpreter_sig, enable_crc_from_FSM_sig,
1153 rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0), crc_data_from_FSM_sig)
1154 begin
1155 case sel_crc_input_source_sig is
1156 when '0' => -- FSM
1157 reset_crc_sig <= reset_crc_from_FSM_sig;
1158 enable_crc_sig <= enable_crc_from_FSM_sig;
1159 crc_data_sig <= crc_data_from_FSM_sig;
1160 when '1' => -- interpreter
1161 reset_crc_sig <= reset_crc_from_interpreter_sig;
1162 enable_crc_sig <= enable_crc_from_interpreter_sig;
1163 crc_data_sig <= rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0);
1164 when others => -- signal undefined
1165 reset_crc_sig <= reset_crc_from_FSM_sig;
1166 enable_crc_sig <= enable_crc_from_FSM_sig;
1167 crc_data_sig <= crc_data_from_FSM_sig;
1168 end case;
1169 end process;
1170
1171 rx_en <= rx_en_sig;
1172 tx_en <= tx_en_sig;
1173
1174 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
1175 start_int_sig <= rec_valid_sig and (not rx_busy_sig); -- avoid continuing to early after FTU answer
1176
1177end Behavioral;
1178
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