source: firmware/FTM/ftu_control/FTM_ftu_control.vhd@ 14259

Last change on this file since 14259 was 11485, checked in by weitzel, 13 years ago
FTM firmware features now the config_single_FTU command (to be tested); also some defaults were changed
File size: 64.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 17:54:04 02/02/2011
6-- Design Name:
7-- Module Name: FTM_ftu_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Communication of FTM with the 40 FTU boards of the FACT camera
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_ftu_control is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus enables for FTU crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- FTU crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- FTU crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- FTU crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- FTU crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- commands from FTM central control
59 new_config : in std_logic;
60 ping_all : in std_logic;
61 read_rates : in std_logic;
62 config_single_FTU : in std_logic;
63
64 -- answers to FTM central control
65 read_rates_started : out std_logic := '0';
66 read_rates_done : out std_logic := '0';
67 new_config_started : out std_logic := '0';
68 new_config_done : out std_logic := '0';
69 ping_all_started : out std_logic := '0';
70 ping_all_done : out std_logic := '0';
71 config_single_FTU_started : out std_logic := '0';
72 config_single_FTU_done : out std_logic := '0';
73
74 -- active FTU lists
75 ftu_active_cr0 : in std_logic_vector (15 downto 0);
76 ftu_active_cr1 : in std_logic_vector (15 downto 0);
77 ftu_active_cr2 : in std_logic_vector (15 downto 0);
78 ftu_active_cr3 : in std_logic_vector (15 downto 0);
79
80 -- parameter for config single FTU command
81 config_single_FTU_param : in std_logic_vector (15 DOWNTO 0);
82
83 --error message interface to ethernet control
84 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
85 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
86 ftu_error_send : out std_logic := '0';
87 ftu_error_send_ack : in std_logic;
88 ftu_error_send_ready : in std_logic;
89
90 -- communication with static (config) RAM
91 -- this RAM is only read by FTU_control
92 static_RAM_busy : in std_logic;
93 static_RAM_started : in std_logic;
94 static_RAM_ready : in std_logic;
95 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
96 read_static_RAM : out std_logic := '0';
97 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
98
99 -- communication with dynamic RAM (e.g. rates)
100 -- this RAM is only written by FTU_control
101 dynamic_RAM_busy : in std_logic;
102 dynamic_RAM_started : in std_logic;
103 dynamic_RAM_ready : in std_logic;
104 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
105 write_dynamic_RAM : out std_logic := '0';
106 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
107
108 -- communication with FTU-list RAM
109 -- this RAM is only written by FTU_control
110 FTUlist_RAM_busy : in std_logic;
111 FTUlist_RAM_started : in std_logic;
112 FTUlist_RAM_ready : in std_logic;
113 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
114 write_FTUlist_RAM : out std_logic := '0';
115 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
116
117 );
118end FTM_ftu_control;
119
120architecture Behavioral of FTM_ftu_control is
121
122 -- list of active FTUs, read out from static RAM before starting to contact FTUs
123 signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
124 --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0'));
125
126 -- signals to count the number of responding FTUs (per crate and total) in case of a ping
127 signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
128 signal no_of_FTU_answer_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE) := 0;
129
130 -- FTU configuration data, read out from static RAM (board by board)
131 signal FTU_dac_array_RAM_sig : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
132 signal FTU_dac_array_RAM_sig_2 : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
133 signal FTU_enable_array_RAM_sig : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
134 signal FTU_enable_array_RAM_sig_2 : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
135 signal FTU_prescaling_RAM_sig : std_logic_vector(15 downto 0) := (others => '0');
136
137 -- signals for receiver of FTU communication
138 signal rec_reset_sig : std_logic := '0'; -- reset
139 signal rec_data_sig : std_logic_vector (7 DOWNTO 0);
140 signal rec_block_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTM_ftu_rs485_receiver
141 signal rec_valid_sig : std_logic; -- initialized in FTM_ftu_rs485_receiver
142
143 -- select signal to multiplex the different crates
144 signal sel_crate_sig : STD_LOGIC_VECTOR (2 downto 0) := "111";
145
146 -- global signals after multiplexer
147 signal rx_en_sig : std_logic := '0';
148 signal tx_en_sig : std_logic := '0';
149 signal rx_valid_sig : std_logic := '0';
150 signal tx_busy_sig : std_logic := '0';
151 signal tx_start_sig : std_logic := '0';
152 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
153 signal rx_busy_sig : std_logic := '0';
154 signal start_int_sig : std_logic := '0';
155
156 -- signals for interpreter of FTU communication
157 signal FTU_brd_add_sig : std_logic_vector (5 DOWNTO 0) := (others => '0');
158 signal FTU_command_sig : std_logic_vector (7 DOWNTO 0) := (others => '1');
159 signal FTU_answer_ok_sig : std_logic; -- initialized in interpreter
160 signal FTU_dac_array_sig : FTU_dac_array_type; -- initialized in interpreter
161 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter
162 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter
163 signal FTU_overflow_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
164 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
165 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
166 signal FTU_dna_sig : std_logic_vector(63 downto 0); -- initialized in interpreter
167
168 -- rx_enable and tx_enable lines from different FTM_ftu_rs485_interface
169 -- initialized in corresponding interface
170 signal rx_en_0_sig : STD_LOGIC;
171 signal tx_en_0_sig : STD_LOGIC;
172 signal rx_en_1_sig : STD_LOGIC;
173 signal tx_en_1_sig : STD_LOGIC;
174 signal rx_en_2_sig : STD_LOGIC;
175 signal tx_en_2_sig : STD_LOGIC;
176 signal rx_en_3_sig : STD_LOGIC;
177 signal tx_en_3_sig : STD_LOGIC;
178
179 signal tx_start_0_sig : std_logic := '0';
180 signal tx_data_0_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
181 signal tx_busy_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
182 signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
183 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0
184 signal rx_busy_0_sig : std_logic; -- initialized in FTU_rs485_interface_0
185
186 signal tx_start_1_sig : std_logic := '0';
187 signal tx_data_1_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
188 signal tx_busy_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
189 signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
190 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1
191 signal rx_busy_1_sig : std_logic; -- initialized in FTU_rs485_interface_1
192
193 signal tx_start_2_sig : std_logic := '0';
194 signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
195 signal tx_busy_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
196 signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
197 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2
198 signal rx_busy_2_sig : std_logic; -- initialized in FTU_rs485_interface_2
199
200 signal tx_start_3_sig : std_logic := '0';
201 signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
202 signal tx_busy_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
203 signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
204 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3
205 signal rx_busy_3_sig : std_logic; -- initialized in FTU_rs485_interface_3
206
207 -- signals to control and read out CRC
208 signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter
209 signal reset_crc_sig : std_logic;
210 signal enable_crc_sig : std_logic;
211 signal crc_data_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
212 signal reset_crc_from_FSM_sig : std_logic := '0';
213 signal reset_crc_from_interpreter_sig : std_logic;
214 signal enable_crc_from_FSM_sig : std_logic := '0';
215 signal enable_crc_from_interpreter_sig : std_logic;
216 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
217 signal crc_data_from_FSM_sig_cp : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
218 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
219 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
220
221 -- various loop counters
222 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;
223 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0;
224 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0;
225 signal FTU_register_cnt : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) := 0;
226 signal FTU_register_cnt_2 : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG) := 0;
227 signal FTU_command_cnt : integer range 0 to 3 := 0;
228 signal FTU_command_cnt_2 : integer range 0 to 2 := 0;
229 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0;
230 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0;
231 signal FTU_list_header_cnt : integer range 0 to (FTU_LIST_RAM_OFFSET + 1):= 0;
232 signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0;
233
234 -- counter to define timeout and number of retries
235 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
236 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
237
238 --Zwischenrechnungen
239 signal FTU_cnt_offset_sig : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0;
240 signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0;
241
242 --Crate and Slot number for config_single_FTU command
243 signal single_FTU_crate_sig : integer range 0 to 7 := 0;
244 signal single_FTU_slot_sig : integer range 0 to 15 := 0;
245
246 component FTM_ftu_rs485_interface
247 port(
248 clk : IN std_logic;
249 -- RS485
250 rx_d : IN std_logic;
251 rx_en : OUT std_logic;
252 tx_d : OUT std_logic;
253 tx_en : OUT std_logic;
254 -- FPGA
255 rx_data : OUT std_logic_vector (7 DOWNTO 0);
256 rx_busy : OUT std_logic := '0';
257 rx_valid : OUT std_logic := '0';
258 tx_data : IN std_logic_vector (7 DOWNTO 0);
259 tx_busy : OUT std_logic := '0';
260 tx_start : IN std_logic
261 );
262 end component;
263
264 component FTM_ftu_rs485_receiver
265 port(
266 rec_clk : in std_logic;
267 rec_reset : in std_logic;
268 --rx_busy : in std_logic;
269 rec_din : in std_logic_vector(7 downto 0);
270 rec_den : in std_logic;
271 rec_dout : out std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
272 rec_valid : out std_logic := '0'
273 );
274 end component;
275
276 component FTM_ftu_rs485_interpreter
277 port(
278 clk : IN std_logic;
279 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0);
280 block_valid : IN std_logic;
281 crc : IN std_logic_vector(7 downto 0);
282 FTU_brd_add : IN std_logic_vector(5 downto 0);
283 FTU_command : IN std_logic_vector(7 downto 0);
284 reset_crc : OUT std_logic := '0';
285 enable_crc : OUT std_logic := '0';
286 FTU_answer_ok : OUT std_logic := '0';
287 FTU_dac_array : OUT FTU_dac_array_type;
288 FTU_enable_array : OUT FTU_enable_array_type;
289 FTU_rate_array : OUT FTU_rate_array_type;
290 FTU_overflow : OUT std_logic_vector(7 downto 0);
291 FTU_prescaling : OUT std_logic_vector(7 downto 0);
292 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
293 FTU_dna : OUT std_logic_vector(63 downto 0)
294 );
295 end component;
296
297 component ucrc_par
298 generic(
299 POLYNOMIAL : std_logic_vector;
300 INIT_VALUE : std_logic_vector;
301 DATA_WIDTH : integer range 2 to 256;
302 SYNC_RESET : integer range 0 to 1
303 );
304 port(
305 clk_i : in std_logic;
306 rst_i : in std_logic;
307 clken_i : in std_logic;
308 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
309 match_o : out std_logic;
310 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
311 );
312 end component;
313
314 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
315 PING, PING_END, FTU_LIST,
316 SEND_ERROR_1, SEND_ERROR_2,
317 RATES, RATES_1, RATES_2, RATES_3,
318 DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3,
319 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
320 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
321 PING_1, PING_2, PING_3, PING_END_1, PING_END_2, PING_END_3,
322 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3,
323 GET_FTU_PAR, READ_CONFIG_SINGLE_FTU,
324 READ_CONFIG_SINGLE_FTU_1, READ_CONFIG_SINGLE_FTU_2, READ_CONFIG_SINGLE_FTU_3,
325 TRANSMIT_CONFIG_SINGLE_FTU_1, TRANSMIT_CONFIG_SINGLE_FTU_2, TRANSMIT_CONFIG_SINGLE_FTU_3,
326 TRANSMIT_CONFIG_SINGLE_FTU, CONFIG_SINGLE_FTU_END);
327 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
328 signal after_error_State : FTM_ftu_rs485_control_StateType;
329
330begin
331
332 Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0
333 port map(
334 clk => clk_50MHz,
335 -- RS485
336 rx_d => rx_d_0,
337 rx_en => rx_en_0_sig,
338 tx_d => tx_d_0,
339 tx_en => tx_en_0_sig,
340 -- FPGA
341 rx_data => rx_data_0_sig,
342 rx_busy => rx_busy_0_sig,
343 rx_valid => rx_valid_0_sig,
344 tx_data => tx_data_0_sig,
345 tx_busy => tx_busy_0_sig,
346 tx_start => tx_start_0_sig
347 );
348
349 Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1
350 port map(
351 clk => clk_50MHz,
352 -- RS485
353 rx_d => rx_d_1,
354 rx_en => rx_en_1_sig,
355 tx_d => tx_d_1,
356 tx_en => tx_en_1_sig,
357 -- FPGA
358 rx_data => rx_data_1_sig,
359 rx_busy => rx_busy_1_sig,
360 rx_valid => rx_valid_1_sig,
361 tx_data => tx_data_1_sig,
362 tx_busy => tx_busy_1_sig,
363 tx_start => tx_start_1_sig
364 );
365
366 Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2
367 port map(
368 clk => clk_50MHz,
369 -- RS485
370 rx_d => rx_d_2,
371 rx_en => rx_en_2_sig,
372 tx_d => tx_d_2,
373 tx_en => tx_en_2_sig,
374 -- FPGA
375 rx_data => rx_data_2_sig,
376 rx_busy => rx_busy_2_sig,
377 rx_valid => rx_valid_2_sig,
378 tx_data => tx_data_2_sig,
379 tx_busy => tx_busy_2_sig,
380 tx_start => tx_start_2_sig
381 );
382
383 Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3
384 port map(
385 clk => clk_50MHz,
386 -- RS485
387 rx_d => rx_d_3,
388 rx_en => rx_en_3_sig,
389 tx_d => tx_d_3,
390 tx_en => tx_en_3_sig,
391 -- FPGA
392 rx_data => rx_data_3_sig,
393 rx_busy => rx_busy_3_sig,
394 rx_valid => rx_valid_3_sig,
395 tx_data => tx_data_3_sig,
396 tx_busy => tx_busy_3_sig,
397 tx_start => tx_start_3_sig
398 );
399
400 Inst_FTM_ftu_rs485_receiver : FTM_ftu_rs485_receiver
401 port map(
402 rec_clk => clk_50MHz,
403 rec_reset => rec_reset_sig,
404 --rx_busy =>,
405 rec_din => rec_data_sig,
406 rec_den => rx_valid_sig,
407 rec_dout => rec_block_sig,
408 rec_valid => rec_valid_sig
409 );
410
411 Inst_FTM_ftu_rs485_interpreter : FTM_ftu_rs485_interpreter
412 port map(
413 clk => clk_50MHz,
414 data_block => rec_block_sig,
415 block_valid => start_int_sig,
416 crc => crc_sig,
417 FTU_brd_add => FTU_brd_add_sig,
418 FTU_command => FTU_command_sig,
419 reset_crc => reset_crc_from_interpreter_sig,
420 enable_crc => enable_crc_from_interpreter_sig,
421 FTU_answer_ok => FTU_answer_ok_sig,
422 FTU_dac_array => FTU_dac_array_sig,
423 FTU_enable_array => FTU_enable_array_sig,
424 FTU_rate_array => FTU_rate_array_sig,
425 FTU_overflow => FTU_overflow_sig,
426 FTU_prescaling => FTU_prescaling_sig,
427 FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
428 FTU_dna => FTU_dna_sig
429 );
430
431 Inst_ucrc_par : ucrc_par
432 generic map(
433 POLYNOMIAL => CRC_POLYNOMIAL,
434 INIT_VALUE => CRC_INIT_VALUE,
435 DATA_WIDTH => (FTU_RS485_BLOCK_WIDTH - 8),
436 SYNC_RESET => 1
437 )
438 port map(
439 clk_i => clk_50MHz,
440 rst_i => reset_crc_sig,
441 clken_i => enable_crc_sig,
442 data_i => crc_data_sig,
443 match_o => open,
444 crc_o => crc_sig_inv
445 );
446
447 -- Main finite state machine to control all 40 FTUs
448 FTM_ftu_rs485_control_FSM: process (clk_50MHz)
449 begin
450 if Rising_edge(clk_50MHz) then
451 case FTM_ftu_rs485_control_State is
452
453 when INIT => -- reset CRC register
454 reset_crc_from_FSM_sig <= '1';
455 FTM_ftu_rs485_control_State <= IDLE;
456
457 when IDLE => -- wait for command from outside
458 sel_crate_sig <= "111";
459 sel_crc_input_source_sig <= '0';
460 reset_crc_from_FSM_sig <= '0';
461 enable_crc_from_FSM_sig <= '0';
462 --new_config_done <= '0';
463 --ping_all_done <= '0';
464 --read_rates_done <= '0';
465 if (new_config = '1') then
466 new_config_done <= '0';
467 new_config_started <= '1';
468 ping_all_started <= '0';
469 read_rates_started <= '0';
470 config_single_FTU_started <= '0';
471 FTM_ftu_rs485_control_State <= ACTIVE_LIST;
472 elsif (new_config = '0' and ping_all = '1') then
473 ping_all_done <= '0';
474 new_config_started <= '0';
475 ping_all_started <= '1';
476 read_rates_started <= '0';
477 config_single_FTU_started <= '0';
478 rec_reset_sig <= '1';
479 FTM_ftu_rs485_control_State <= PING;
480 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then
481 read_rates_done <= '0';
482 new_config_started <= '0';
483 ping_all_started <= '0';
484 read_rates_started <= '1';
485 config_single_FTU_started <= '0';
486 FTM_ftu_rs485_control_State <= RATES;
487 elsif (new_config = '0' and ping_all = '0' and read_rates = '0' and config_single_FTU = '1') then
488 config_single_FTU_done <= '0';
489 new_config_started <= '0';
490 ping_all_started <= '0';
491 read_rates_started <= '0';
492 config_single_FTU_started <= '1';
493 FTM_ftu_rs485_control_State <= GET_FTU_PAR;
494 else
495 new_config_started <= '0';
496 ping_all_started <= '0';
497 read_rates_started <= '0';
498 config_single_FTU_started <= '0';
499 FTM_ftu_rs485_control_State <= IDLE;
500 end if;
501
502 when ACTIVE_LIST => -- copy active FTU list from inputs to array
503 active_FTU_array_sig(0) <= ftu_active_cr0;
504 active_FTU_array_sig(1) <= ftu_active_cr1;
505 active_FTU_array_sig(2) <= ftu_active_cr2;
506 active_FTU_array_sig(3) <= ftu_active_cr3;
507 FTM_ftu_rs485_control_State <= READ_CONFIG;
508
509 when GET_FTU_PAR => -- copy FTU parameter (crate and slot) from input
510 single_FTU_crate_sig <= conv_integer(unsigned(config_single_FTU_param( 2 downto 0)));
511 single_FTU_slot_sig <= conv_integer(unsigned(config_single_FTU_param(11 downto 8)));
512 FTM_ftu_rs485_control_State <= READ_CONFIG_SINGLE_FTU;
513
514-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list
515-- if (active_FTU_list_cnt < NO_OF_CRATES) then
516-- active_FTU_list_cnt <= active_FTU_list_cnt + 1;
517-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1;
518-- else
519-- active_FTU_list_cnt <= 0;
520-- FTM_ftu_rs485_control_State <= READ_CONFIG;
521-- end if;
522
523-- when ACTIVE_LIST_1 =>
524-- if (static_RAM_busy = '0') then
525-- read_static_RAM <= '1';
526-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH);
527-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2;
528-- end if;
529
530-- when ACTIVE_LIST_2 =>
531-- if (static_RAM_started = '1') then
532-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;
533-- end if;
534
535-- when ACTIVE_LIST_3 =>
536-- if (static_RAM_ready = '1') then
537-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;
538-- read_static_RAM <= '0';
539-- FTM_ftu_rs485_control_State <= ACTIVE_LIST;
540-- end if;
541
542 when READ_CONFIG => -- read configuration of FTUs (one by one)
543 if (crate_cnt < NO_OF_CRATES) then
544 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
545 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
546 if (FTU_register_cnt < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1)) then
547 FTU_register_cnt <= FTU_register_cnt + 1;
548 FTM_ftu_rs485_control_State <= READ_CONFIG_1;
549 else
550 FTU_cnt <= FTU_cnt + 1;
551 FTU_register_cnt <= 0;
552 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
553 rec_reset_sig <= '1';
554 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
555 else
556 FTM_ftu_rs485_control_State <= READ_CONFIG;
557 end if;
558 end if;
559 else
560 crate_cnt <= crate_cnt + 1;
561 FTU_cnt <= 0;
562 FTM_ftu_rs485_control_State <= READ_CONFIG;
563 end if;
564 else
565 crate_cnt <= 0;
566 new_config_started <= '0';
567 new_config_done <= '1';
568 sel_crate_sig <= "111";
569 FTM_ftu_rs485_control_State <= IDLE;
570 end if;
571
572 when READ_CONFIG_SINGLE_FTU => -- read configuration of one FTU
573 sel_crate_sig <= conv_std_logic_vector(single_FTU_crate_sig, 3);
574 if (FTU_register_cnt_2 < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
575 FTU_register_cnt_2 <= FTU_register_cnt_2 + 1;
576 FTM_ftu_rs485_control_State <= READ_CONFIG_SINGLE_FTU_1;
577 else
578 FTU_register_cnt_2 <= 0;
579 if (active_FTU_array_sig(single_FTU_crate_sig)(single_FTU_slot_sig) = '1') then
580 rec_reset_sig <= '1';
581 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU;
582 else
583 FTM_ftu_rs485_control_State <= CONFIG_SINGLE_FTU_END;
584 end if;
585 end if;
586
587 when READ_CONFIG_1 =>
588 if (static_RAM_busy = '0') then
589 read_static_RAM <= '1';
590 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
591 crate_cnt * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
592 FTU_cnt * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
593 (FTU_register_cnt - 1), STATIC_RAM_ADDR_WIDTH);
594 FTM_ftu_rs485_control_State <= READ_CONFIG_2;
595 end if;
596
597 when READ_CONFIG_SINGLE_FTU_1 =>
598 if (static_RAM_busy = '0') then
599 read_static_RAM <= '1';
600 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
601 single_FTU_crate_sig * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
602 single_FTU_slot_sig * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
603 (FTU_register_cnt_2 - 1), STATIC_RAM_ADDR_WIDTH);
604 FTM_ftu_rs485_control_State <= READ_CONFIG_SINGLE_FTU_2;
605 end if;
606
607 when READ_CONFIG_2 =>
608 if (static_RAM_started = '1') then
609 FTM_ftu_rs485_control_State <= READ_CONFIG_3;
610 end if;
611
612 when READ_CONFIG_SINGLE_FTU_2 =>
613 if (static_RAM_started = '1') then
614 FTM_ftu_rs485_control_State <= READ_CONFIG_SINGLE_FTU_3;
615 end if;
616
617 when READ_CONFIG_3 =>
618 if (static_RAM_ready = '1') then
619 if ((FTU_register_cnt - 1) < NO_OF_FTU_ENABLE_REG) then
620 FTU_enable_array_RAM_sig(FTU_register_cnt - 1) <= data_static_RAM;
621 elsif ((FTU_register_cnt - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
622 FTU_dac_array_RAM_sig((FTU_register_cnt - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
623 elsif ((FTU_register_cnt - 1) = (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
624 FTU_prescaling_RAM_sig <= data_static_RAM;
625 end if;
626 read_static_RAM <= '0';
627 FTM_ftu_rs485_control_State <= READ_CONFIG;
628 end if;
629
630 when READ_CONFIG_SINGLE_FTU_3 =>
631 if (static_RAM_ready = '1') then
632 if ((FTU_register_cnt_2 - 1) < NO_OF_FTU_ENABLE_REG) then
633 FTU_enable_array_RAM_sig_2(FTU_register_cnt_2 - 1) <= data_static_RAM;
634 elsif ((FTU_register_cnt_2 - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
635 FTU_dac_array_RAM_sig_2((FTU_register_cnt_2 - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
636 end if;
637 read_static_RAM <= '0';
638 FTM_ftu_rs485_control_State <= READ_CONFIG_SINGLE_FTU;
639 end if;
640
641 when TRANSMIT_CONFIG => -- send configuration to FTUs (one by one)
642 rec_reset_sig <= '0';
643 if (FTU_command_cnt = 0) then -- DACs
644 FTU_command_cnt <= FTU_command_cnt + 1;
645 enable_crc_from_FSM_sig <= '1';
646 crc_data_from_FSM_sig <= "00000000"
647 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
648 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
649 & "00000000"
650 & FTU_dac_array_RAM_sig(4)(15 downto 8) & FTU_dac_array_RAM_sig(4)(7 downto 0)
651 & FTU_dac_array_RAM_sig(3)(15 downto 8) & FTU_dac_array_RAM_sig(3)(7 downto 0)
652 & FTU_dac_array_RAM_sig(2)(15 downto 8) & FTU_dac_array_RAM_sig(2)(7 downto 0)
653 & FTU_dac_array_RAM_sig(1)(15 downto 8) & FTU_dac_array_RAM_sig(1)(7 downto 0)
654 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0)
655 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
656 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
657 & FTU_RS485_START_DELIM;
658 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
659 FTU_command_sig <= "00000000";
660 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
661 elsif (FTU_command_cnt = 1) then -- enables
662 FTU_command_cnt <= FTU_command_cnt + 1;
663 enable_crc_from_FSM_sig <= '1';
664 crc_data_from_FSM_sig <= "00000000"
665 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
666 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
667 & "00000000" & "00000000" & "00000000"
668 & FTU_enable_array_RAM_sig(3)(15 downto 8) & FTU_enable_array_RAM_sig(3)(7 downto 0)
669 & FTU_enable_array_RAM_sig(2)(15 downto 8) & FTU_enable_array_RAM_sig(2)(7 downto 0)
670 & FTU_enable_array_RAM_sig(1)(15 downto 8) & FTU_enable_array_RAM_sig(1)(7 downto 0)
671 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0)
672 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
673 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
674 & FTU_RS485_START_DELIM;
675 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
676 FTU_command_sig <= "00000011";
677 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
678 elsif (FTU_command_cnt = 2) then -- prescaling
679 FTU_command_cnt <= FTU_command_cnt + 1;
680 enable_crc_from_FSM_sig <= '1';
681 crc_data_from_FSM_sig <= "00000000"
682 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
683 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
684 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
685 & "00000000" & "00000000" & "00000000" & "00000000"
686 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0)
687 & "00000110" & FIRMWARE_ID & FTM_ADDRESS
688 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
689 & FTU_RS485_START_DELIM;
690 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
691 FTU_command_sig <= "00000110";
692 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
693 else
694 FTU_command_cnt <= 0;
695 enable_crc_from_FSM_sig <= '0';
696 FTM_ftu_rs485_control_State <= READ_CONFIG;
697 end if;
698
699 when TRANSMIT_CONFIG_SINGLE_FTU => -- send configuration to one FTU
700 rec_reset_sig <= '0';
701 if (FTU_command_cnt_2 = 0) then -- DACs
702 FTU_command_cnt_2 <= FTU_command_cnt_2 + 1;
703 enable_crc_from_FSM_sig <= '1';
704 crc_data_from_FSM_sig <= "00000000"
705 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
706 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
707 & "00000000"
708 & FTU_dac_array_RAM_sig_2(4)(15 downto 8) & FTU_dac_array_RAM_sig_2(4)(7 downto 0)
709 & FTU_dac_array_RAM_sig_2(3)(15 downto 8) & FTU_dac_array_RAM_sig_2(3)(7 downto 0)
710 & FTU_dac_array_RAM_sig_2(2)(15 downto 8) & FTU_dac_array_RAM_sig_2(2)(7 downto 0)
711 & FTU_dac_array_RAM_sig_2(1)(15 downto 8) & FTU_dac_array_RAM_sig_2(1)(7 downto 0)
712 & FTU_dac_array_RAM_sig_2(0)(15 downto 8) & FTU_dac_array_RAM_sig_2(0)(7 downto 0)
713 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
714 & "00" & conv_std_logic_vector(single_FTU_slot_sig,4) & conv_std_logic_vector(single_FTU_crate_sig,2)
715 & FTU_RS485_START_DELIM;
716 FTU_brd_add_sig <= conv_std_logic_vector(single_FTU_slot_sig,4) & conv_std_logic_vector(single_FTU_crate_sig,2);
717 FTU_command_sig <= "00000000";
718 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_1;
719 elsif (FTU_command_cnt_2 = 1) then -- enables
720 FTU_command_cnt_2 <= FTU_command_cnt_2 + 1;
721 enable_crc_from_FSM_sig <= '1';
722 crc_data_from_FSM_sig <= "00000000"
723 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
724 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
725 & "00000000" & "00000000" & "00000000"
726 & FTU_enable_array_RAM_sig_2(3)(15 downto 8) & FTU_enable_array_RAM_sig_2(3)(7 downto 0)
727 & FTU_enable_array_RAM_sig_2(2)(15 downto 8) & FTU_enable_array_RAM_sig_2(2)(7 downto 0)
728 & FTU_enable_array_RAM_sig_2(1)(15 downto 8) & FTU_enable_array_RAM_sig_2(1)(7 downto 0)
729 & FTU_enable_array_RAM_sig_2(0)(15 downto 8) & FTU_enable_array_RAM_sig_2(0)(7 downto 0)
730 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
731 & "00" & conv_std_logic_vector(single_FTU_slot_sig,4) & conv_std_logic_vector(single_FTU_crate_sig,2)
732 & FTU_RS485_START_DELIM;
733 FTU_brd_add_sig <= conv_std_logic_vector(single_FTU_slot_sig,4) & conv_std_logic_vector(single_FTU_crate_sig,2);
734 FTU_command_sig <= "00000011";
735 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_1;
736 else
737 FTU_command_cnt_2 <= 0;
738 enable_crc_from_FSM_sig <= '0';
739 FTM_ftu_rs485_control_State <= CONFIG_SINGLE_FTU_END;
740 end if;
741
742 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation
743 enable_crc_from_FSM_sig <= '0';
744 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
745 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
746
747 when TRANSMIT_CONFIG_SINGLE_FTU_1 => -- wait one cycle for CRC calculation
748 enable_crc_from_FSM_sig <= '0';
749 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
750 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_2;
751
752 when TRANSMIT_CONFIG_2 => -- transmit byte by byte
753 if (tx_busy_sig = '0') then
754 if (frame_cnt < 27) then
755 frame_cnt <= frame_cnt + 1;
756 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
757 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
758 tx_start_sig <= '1';
759 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
760 elsif (frame_cnt = 27) then
761 frame_cnt <= frame_cnt + 1;
762 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
763 tx_data_sig <= crc_sig;
764 tx_start_sig <= '1';
765 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
766 else
767 frame_cnt <= 0;
768 reset_crc_from_FSM_sig <= '1';
769 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
770 end if;
771 else
772 tx_start_sig <= '0';
773 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
774 end if;
775
776 when TRANSMIT_CONFIG_SINGLE_FTU_2 => -- transmit byte by byte
777 if (tx_busy_sig = '0') then
778 if (frame_cnt < 27) then
779 frame_cnt <= frame_cnt + 1;
780 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
781 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
782 tx_start_sig <= '1';
783 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_2;
784 elsif (frame_cnt = 27) then
785 frame_cnt <= frame_cnt + 1;
786 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
787 tx_data_sig <= crc_sig;
788 tx_start_sig <= '1';
789 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_2;
790 else
791 frame_cnt <= 0;
792 reset_crc_from_FSM_sig <= '1';
793 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_3;
794 end if;
795 else
796 tx_start_sig <= '0';
797 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_2;
798 end if;
799
800 when TRANSMIT_CONFIG_3 => -- wait for FTU answer
801 reset_crc_from_FSM_sig <= '0';
802 if (FTU_answer_ok_sig = '1') then
803 timeout_cnt <= 0;
804 retry_cnt <= 0;
805 sel_crc_input_source_sig <= '0';
806 if (retry_cnt = 0) then -- no errors
807 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
808 else -- send error message and move to next command;
809 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
810 after_error_State <= TRANSMIT_CONFIG;
811 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
812 end if;
813 else
814 if (timeout_cnt < FTU_RS485_TIMEOUT) then
815 timeout_cnt <= timeout_cnt + 1;
816 sel_crc_input_source_sig <= '1';
817 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
818 else
819 timeout_cnt <= 0;
820 sel_crc_input_source_sig <= '0';
821 rec_reset_sig <= '1';
822 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
823 retry_cnt <= retry_cnt + 1;
824 FTU_command_cnt <= FTU_command_cnt - 1; -- try this command again
825 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
826 else
827 retry_cnt <= 0;
828 FTU_command_cnt <= FTU_command_cnt; -- send error message and move to next command
829 ftu_error_calls <= (others => '0');
830 after_error_State <= TRANSMIT_CONFIG;
831 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
832 end if;
833 end if;
834 end if;
835
836 when TRANSMIT_CONFIG_SINGLE_FTU_3 => -- wait for FTU answer
837 reset_crc_from_FSM_sig <= '0';
838 if (FTU_answer_ok_sig = '1') then
839 timeout_cnt <= 0;
840 retry_cnt <= 0;
841 sel_crc_input_source_sig <= '0';
842 if (retry_cnt = 0) then -- no errors
843 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU;
844 else -- send error message and move to next command;
845 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
846 after_error_State <= TRANSMIT_CONFIG_SINGLE_FTU;
847 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
848 end if;
849 else
850 if (timeout_cnt < FTU_RS485_TIMEOUT) then
851 timeout_cnt <= timeout_cnt + 1;
852 sel_crc_input_source_sig <= '1';
853 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU_3;
854 else
855 timeout_cnt <= 0;
856 sel_crc_input_source_sig <= '0';
857 rec_reset_sig <= '1';
858 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
859 retry_cnt <= retry_cnt + 1;
860 FTU_command_cnt_2 <= FTU_command_cnt_2 - 1; -- try this command again
861 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_SINGLE_FTU;
862 else
863 retry_cnt <= 0;
864 FTU_command_cnt_2 <= FTU_command_cnt_2; -- send error message and move to next command
865 ftu_error_calls <= (others => '0');
866 after_error_State <= TRANSMIT_CONFIG_SINGLE_FTU;
867 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
868 end if;
869 end if;
870 end if;
871
872 when SEND_ERROR_1 => -- send an error message
873 ftu_error_send <= '1';
874 if (ftu_error_send_ack = '1') then
875 ftu_error_send <= '0';
876 FTM_ftu_rs485_control_State <= SEND_ERROR_2;
877 end if;
878
879 when SEND_ERROR_2 =>
880 if (ftu_error_send_ready = '1') then
881 FTM_ftu_rs485_control_State <= after_error_state;
882 end if;
883
884 when CONFIG_SINGLE_FTU_END =>
885 config_single_FTU_started <= '0';
886 config_single_FTU_done <= '1';
887 sel_crate_sig <= "111";
888 FTM_ftu_rs485_control_State <= IDLE;
889
890 when PING => -- ping all FTUs
891 rec_reset_sig <= '0';
892 if (crate_cnt < NO_OF_CRATES) then
893 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
894 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
895 FTU_cnt <= FTU_cnt + 1;
896 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
897 enable_crc_from_FSM_sig <= '1';
898 crc_data_from_FSM_sig <= "00000000"
899 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
900 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
901 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
902 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
903 & "00000101" & FIRMWARE_ID & FTM_ADDRESS
904 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
905 & FTU_RS485_START_DELIM;
906 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
907 FTU_command_sig <= "00000101";
908 FTM_ftu_rs485_control_State <= PING_1;
909 else
910 FTM_ftu_rs485_control_State <= PING;
911 end if;
912 else
913 crate_cnt <= crate_cnt + 1;
914 FTU_cnt <= 0;
915 FTM_ftu_rs485_control_State <= PING;
916 end if;
917 else
918 crate_cnt <= 0;
919 FTM_ftu_rs485_control_State <= PING_END;
920 end if;
921
922 when PING_1 => -- wait one cycle for CRC calculation
923 enable_crc_from_FSM_sig <= '0';
924 --rec_reset_sig <= '1';
925 FTM_ftu_rs485_control_State <= PING_2;
926
927 when PING_2 => -- transmit byte by byte
928 rec_reset_sig <= '0';
929 if (tx_busy_sig = '0') then
930 if (frame_cnt < 27) then
931 frame_cnt <= frame_cnt + 1;
932 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
933 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
934 tx_start_sig <= '1';
935 FTM_ftu_rs485_control_State <= PING_2;
936 elsif (frame_cnt = 27) then
937 frame_cnt <= frame_cnt + 1;
938 tx_data_sig <= crc_sig;
939 tx_start_sig <= '1';
940 rec_reset_sig <= '1'; -- new
941 FTM_ftu_rs485_control_State <= PING_2;
942 else
943 frame_cnt <= 0;
944 reset_crc_from_FSM_sig <= '1';
945 FTM_ftu_rs485_control_State <= PING_3;
946 end if;
947 else
948 tx_start_sig <= '0';
949 FTM_ftu_rs485_control_State <= PING_2;
950 end if;
951
952 when PING_3 => -- wait for FTU answer
953 reset_crc_from_FSM_sig <= '0';
954 if (FTU_answer_ok_sig = '1') then
955 FTU_answer_array_sig(crate_cnt) <= FTU_answer_array_sig(crate_cnt) + 1;
956 no_of_FTU_answer_sig <= no_of_FTU_answer_sig + 1;
957 timeout_cnt <= 0;
958 sel_crc_input_source_sig <= '0';
959 FTM_ftu_rs485_control_State <= FTU_LIST;
960 else
961 if (timeout_cnt < FTU_RS485_TIMEOUT) then
962 timeout_cnt <= timeout_cnt + 1;
963 sel_crc_input_source_sig <= '1';
964 FTM_ftu_rs485_control_State <= PING_3;
965 else
966 timeout_cnt <= 0;
967 sel_crc_input_source_sig <= '0';
968 rec_reset_sig <= '1';
969 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
970 retry_cnt <= retry_cnt + 1;
971 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
972 FTM_ftu_rs485_control_State <= PING;
973 else
974 FTU_cnt <= FTU_cnt; -- move on
975 FTM_ftu_rs485_control_State <= FTU_LIST;
976 end if;
977 end if;
978 end if;
979
980 when FTU_LIST => -- fill FTU-list for actual FTU
981 rec_reset_sig <= '0';
982 if (FTU_list_reg_cnt < NO_OF_FTU_LIST_REG) then
983 FTU_list_reg_cnt <= FTU_list_reg_cnt + 1;
984 FTM_ftu_rs485_control_State <= FTU_LIST_1;
985 else
986 FTU_list_reg_cnt <= 0;
987 retry_cnt <= 0;
988 FTM_ftu_rs485_control_State <= PING;
989 end if;
990
991 when FTU_LIST_1 =>
992 if (FTUlist_RAM_busy = '0') then
993 write_FTUlist_RAM <= '1';
994 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
995 (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) +
996 ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) +
997 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
998 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
999 if ((FTU_list_reg_cnt - 1) = 0) then
1000 data_FTUlist_RAM <= "000000" & conv_std_logic_vector((retry_cnt + 1),2) & "00" & FTU_brd_add_sig;
1001 elsif ((FTU_list_reg_cnt - 1) = 1) then
1002 data_FTUlist_RAM <= FTU_dna_sig(63 downto 48);
1003 elsif ((FTU_list_reg_cnt - 1) = 2) then
1004 data_FTUlist_RAM <= FTU_dna_sig(47 downto 32);
1005 elsif ((FTU_list_reg_cnt - 1) = 3) then
1006 data_FTUlist_RAM <= FTU_dna_sig(31 downto 16);
1007 elsif ((FTU_list_reg_cnt - 1) = 4) then
1008 data_FTUlist_RAM <= FTU_dna_sig(15 downto 0);
1009 elsif ((FTU_list_reg_cnt - 1) = 5) then
1010 data_FTUlist_RAM <= "00000000" & FTU_crc_error_cnt_sig;
1011 end if;
1012 else
1013 data_FTUlist_RAM <= (others => '0');
1014 end if;
1015 FTM_ftu_rs485_control_State <= FTU_LIST_2;
1016 end if;
1017
1018 when FTU_LIST_2 =>
1019 if (FTUlist_RAM_started = '1') then
1020 write_FTUlist_RAM <= '0';
1021 FTM_ftu_rs485_control_State <= FTU_LIST_3;
1022 end if;
1023
1024 when FTU_LIST_3 =>
1025 if (FTUlist_RAM_ready = '1') then
1026 FTM_ftu_rs485_control_State <= FTU_LIST;
1027 end if;
1028
1029 when PING_END => -- add final ping statistics to FTU-list
1030 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then
1031 --FTU_list_header_cnt <= FTU_list_header_cnt + 1;
1032 FTM_ftu_rs485_control_State <= PING_END_1;
1033 else
1034 FTU_list_header_cnt <= 0;
1035 ping_all_started <= '0';
1036 ping_all_done <= '1';
1037 sel_crate_sig <= "111";
1038 FTU_answer_array_sig(0) <= 0;
1039 FTU_answer_array_sig(1) <= 0;
1040 FTU_answer_array_sig(2) <= 0;
1041 FTU_answer_array_sig(3) <= 0;
1042 no_of_FTU_answer_sig <= 0;
1043 FTM_ftu_rs485_control_State <= IDLE;
1044 end if;
1045
1046 when PING_END_1 =>
1047 if (FTUlist_RAM_busy = '0') then
1048 write_FTUlist_RAM <= '1';
1049 --addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
1050 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt), FTU_LIST_RAM_ADDR_WIDTH);
1051 --if ((FTU_list_header_cnt - 1) = 0) then
1052 if ((FTU_list_header_cnt) = 0) then
1053 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16);
1054 --elsif ((FTU_list_header_cnt - 1) < 5) then
1055 elsif ((FTU_list_header_cnt) < 5) then
1056 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16);
1057 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 1), 16);
1058 --elsif ((FTU_list_header_cnt - 1) < 9) then
1059 elsif ((FTU_list_header_cnt) < 9) then
1060 --data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6);
1061 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_list_header_cnt - 6, 16);
1062 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 5);
1063 end if;
1064 FTM_ftu_rs485_control_State <= PING_END_2;
1065 end if;
1066
1067 when PING_END_2 =>
1068 if (FTUlist_RAM_started = '1') then
1069 write_FTUlist_RAM <= '0';
1070 FTM_ftu_rs485_control_State <= PING_END_3;
1071 end if;
1072
1073 when PING_END_3 =>
1074 if (FTUlist_RAM_ready = '1') then
1075 FTU_list_header_cnt <= FTU_list_header_cnt + 1;
1076 FTM_ftu_rs485_control_State <= PING_END;
1077 end if;
1078
1079 when RATES => -- read all FTU rates
1080 rec_reset_sig <= '0';
1081 if (crate_cnt < NO_OF_CRATES) then
1082 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
1083 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
1084 FTU_cnt <= FTU_cnt + 1;
1085 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
1086 enable_crc_from_FSM_sig <= '1';
1087 crc_data_from_FSM_sig <= "00000000"
1088 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
1089 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
1090 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
1091 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
1092 & "00000010" & FIRMWARE_ID & FTM_ADDRESS
1093 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
1094 & FTU_RS485_START_DELIM;
1095 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
1096 FTU_command_sig <= "00000010";
1097 FTM_ftu_rs485_control_State <= RATES_1;
1098 else
1099 FTM_ftu_rs485_control_State <= RATES;
1100 end if;
1101 else
1102 crate_cnt <= crate_cnt + 1;
1103 FTU_cnt <= 0;
1104 FTM_ftu_rs485_control_State <= RATES;
1105 end if;
1106 else
1107 crate_cnt <= 0;
1108 read_rates_started <= '0';
1109 read_rates_done <= '1';
1110 sel_crate_sig <= "111";
1111 FTM_ftu_rs485_control_State <= IDLE;
1112 end if;
1113
1114 when RATES_1 => -- wait one cycle for CRC calculation
1115 enable_crc_from_FSM_sig <= '0';
1116 --rec_reset_sig <= '1'; --new
1117 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
1118 FTM_ftu_rs485_control_State <= RATES_2;
1119
1120 when RATES_2 => -- transmit byte by byte
1121 rec_reset_sig <= '0'; --new
1122 if (tx_busy_sig = '0') then
1123 if (frame_cnt < 27) then
1124 frame_cnt <= frame_cnt + 1;
1125 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
1126 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
1127 tx_start_sig <= '1';
1128 FTM_ftu_rs485_control_State <= RATES_2;
1129 elsif (frame_cnt = 27) then
1130 frame_cnt <= frame_cnt + 1;
1131 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
1132 tx_data_sig <= crc_sig;
1133 tx_start_sig <= '1';
1134 rec_reset_sig <= '1';
1135 FTM_ftu_rs485_control_State <= RATES_2;
1136 else
1137 frame_cnt <= 0;
1138 reset_crc_from_FSM_sig <= '1';
1139 FTM_ftu_rs485_control_State <= RATES_3;
1140 end if;
1141 else
1142 tx_start_sig <= '0';
1143 FTM_ftu_rs485_control_State <= RATES_2;
1144 end if;
1145
1146 when RATES_3 => -- wait for FTU answer
1147 reset_crc_from_FSM_sig <= '0';
1148 if (FTU_answer_ok_sig = '1') then
1149 timeout_cnt <= 0;
1150 sel_crc_input_source_sig <= '0';
1151 --FTM_ftu_rs485_control_State <= RATES;
1152 if (retry_cnt = 0) then -- no errors
1153 FTM_ftu_rs485_control_State <= DD_RAM;
1154 else -- send error message and move to next command;
1155 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
1156 after_error_State <= DD_RAM;
1157 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
1158 end if;
1159 else
1160 if (timeout_cnt < FTU_RS485_TIMEOUT) then
1161 timeout_cnt <= timeout_cnt + 1;
1162 sel_crc_input_source_sig <= '1';
1163 FTM_ftu_rs485_control_State <= RATES_3;
1164 else
1165 timeout_cnt <= 0;
1166 sel_crc_input_source_sig <= '0';
1167 rec_reset_sig <= '1';
1168 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
1169 retry_cnt <= retry_cnt + 1;
1170 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
1171 FTM_ftu_rs485_control_State <= RATES;
1172 else
1173 --retry_cnt <= 0;
1174 FTU_cnt <= FTU_cnt; -- move on
1175 ftu_error_calls <= (others => '0');
1176 after_error_State <= DD_RAM;
1177 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
1178 end if;
1179 end if;
1180 end if;
1181
1182 when DD_RAM => -- write rates of actual FTU to DD RAM
1183 rec_reset_sig <= '0';
1184 if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then
1185 DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1;
1186 FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG);
1187 crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG);
1188 FTM_ftu_rs485_control_State <= DD_RAM_1;
1189 else
1190 DD_RAM_reg_cnt <= 0;
1191 retry_cnt <= 0;
1192 FTM_ftu_rs485_control_State <= RATES;
1193 end if;
1194
1195 when DD_RAM_1 =>
1196 if (dynamic_RAM_busy = '0') then
1197 write_dynamic_RAM <= '1';
1198 addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1199 crate_cnt_offset_sig +
1200 --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) +
1201 --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1202 FTU_cnt_offset_sig +
1203 (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1204 if ( (retry_cnt < FTU_RS485_NO_OF_RETRY)
1205 and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG))
1206 and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then
1207 if ((DD_RAM_reg_cnt - 1) = 0) then
1208 data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16);
1209 elsif ((DD_RAM_reg_cnt - 1) = 1) then
1210 data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0);
1211 elsif ((DD_RAM_reg_cnt - 1) = 2) then
1212 data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16);
1213 elsif ((DD_RAM_reg_cnt - 1) = 3) then
1214 data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0);
1215 elsif ((DD_RAM_reg_cnt - 1) = 4) then
1216 data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16);
1217 elsif ((DD_RAM_reg_cnt - 1) = 5) then
1218 data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0);
1219 elsif ((DD_RAM_reg_cnt - 1) = 6) then
1220 data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16);
1221 elsif ((DD_RAM_reg_cnt - 1) = 7) then
1222 data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0);
1223 elsif ((DD_RAM_reg_cnt - 1) = 8) then
1224 data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16);
1225 elsif ((DD_RAM_reg_cnt - 1) = 9) then
1226 data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0);
1227 elsif ((DD_RAM_reg_cnt - 1) = 10) then
1228 data_dynamic_RAM <= "00000000" & FTU_overflow_sig;
1229 elsif ((DD_RAM_reg_cnt - 1) = 11) then
1230 data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig;
1231-- elsif ((DD_RAM_reg_cnt - 1) = 10) then
1232-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1233-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1234-- FTU_cnt_offset_sig +
1235-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1236-- elsif ((DD_RAM_reg_cnt - 1) = 11) then
1237-- --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH);
1238-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1239-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1240-- FTU_cnt_offset_sig +
1241-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1242 end if;
1243 else
1244 data_dynamic_RAM <= (others => '0');
1245 end if;
1246 FTM_ftu_rs485_control_State <= DD_RAM_2;
1247 end if;
1248
1249 when DD_RAM_2 =>
1250 if (dynamic_RAM_started = '1') then
1251 write_dynamic_RAM <= '0';
1252 FTM_ftu_rs485_control_State <= DD_RAM_3;
1253 end if;
1254
1255 when DD_RAM_3 =>
1256 if (dynamic_RAM_ready = '1') then
1257 FTM_ftu_rs485_control_State <= DD_RAM;
1258 end if;
1259
1260 end case;
1261 end if;
1262 end process FTM_ftu_rs485_control_FSM;
1263
1264 -- Process to multiplex the different crate buses
1265 sel_crate_process: process (sel_crate_sig,
1266 rx_en_0_sig, rx_en_1_sig, rx_en_2_sig, rx_en_3_sig,
1267 tx_en_0_sig, tx_en_1_sig, tx_en_2_sig, tx_en_3_sig,
1268 rx_valid_0_sig, rx_valid_1_sig, rx_valid_2_sig, rx_valid_3_sig,
1269 rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
1270 tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
1271 rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig,
1272 tx_start_sig, tx_data_sig)
1273 begin
1274 case sel_crate_sig is
1275 when "000" => -- crate 0
1276 rx_en_sig <= rx_en_0_sig;
1277 tx_en_sig <= tx_en_0_sig;
1278 rx_valid_sig <= rx_valid_0_sig;
1279 rec_data_sig <= rx_data_0_sig;
1280 tx_busy_sig <= tx_busy_0_sig;
1281 rx_busy_sig <= rx_busy_0_sig;
1282 tx_start_0_sig <= tx_start_sig;
1283 tx_start_1_sig <= '0';
1284 tx_start_2_sig <= '0';
1285 tx_start_3_sig <= '0';
1286 tx_data_0_sig <= tx_data_sig;
1287 tx_data_1_sig <= (others => '0');
1288 tx_data_2_sig <= (others => '0');
1289 tx_data_3_sig <= (others => '0');
1290 when "001" => -- crate 1
1291 rx_en_sig <= rx_en_1_sig;
1292 tx_en_sig <= tx_en_1_sig;
1293 rx_valid_sig <= rx_valid_1_sig;
1294 rec_data_sig <= rx_data_1_sig;
1295 tx_busy_sig <= tx_busy_1_sig;
1296 rx_busy_sig <= rx_busy_1_sig;
1297 tx_start_0_sig <= '0';
1298 tx_start_1_sig <= tx_start_sig;
1299 tx_start_2_sig <= '0';
1300 tx_start_3_sig <= '0';
1301 tx_data_0_sig <= (others => '0');
1302 tx_data_1_sig <= tx_data_sig;
1303 tx_data_2_sig <= (others => '0');
1304 tx_data_3_sig <= (others => '0');
1305 when "010" => -- crate 2
1306 rx_en_sig <= rx_en_2_sig;
1307 tx_en_sig <= tx_en_2_sig;
1308 rx_valid_sig <= rx_valid_2_sig;
1309 rec_data_sig <= rx_data_2_sig;
1310 tx_busy_sig <= tx_busy_2_sig;
1311 rx_busy_sig <= rx_busy_2_sig;
1312 tx_start_0_sig <= '0';
1313 tx_start_1_sig <= '0';
1314 tx_start_2_sig <= tx_start_sig;
1315 tx_start_3_sig <= '0';
1316 tx_data_0_sig <= (others => '0');
1317 tx_data_1_sig <= (others => '0');
1318 tx_data_2_sig <= tx_data_sig;
1319 tx_data_3_sig <= (others => '0');
1320 when "011" => -- crate 3
1321 rx_en_sig <= rx_en_3_sig;
1322 tx_en_sig <= tx_en_3_sig;
1323 rx_valid_sig <= rx_valid_3_sig;
1324 rec_data_sig <= rx_data_3_sig;
1325 tx_busy_sig <= tx_busy_3_sig;
1326 rx_busy_sig <= rx_busy_3_sig;
1327 tx_start_0_sig <= '0';
1328 tx_start_1_sig <= '0';
1329 tx_start_2_sig <= '0';
1330 tx_start_3_sig <= tx_start_sig;
1331 tx_data_0_sig <= (others => '0');
1332 tx_data_1_sig <= (others => '0');
1333 tx_data_2_sig <= (others => '0');
1334 tx_data_3_sig <= tx_data_sig;
1335 when others => -- no crate specified
1336 rx_en_sig <= '0';
1337 tx_en_sig <= '0';
1338 rx_valid_sig <= '0';
1339 rec_data_sig <= (others => '0');
1340 tx_busy_sig <= '0';
1341 rx_busy_sig <= '0';
1342 tx_start_0_sig <= '0';
1343 tx_start_1_sig <= '0';
1344 tx_start_2_sig <= '0';
1345 tx_start_3_sig <= '0';
1346 tx_data_0_sig <= (others => '0');
1347 tx_data_1_sig <= (others => '0');
1348 tx_data_2_sig <= (others => '0');
1349 tx_data_3_sig <= (others => '0');
1350 end case;
1351 end process;
1352
1353 -- Process to select the CRC input source (FSM or interpreter)
1354 sel_crc_cource_process : process (sel_crc_input_source_sig,
1355 reset_crc_from_interpreter_sig, reset_crc_from_FSM_sig,
1356 enable_crc_from_interpreter_sig, enable_crc_from_FSM_sig,
1357 rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0), crc_data_from_FSM_sig)
1358 begin
1359 case sel_crc_input_source_sig is
1360 when '0' => -- FSM
1361 reset_crc_sig <= reset_crc_from_FSM_sig;
1362 enable_crc_sig <= enable_crc_from_FSM_sig;
1363 crc_data_sig <= crc_data_from_FSM_sig;
1364 when '1' => -- interpreter
1365 reset_crc_sig <= reset_crc_from_interpreter_sig;
1366 enable_crc_sig <= enable_crc_from_interpreter_sig;
1367 crc_data_sig <= rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0);
1368 when others => -- signal undefined
1369 reset_crc_sig <= reset_crc_from_FSM_sig;
1370 enable_crc_sig <= enable_crc_from_FSM_sig;
1371 crc_data_sig <= crc_data_from_FSM_sig;
1372 end case;
1373 end process;
1374
1375 rx_en <= rx_en_sig;
1376 tx_en <= tx_en_sig;
1377
1378 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
1379 start_int_sig <= rec_valid_sig and (not rx_busy_sig); -- avoid continuing to early after FTU answer
1380
1381end Behavioral;
1382
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