source: firmware/FTM/ftu_control/FTM_ftu_control.vhd@ 10247

Last change on this file since 10247 was 10227, checked in by weitzel, 14 years ago
first version of FTM firmware including ethernet and FTU interface; still some debugging needed
File size: 40.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 17:54:04 02/02/2011
6-- Design Name:
7-- Module Name: FTM_ftu_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Communication of FTM with the 40 FTU boards of the FACT camera
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_ftu_control is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus enables for FTU crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- FTU crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- FTU crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- FTU crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- FTU crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- commands from FTM main control
59 new_config : in std_logic;
60 ping_all : in std_logic;
61 read_rates : in std_logic;
62
63 -- answers to FTM main control
64 read_rates_started : out std_logic := '0';
65 read_rates_done : out std_logic := '0';
66 new_config_started : out std_logic := '0';
67 new_config_done : out std_logic := '0';
68 ping_all_started : out std_logic := '0';
69 ping_all_done : out std_logic := '0';
70
71 -- active FTU lists
72 ftu_active_cr0 : in std_logic_vector (15 downto 0);
73 ftu_active_cr1 : in std_logic_vector (15 downto 0);
74 ftu_active_cr2 : in std_logic_vector (15 downto 0);
75 ftu_active_cr3 : in std_logic_vector (15 downto 0);
76
77 -- communication with static (config) RAM
78 -- this RAM is only read by FTU_control
79 static_RAM_busy : in std_logic;
80 static_RAM_started : in std_logic;
81 static_RAM_ready : in std_logic;
82 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
83 read_static_RAM : out std_logic := '0';
84 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
85
86 -- communication with dynamic RAM (e.g. rates)
87 -- this RAM is only written by FTU_control
88 dynamic_RAM_busy : in std_logic;
89 dynamic_RAM_started : in std_logic;
90 dynamic_RAM_ready : in std_logic;
91 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
92 write_dynamic_RAM : out std_logic := '0';
93 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
94
95 -- communication with FTU-list RAM
96 -- this RAM is only written by FTU_control
97 FTUlist_RAM_busy : in std_logic;
98 FTUlist_RAM_started : in std_logic;
99 FTUlist_RAM_ready : in std_logic;
100 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
101 write_FTUlist_RAM : out std_logic := '0';
102 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
103
104 );
105end FTM_ftu_control;
106
107architecture Behavioral of FTM_ftu_control is
108
109 -- list of active FTUs, read out from static RAM before starting to contact FTUs
110 signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
111
112 -- signals to count the number of responding FTUs (per crate and total) in case of a ping
113 signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
114 signal no_of_FTU_answer_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE) := 0;
115
116 -- FTU configuration data, read out from static RAM (board by board)
117 signal FTU_dac_array_RAM_sig : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
118 signal FTU_enable_array_RAM_sig : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
119 signal FTU_prescaling_RAM_sig : std_logic_vector(15 downto 0) := (others => '0');
120
121 -- signals for receiver of FTU communication
122 signal rec_reset_sig : std_logic := '0'; -- reset
123 signal rec_data_sig : std_logic_vector (7 DOWNTO 0);
124 signal rec_block_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTM_ftu_rs485_receiver
125 signal rec_valid_sig : std_logic; -- initialized in FTM_ftu_rs485_receiver
126
127 -- select signal to multiplex the different crates
128 signal sel_crate_sig : STD_LOGIC_VECTOR (2 downto 0) := "111";
129
130 -- global signals after multiplexer
131 signal rx_en_sig : std_logic := '0';
132 signal tx_en_sig : std_logic := '0';
133 signal rx_valid_sig : std_logic := '0';
134 signal tx_busy_sig : std_logic := '0';
135 signal tx_start_sig : std_logic := '0';
136 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
137
138 -- signals for interpreter of FTU communication
139 signal FTU_brd_add_sig : std_logic_vector (5 DOWNTO 0) := (others => '0');
140 signal FTU_command_sig : std_logic_vector (7 DOWNTO 0) := (others => '1');
141 signal FTU_answer_ok_sig : std_logic; -- initialized in interpreter
142 signal FTU_dac_array_sig : FTU_dac_array_type; -- initialized in interpreter
143 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter
144 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter
145 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
146 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
147 signal FTU_dna_sig : std_logic_vector(63 downto 0); -- initialized in interpreter
148
149 -- rx_enable and tx_enable lines from different FTM_ftu_rs485_interface
150 -- initialized in corresponding interface
151 signal rx_en_0_sig : STD_LOGIC;
152 signal tx_en_0_sig : STD_LOGIC;
153 signal rx_en_1_sig : STD_LOGIC;
154 signal tx_en_1_sig : STD_LOGIC;
155 signal rx_en_2_sig : STD_LOGIC;
156 signal tx_en_2_sig : STD_LOGIC;
157 signal rx_en_3_sig : STD_LOGIC;
158 signal tx_en_3_sig : STD_LOGIC;
159
160 signal tx_start_0_sig : std_logic := '0';
161 signal tx_data_0_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
162 signal tx_busy_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
163 signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
164 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0
165
166 signal tx_start_1_sig : std_logic := '0';
167 signal tx_data_1_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
168 signal tx_busy_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
169 signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
170 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1
171
172 signal tx_start_2_sig : std_logic := '0';
173 signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
174 signal tx_busy_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
175 signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
176 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2
177
178 signal tx_start_3_sig : std_logic := '0';
179 signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
180 signal tx_busy_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
181 signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
182 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3
183
184 -- signals to control and read out CRC
185 signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter
186 signal reset_crc_sig : std_logic;
187 signal enable_crc_sig : std_logic;
188 signal crc_data_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
189 signal reset_crc_from_FSM_sig : std_logic := '0';
190 signal reset_crc_from_interpreter_sig : std_logic;
191 signal enable_crc_from_FSM_sig : std_logic := '0';
192 signal enable_crc_from_interpreter_sig : std_logic;
193 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
194 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
195 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
196
197 -- various loop counters
198 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;
199 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0;
200 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0;
201 signal FTU_register_cnt : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) := 0;
202 signal FTU_command_cnt : integer range 0 to 3 := 0;
203 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0;
204 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0;
205 signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0;
206
207 -- counter to define timeout and number of retries
208 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
209 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
210
211 component FTM_ftu_rs485_interface
212 port(
213 clk : IN std_logic;
214 -- RS485
215 rx_d : IN std_logic;
216 rx_en : OUT std_logic;
217 tx_d : OUT std_logic;
218 tx_en : OUT std_logic;
219 -- FPGA
220 rx_data : OUT std_logic_vector (7 DOWNTO 0);
221 --rx_busy : OUT std_logic := '0';
222 rx_valid : OUT std_logic := '0';
223 tx_data : IN std_logic_vector (7 DOWNTO 0);
224 tx_busy : OUT std_logic := '0';
225 tx_start : IN std_logic
226 );
227 end component;
228
229 component FTM_ftu_rs485_receiver
230 port(
231 rec_clk : in std_logic;
232 rec_reset : in std_logic;
233 --rx_busy : in std_logic;
234 rec_din : in std_logic_vector(7 downto 0);
235 rec_den : in std_logic;
236 rec_dout : out std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
237 rec_valid : out std_logic := '0'
238 );
239 end component;
240
241 component FTM_ftu_rs485_interpreter
242 port(
243 clk : IN std_logic;
244 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0);
245 block_valid : IN std_logic;
246 crc : IN std_logic_vector(7 downto 0);
247 FTU_brd_add : IN std_logic_vector(5 downto 0);
248 FTU_command : IN std_logic_vector(7 downto 0);
249 reset_crc : OUT std_logic := '0';
250 enable_crc : OUT std_logic := '0';
251 FTU_answer_ok : OUT std_logic := '0';
252 FTU_dac_array : OUT FTU_dac_array_type;
253 FTU_enable_array : OUT FTU_enable_array_type;
254 FTU_rate_array : OUT FTU_rate_array_type;
255 FTU_prescaling : OUT std_logic_vector(7 downto 0);
256 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
257 FTU_dna : OUT std_logic_vector(63 downto 0)
258 );
259 end component;
260
261 component ucrc_par
262 generic(
263 POLYNOMIAL : std_logic_vector;
264 INIT_VALUE : std_logic_vector;
265 DATA_WIDTH : integer range 2 to 256;
266 SYNC_RESET : integer range 0 to 1
267 );
268 port(
269 clk_i : in std_logic;
270 rst_i : in std_logic;
271 clken_i : in std_logic;
272 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
273 match_o : out std_logic;
274 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
275 );
276 end component;
277
278 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
279 PING, PING_END, FTU_LIST, RATES,
280 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
281 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
282 PING_1, PING_2, PING_3, PING_END_1, PING_END_2, PING_END_3,
283 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3);
284 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
285
286begin
287
288 Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0
289 port map(
290 clk => clk_50MHz,
291 -- RS485
292 rx_d => rx_d_0,
293 rx_en => rx_en_0_sig,
294 tx_d => tx_d_0,
295 tx_en => tx_en_0_sig,
296 -- FPGA
297 rx_data => rx_data_0_sig,
298 --rx_busy => ,
299 rx_valid => rx_valid_0_sig,
300 tx_data => tx_data_0_sig,
301 tx_busy => tx_busy_0_sig,
302 tx_start => tx_start_0_sig
303 );
304
305 Inst_FTM_fTU_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1
306 port map(
307 clk => clk_50MHz,
308 -- RS485
309 rx_d => rx_d_1,
310 rx_en => rx_en_1_sig,
311 tx_d => tx_d_1,
312 tx_en => tx_en_1_sig,
313 -- FPGA
314 rx_data => rx_data_1_sig,
315 --rx_busy => ,
316 rx_valid => rx_valid_1_sig,
317 tx_data => tx_data_1_sig,
318 tx_busy => tx_busy_1_sig,
319 tx_start => tx_start_1_sig
320 );
321
322 Inst_FTM_fTU_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2
323 port map(
324 clk => clk_50MHz,
325 -- RS485
326 rx_d => rx_d_2,
327 rx_en => rx_en_2_sig,
328 tx_d => tx_d_2,
329 tx_en => tx_en_2_sig,
330 -- FPGA
331 rx_data => rx_data_2_sig,
332 --rx_busy => ,
333 rx_valid => rx_valid_2_sig,
334 tx_data => tx_data_2_sig,
335 tx_busy => tx_busy_2_sig,
336 tx_start => tx_start_2_sig
337 );
338
339 Inst_FTM_fTU_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3
340 port map(
341 clk => clk_50MHz,
342 -- RS485
343 rx_d => rx_d_3,
344 rx_en => rx_en_3_sig,
345 tx_d => tx_d_3,
346 tx_en => tx_en_3_sig,
347 -- FPGA
348 rx_data => rx_data_3_sig,
349 --rx_busy => ,
350 rx_valid => rx_valid_3_sig,
351 tx_data => tx_data_3_sig,
352 tx_busy => tx_busy_3_sig,
353 tx_start => tx_start_3_sig
354 );
355
356 Inst_FTM_ftu_rs485_receiver : FTM_ftu_rs485_receiver
357 port map(
358 rec_clk => clk_50MHz,
359 rec_reset => rec_reset_sig,
360 --rx_busy =>,
361 rec_din => rec_data_sig,
362 rec_den => rx_valid_sig,
363 rec_dout => rec_block_sig,
364 rec_valid => rec_valid_sig
365 );
366
367 Inst_FTM_ftu_rs485_interpreter : FTM_ftu_rs485_interpreter
368 port map(
369 clk => clk_50MHz,
370 data_block => rec_block_sig,
371 block_valid => rec_valid_sig,
372 crc => crc_sig,
373 FTU_brd_add => FTU_brd_add_sig,
374 FTU_command => FTU_command_sig,
375 reset_crc => reset_crc_from_interpreter_sig,
376 enable_crc => enable_crc_from_interpreter_sig,
377 FTU_answer_ok => FTU_answer_ok_sig,
378 FTU_dac_array => FTU_dac_array_sig,
379 FTU_enable_array => FTU_enable_array_sig,
380 FTU_rate_array => FTU_rate_array_sig,
381 FTU_prescaling => FTU_prescaling_sig,
382 FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
383 FTU_dna => FTU_dna_sig
384 );
385
386 Inst_ucrc_par : ucrc_par
387 generic map(
388 POLYNOMIAL => CRC_POLYNOMIAL,
389 INIT_VALUE => CRC_INIT_VALUE,
390 DATA_WIDTH => (FTU_RS485_BLOCK_WIDTH - 8),
391 SYNC_RESET => 1
392 )
393 port map(
394 clk_i => clk_50MHz,
395 rst_i => reset_crc_sig,
396 clken_i => enable_crc_sig,
397 data_i => crc_data_sig,
398 match_o => open,
399 crc_o => crc_sig_inv
400 );
401
402 -- Main finite state machine to control all 40 FTUs
403 FTM_ftu_rs485_control_FSM: process (clk_50MHz)
404 begin
405 if Rising_edge(clk_50MHz) then
406 case FTM_ftu_rs485_control_State is
407
408 when INIT => -- reset CRC register
409 reset_crc_from_FSM_sig <= '1';
410 FTM_ftu_rs485_control_State <= IDLE;
411
412 when IDLE => -- wait for command from outside
413 sel_crate_sig <= "111";
414 sel_crc_input_source_sig <= '0';
415 reset_crc_from_FSM_sig <= '0';
416 enable_crc_from_FSM_sig <= '0';
417 new_config_done <= '0';
418 ping_all_done <= '0';
419 read_rates_done <= '0';
420 if (new_config = '1') then
421 new_config_started <= '1';
422 ping_all_started <= '0';
423 read_rates_started <= '0';
424 FTM_ftu_rs485_control_State <= ACTIVE_LIST;
425 elsif (new_config = '0' and ping_all = '1') then
426 new_config_started <= '0';
427 ping_all_started <= '1';
428 read_rates_started <= '0';
429 FTM_ftu_rs485_control_State <= PING;
430 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then
431 new_config_started <= '0';
432 ping_all_started <= '0';
433 read_rates_started <= '1';
434 FTM_ftu_rs485_control_State <= RATES;
435 else
436 new_config_started <= '0';
437 ping_all_started <= '0';
438 read_rates_started <= '0';
439 FTM_ftu_rs485_control_State <= IDLE;
440 end if;
441
442 when ACTIVE_LIST => -- copy active FTU list from inputs to array
443 active_FTU_array_sig(0) <= ftu_active_cr0;
444 active_FTU_array_sig(1) <= ftu_active_cr1;
445 active_FTU_array_sig(2) <= ftu_active_cr2;
446 active_FTU_array_sig(3) <= ftu_active_cr3;
447 FTM_ftu_rs485_control_State <= READ_CONFIG;
448
449-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list
450-- if (active_FTU_list_cnt < NO_OF_CRATES) then
451-- active_FTU_list_cnt <= active_FTU_list_cnt + 1;
452-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1;
453-- else
454-- active_FTU_list_cnt <= 0;
455-- FTM_ftu_rs485_control_State <= READ_CONFIG;
456-- end if;
457
458-- when ACTIVE_LIST_1 =>
459-- if (static_RAM_busy = '0') then
460-- read_static_RAM <= '1';
461-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH);
462-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2;
463-- end if;
464
465-- when ACTIVE_LIST_2 =>
466-- if (static_RAM_started = '1') then
467-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;
468-- end if;
469
470-- when ACTIVE_LIST_3 =>
471-- if (static_RAM_ready = '1') then
472-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;
473-- read_static_RAM <= '0';
474-- FTM_ftu_rs485_control_State <= ACTIVE_LIST;
475-- end if;
476
477 when READ_CONFIG => -- read configuration of FTUs (one by one)
478 if (crate_cnt < NO_OF_CRATES) then
479 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
480 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
481 if (FTU_register_cnt < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1)) then
482 FTU_register_cnt <= FTU_register_cnt + 1;
483 FTM_ftu_rs485_control_State <= READ_CONFIG_1;
484 else
485 FTU_cnt <= FTU_cnt + 1;
486 FTU_register_cnt <= 0;
487 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
488 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
489 else
490 FTM_ftu_rs485_control_State <= READ_CONFIG;
491 end if;
492 end if;
493 else
494 crate_cnt <= crate_cnt + 1;
495 FTU_cnt <= 0;
496 FTM_ftu_rs485_control_State <= READ_CONFIG;
497 end if;
498 else
499 crate_cnt <= 0;
500 new_config_started <= '0';
501 new_config_done <= '1';
502 sel_crate_sig <= "111";
503 FTM_ftu_rs485_control_State <= IDLE;
504 end if;
505
506 when READ_CONFIG_1 =>
507 if (static_RAM_busy = '0') then
508 read_static_RAM <= '1';
509 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
510 crate_cnt * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
511 FTU_cnt * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
512 (FTU_register_cnt - 1), STATIC_RAM_ADDR_WIDTH);
513 FTM_ftu_rs485_control_State <= READ_CONFIG_2;
514 end if;
515
516 when READ_CONFIG_2 =>
517 if (static_RAM_started = '1') then
518 FTM_ftu_rs485_control_State <= READ_CONFIG_3;
519 end if;
520
521 when READ_CONFIG_3 =>
522 if (static_RAM_ready = '1') then
523 if ((FTU_register_cnt - 1) < NO_OF_FTU_ENABLE_REG) then
524 FTU_enable_array_RAM_sig(FTU_register_cnt - 1) <= data_static_RAM;
525 elsif ((FTU_register_cnt - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
526 FTU_dac_array_RAM_sig((FTU_register_cnt - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
527 elsif ((FTU_register_cnt - 1) = (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
528 FTU_prescaling_RAM_sig <= data_static_RAM;
529 end if;
530 read_static_RAM <= '0';
531 FTM_ftu_rs485_control_State <= READ_CONFIG;
532 end if;
533
534 when TRANSMIT_CONFIG => -- send configuration to FTUs (one by one)
535 rec_reset_sig <= '0';
536 if (FTU_command_cnt = 0) then -- DACs
537 FTU_command_cnt <= FTU_command_cnt + 1;
538 enable_crc_from_FSM_sig <= '1';
539 crc_data_from_FSM_sig <= "00000000"
540 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
541 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
542 & "00000000"
543 & FTU_dac_array_RAM_sig(4)(15 downto 8) & FTU_dac_array_RAM_sig(4)(7 downto 0)
544 & FTU_dac_array_RAM_sig(3)(15 downto 8) & FTU_dac_array_RAM_sig(3)(7 downto 0)
545 & FTU_dac_array_RAM_sig(2)(15 downto 8) & FTU_dac_array_RAM_sig(2)(7 downto 0)
546 & FTU_dac_array_RAM_sig(1)(15 downto 8) & FTU_dac_array_RAM_sig(1)(7 downto 0)
547 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0)
548 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
549 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
550 & FTU_RS485_START_DELIM;
551 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
552 FTU_command_sig <= "00000000";
553 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
554 elsif (FTU_command_cnt = 1) then -- enables
555 FTU_command_cnt <= FTU_command_cnt + 1;
556 enable_crc_from_FSM_sig <= '1';
557 crc_data_from_FSM_sig <= "00000000"
558 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
559 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
560 & "00000000" & "00000000" & "00000000"
561 & FTU_enable_array_RAM_sig(3)(15 downto 8) & FTU_enable_array_RAM_sig(3)(7 downto 0)
562 & FTU_enable_array_RAM_sig(2)(15 downto 8) & FTU_enable_array_RAM_sig(2)(7 downto 0)
563 & FTU_enable_array_RAM_sig(1)(15 downto 8) & FTU_enable_array_RAM_sig(1)(7 downto 0)
564 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0)
565 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
566 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
567 & FTU_RS485_START_DELIM;
568 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
569 FTU_command_sig <= "00000011";
570 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
571 elsif (FTU_command_cnt = 2) then -- prescaling
572 FTU_command_cnt <= FTU_command_cnt + 1;
573 enable_crc_from_FSM_sig <= '1';
574 crc_data_from_FSM_sig <= "00000000"
575 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
576 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
577 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
578 & "00000000" & "00000000" & "00000000" & "00000000"
579 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0)
580 & "00000110" & FIRMWARE_ID & FTM_ADDRESS
581 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
582 & FTU_RS485_START_DELIM;
583 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
584 FTU_command_sig <= "00000110";
585 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
586 else
587 FTU_command_cnt <= 0;
588 enable_crc_from_FSM_sig <= '0';
589 FTM_ftu_rs485_control_State <= READ_CONFIG;
590 end if;
591
592 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation
593 enable_crc_from_FSM_sig <= '0';
594 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
595
596 when TRANSMIT_CONFIG_2 => -- transmit byte by byte
597 if (tx_busy_sig = '0') then
598 if (frame_cnt < 27) then
599 frame_cnt <= frame_cnt + 1;
600 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
601 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
602 tx_start_sig <= '1';
603 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
604 elsif (frame_cnt = 27) then
605 frame_cnt <= frame_cnt + 1;
606 tx_data_sig <= crc_sig;
607 tx_start_sig <= '1';
608 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
609 else
610 frame_cnt <= 0;
611 reset_crc_from_FSM_sig <= '1';
612 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
613 end if;
614 else
615 tx_start_sig <= '0';
616 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
617 end if;
618
619 when TRANSMIT_CONFIG_3 => -- wait for FTU answer
620 reset_crc_from_FSM_sig <= '0';
621 if (FTU_answer_ok_sig = '1') then
622 timeout_cnt <= 0;
623 retry_cnt <= 0;
624 sel_crc_input_source_sig <= '0';
625 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
626 else
627 if (timeout_cnt < FTU_RS485_TIMEOUT) then
628 timeout_cnt <= timeout_cnt + 1;
629 sel_crc_input_source_sig <= '1';
630 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
631 else
632 timeout_cnt <= 0;
633 sel_crc_input_source_sig <= '0';
634 rec_reset_sig <= '1';
635 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
636 retry_cnt <= retry_cnt + 1;
637 FTU_command_cnt <= FTU_command_cnt - 1; -- try this command again
638 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
639 else
640 retry_cnt <= 0;
641 FTU_command_cnt <= FTU_command_cnt; -- move to next command;
642 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
643 end if;
644 end if;
645 end if;
646
647 when PING => -- ping all FTUs
648 rec_reset_sig <= '0';
649 if (crate_cnt < NO_OF_CRATES) then
650 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
651 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
652 FTU_cnt <= FTU_cnt + 1;
653 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
654 enable_crc_from_FSM_sig <= '1';
655 crc_data_from_FSM_sig <= "00000000"
656 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
657 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
658 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
659 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
660 & "00000101" & FIRMWARE_ID & FTM_ADDRESS
661 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
662 & FTU_RS485_START_DELIM;
663 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
664 FTU_command_sig <= "00000101";
665 FTM_ftu_rs485_control_State <= PING_1;
666 else
667 FTM_ftu_rs485_control_State <= PING;
668 end if;
669 else
670 crate_cnt <= crate_cnt + 1;
671 FTU_cnt <= 0;
672 FTM_ftu_rs485_control_State <= PING;
673 end if;
674 else
675 crate_cnt <= 0;
676 FTM_ftu_rs485_control_State <= PING_END;
677 end if;
678
679 when PING_1 => -- wait one cycle for CRC calculation
680 enable_crc_from_FSM_sig <= '0';
681 FTM_ftu_rs485_control_State <= PING_2;
682
683 when PING_2 => -- transmit byte by byte
684 if (tx_busy_sig = '0') then
685 if (frame_cnt < 27) then
686 frame_cnt <= frame_cnt + 1;
687 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
688 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
689 tx_start_sig <= '1';
690 FTM_ftu_rs485_control_State <= PING_2;
691 elsif (frame_cnt = 27) then
692 frame_cnt <= frame_cnt + 1;
693 tx_data_sig <= crc_sig;
694 tx_start_sig <= '1';
695 FTM_ftu_rs485_control_State <= PING_2;
696 else
697 frame_cnt <= 0;
698 reset_crc_from_FSM_sig <= '1';
699 FTM_ftu_rs485_control_State <= PING_3;
700 end if;
701 else
702 tx_start_sig <= '0';
703 FTM_ftu_rs485_control_State <= PING_2;
704 end if;
705
706 when PING_3 => -- wait for FTU answer
707 reset_crc_from_FSM_sig <= '0';
708 if (FTU_answer_ok_sig = '1') then
709 FTU_answer_array_sig(crate_cnt) <= FTU_answer_array_sig(crate_cnt) + 1;
710 no_of_FTU_answer_sig <= no_of_FTU_answer_sig + 1;
711 timeout_cnt <= 0;
712 sel_crc_input_source_sig <= '0';
713 FTM_ftu_rs485_control_State <= FTU_LIST;
714 else
715 if (timeout_cnt < FTU_RS485_TIMEOUT) then
716 timeout_cnt <= timeout_cnt + 1;
717 sel_crc_input_source_sig <= '1';
718 FTM_ftu_rs485_control_State <= PING_3;
719 else
720 timeout_cnt <= 0;
721 sel_crc_input_source_sig <= '0';
722 rec_reset_sig <= '1';
723 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
724 retry_cnt <= retry_cnt + 1;
725 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
726 FTM_ftu_rs485_control_State <= PING;
727 else
728 FTU_cnt <= FTU_cnt; -- move on
729 FTM_ftu_rs485_control_State <= FTU_LIST;
730 end if;
731 end if;
732 end if;
733
734 when FTU_LIST => -- fill FTU-list for actual FTU
735 rec_reset_sig <= '0';
736 if (FTU_list_reg_cnt < NO_OF_FTU_LIST_REG) then
737 FTU_list_reg_cnt <= FTU_list_reg_cnt + 1;
738 FTM_ftu_rs485_control_State <= FTU_LIST_1;
739 else
740 FTU_list_reg_cnt <= 0;
741 retry_cnt <= 0;
742 FTM_ftu_rs485_control_State <= PING;
743 end if;
744
745 when FTU_LIST_1 =>
746 if (FTUlist_RAM_busy = '0') then
747 write_FTUlist_RAM <= '1';
748 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
749 (FTU_cnt - 1)* NO_OF_FTU_LIST_REG +
750 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
751 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
752 if ((FTU_list_reg_cnt - 1) = 0) then
753 data_FTUlist_RAM <= "000000" & conv_std_logic_vector((retry_cnt + 1),2) & "00" & FTU_brd_add_sig;
754 elsif ((FTU_list_reg_cnt - 1) = 1) then
755 data_FTUlist_RAM <= FTU_dna_sig(63 downto 48);
756 elsif ((FTU_list_reg_cnt - 1) = 2) then
757 data_FTUlist_RAM <= FTU_dna_sig(47 downto 32);
758 elsif ((FTU_list_reg_cnt - 1) = 3) then
759 data_FTUlist_RAM <= FTU_dna_sig(31 downto 16);
760 elsif ((FTU_list_reg_cnt - 1) = 4) then
761 data_FTUlist_RAM <= FTU_dna_sig(15 downto 0);
762 elsif ((FTU_list_reg_cnt - 1) = 5) then
763 data_FTUlist_RAM <= "00000000" & FTU_crc_error_cnt_sig;
764 end if;
765 else
766 data_FTUlist_RAM <= (others => '0');
767 end if;
768 FTM_ftu_rs485_control_State <= FTU_LIST_2;
769 end if;
770
771 when FTU_LIST_2 =>
772 if (FTUlist_RAM_started = '1') then
773 write_FTUlist_RAM <= '0';
774 FTM_ftu_rs485_control_State <= FTU_LIST_3;
775 end if;
776
777 when FTU_LIST_3 =>
778 if (FTUlist_RAM_ready = '1') then
779 FTM_ftu_rs485_control_State <= FTU_LIST;
780 end if;
781
782 when PING_END => -- add final ping statistics to FTU-list
783 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then
784 FTU_list_header_cnt <= FTU_list_header_cnt + 1;
785 FTM_ftu_rs485_control_State <= PING_END_1;
786 else
787 FTU_list_header_cnt <= 0;
788 ping_all_started <= '0';
789 ping_all_done <= '1';
790 sel_crate_sig <= "111";
791 FTM_ftu_rs485_control_State <= IDLE;
792 end if;
793
794 when PING_END_1 =>
795 if (FTUlist_RAM_busy = '0') then
796 write_FTUlist_RAM <= '1';
797 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
798 if ((FTU_list_header_cnt - 1) = 0) then
799 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16);
800 elsif ((FTU_list_header_cnt - 1) < 5) then
801 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16);
802 elsif ((FTU_list_header_cnt - 1) < 9) then
803 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6);
804 end if;
805 FTM_ftu_rs485_control_State <= PING_END_2;
806 end if;
807
808 when PING_END_2 =>
809 if (FTUlist_RAM_started = '1') then
810 write_FTUlist_RAM <= '0';
811 FTM_ftu_rs485_control_State <= PING_END_3;
812 end if;
813
814 when PING_END_3 =>
815 if (FTUlist_RAM_ready = '1') then
816 FTM_ftu_rs485_control_State <= PING_END;
817 end if;
818
819 when RATES => -- read all FTU rates
820 FTM_ftu_rs485_control_State <= IDLE;
821
822 end case;
823 end if;
824 end process FTM_ftu_rs485_control_FSM;
825
826 -- Process to multiplex the different crate buses
827 sel_crate_process: process (sel_crate_sig,
828 rx_en_0_sig, rx_en_1_sig, rx_en_2_sig, rx_en_3_sig,
829 tx_en_0_sig, tx_en_1_sig, tx_en_2_sig, tx_en_3_sig,
830 rx_valid_0_sig, rx_valid_1_sig, rx_valid_2_sig, rx_valid_3_sig,
831 rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
832 tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
833 tx_start_sig, tx_data_sig)
834 begin
835 case sel_crate_sig is
836 when "000" => -- crate 0
837 rx_en_sig <= rx_en_0_sig;
838 tx_en_sig <= tx_en_0_sig;
839 rx_valid_sig <= rx_valid_0_sig;
840 rec_data_sig <= rx_data_0_sig;
841 tx_busy_sig <= tx_busy_0_sig;
842 tx_start_0_sig <= tx_start_sig;
843 tx_start_1_sig <= '0';
844 tx_start_2_sig <= '0';
845 tx_start_3_sig <= '0';
846 tx_data_0_sig <= tx_data_sig;
847 tx_data_1_sig <= (others => '0');
848 tx_data_2_sig <= (others => '0');
849 tx_data_3_sig <= (others => '0');
850 when "001" => -- crate 1
851 rx_en_sig <= rx_en_1_sig;
852 tx_en_sig <= tx_en_1_sig;
853 rx_valid_sig <= rx_valid_1_sig;
854 rec_data_sig <= rx_data_1_sig;
855 tx_busy_sig <= tx_busy_1_sig;
856 tx_start_0_sig <= '0';
857 tx_start_1_sig <= tx_start_sig;
858 tx_start_2_sig <= '0';
859 tx_start_3_sig <= '0';
860 tx_data_0_sig <= (others => '0');
861 tx_data_1_sig <= tx_data_sig;
862 tx_data_2_sig <= (others => '0');
863 tx_data_3_sig <= (others => '0');
864 when "010" => -- crate 2
865 rx_en_sig <= rx_en_2_sig;
866 tx_en_sig <= tx_en_2_sig;
867 rx_valid_sig <= rx_valid_2_sig;
868 rec_data_sig <= rx_data_2_sig;
869 tx_busy_sig <= tx_busy_2_sig;
870 tx_start_0_sig <= '0';
871 tx_start_1_sig <= '0';
872 tx_start_2_sig <= tx_start_sig;
873 tx_start_3_sig <= '0';
874 tx_data_0_sig <= (others => '0');
875 tx_data_1_sig <= (others => '0');
876 tx_data_2_sig <= tx_data_sig;
877 tx_data_3_sig <= (others => '0');
878 when "011" => -- crate 3
879 rx_en_sig <= rx_en_3_sig;
880 tx_en_sig <= tx_en_3_sig;
881 rx_valid_sig <= rx_valid_3_sig;
882 rec_data_sig <= rx_data_3_sig;
883 tx_busy_sig <= tx_busy_3_sig;
884 tx_start_0_sig <= '0';
885 tx_start_1_sig <= '0';
886 tx_start_2_sig <= '0';
887 tx_start_3_sig <= tx_start_sig;
888 tx_data_0_sig <= (others => '0');
889 tx_data_1_sig <= (others => '0');
890 tx_data_2_sig <= (others => '0');
891 tx_data_3_sig <= tx_data_sig;
892 when others => -- no crate specified
893 rx_en_sig <= '0';
894 tx_en_sig <= '0';
895 rx_valid_sig <= '0';
896 rec_data_sig <= (others => '0');
897 tx_busy_sig <= '0';
898 tx_start_0_sig <= '0';
899 tx_start_1_sig <= '0';
900 tx_start_2_sig <= '0';
901 tx_start_3_sig <= '0';
902 tx_data_0_sig <= (others => '0');
903 tx_data_1_sig <= (others => '0');
904 tx_data_2_sig <= (others => '0');
905 tx_data_3_sig <= (others => '0');
906 end case;
907 end process;
908
909 -- Process to select the CRC input source (FSM or interpreter)
910 sel_crc_cource_process : process (sel_crc_input_source_sig,
911 reset_crc_from_interpreter_sig, reset_crc_from_FSM_sig,
912 enable_crc_from_interpreter_sig, enable_crc_from_FSM_sig,
913 rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0), crc_data_from_FSM_sig)
914 begin
915 case sel_crc_input_source_sig is
916 when '0' => -- FSM
917 reset_crc_sig <= reset_crc_from_FSM_sig;
918 enable_crc_sig <= enable_crc_from_FSM_sig;
919 crc_data_sig <= crc_data_from_FSM_sig;
920 when '1' => -- interpreter
921 reset_crc_sig <= reset_crc_from_interpreter_sig;
922 enable_crc_sig <= enable_crc_from_interpreter_sig;
923 crc_data_sig <= rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0);
924 when others => -- signal undefined
925 reset_crc_sig <= reset_crc_from_FSM_sig;
926 enable_crc_sig <= enable_crc_from_FSM_sig;
927 crc_data_sig <= crc_data_from_FSM_sig;
928 end case;
929 end process;
930
931 rx_en <= rx_en_sig;
932 tx_en <= tx_en_sig;
933
934 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
935
936end Behavioral;
937
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