source: firmware/FTM/ftu_control/FTM_ftu_control.vhd@ 10282

Last change on this file since 10282 was 10256, checked in by weitzel, 15 years ago
new version of FTM ethernet module; first version of clock conditioner
File size: 45.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 17:54:04 02/02/2011
6-- Design Name:
7-- Module Name: FTM_ftu_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Communication of FTM with the 40 FTU boards of the FACT camera
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_ftu_control is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus enables for FTU crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- FTU crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- FTU crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- FTU crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- FTU crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- commands from FTM main control
59 new_config : in std_logic;
60 ping_all : in std_logic;
61 read_rates : in std_logic;
62
63 -- answers to FTM main control
64 read_rates_started : out std_logic := '0';
65 read_rates_done : out std_logic := '0';
66 new_config_started : out std_logic := '0';
67 new_config_done : out std_logic := '0';
68 ping_all_started : out std_logic := '0';
69 ping_all_done : out std_logic := '0';
70
71 -- active FTU lists
72 ftu_active_cr0 : in std_logic_vector (15 downto 0);
73 ftu_active_cr1 : in std_logic_vector (15 downto 0);
74 ftu_active_cr2 : in std_logic_vector (15 downto 0);
75 ftu_active_cr3 : in std_logic_vector (15 downto 0);
76
77 -- communication with static (config) RAM
78 -- this RAM is only read by FTU_control
79 static_RAM_busy : in std_logic;
80 static_RAM_started : in std_logic;
81 static_RAM_ready : in std_logic;
82 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
83 read_static_RAM : out std_logic := '0';
84 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
85
86 -- communication with dynamic RAM (e.g. rates)
87 -- this RAM is only written by FTU_control
88 dynamic_RAM_busy : in std_logic;
89 dynamic_RAM_started : in std_logic;
90 dynamic_RAM_ready : in std_logic;
91 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
92 write_dynamic_RAM : out std_logic := '0';
93 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
94
95 -- communication with FTU-list RAM
96 -- this RAM is only written by FTU_control
97 FTUlist_RAM_busy : in std_logic;
98 FTUlist_RAM_started : in std_logic;
99 FTUlist_RAM_ready : in std_logic;
100 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
101 write_FTUlist_RAM : out std_logic := '0';
102 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
103
104 );
105end FTM_ftu_control;
106
107architecture Behavioral of FTM_ftu_control is
108
109 -- list of active FTUs, read out from static RAM before starting to contact FTUs
110 signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
111 --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0'));
112
113 -- signals to count the number of responding FTUs (per crate and total) in case of a ping
114 signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
115 signal no_of_FTU_answer_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE) := 0;
116
117 -- FTU configuration data, read out from static RAM (board by board)
118 signal FTU_dac_array_RAM_sig : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
119 signal FTU_enable_array_RAM_sig : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
120 signal FTU_prescaling_RAM_sig : std_logic_vector(15 downto 0) := (others => '0');
121
122 -- signals for receiver of FTU communication
123 signal rec_reset_sig : std_logic := '0'; -- reset
124 signal rec_data_sig : std_logic_vector (7 DOWNTO 0);
125 signal rec_block_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTM_ftu_rs485_receiver
126 signal rec_valid_sig : std_logic; -- initialized in FTM_ftu_rs485_receiver
127
128 -- select signal to multiplex the different crates
129 signal sel_crate_sig : STD_LOGIC_VECTOR (2 downto 0) := "111";
130
131 -- global signals after multiplexer
132 signal rx_en_sig : std_logic := '0';
133 signal tx_en_sig : std_logic := '0';
134 signal rx_valid_sig : std_logic := '0';
135 signal tx_busy_sig : std_logic := '0';
136 signal tx_start_sig : std_logic := '0';
137 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
138 signal rx_busy_sig : std_logic := '0';
139 signal start_int_sig : std_logic := '0';
140
141 -- signals for interpreter of FTU communication
142 signal FTU_brd_add_sig : std_logic_vector (5 DOWNTO 0) := (others => '0');
143 signal FTU_command_sig : std_logic_vector (7 DOWNTO 0) := (others => '1');
144 signal FTU_answer_ok_sig : std_logic; -- initialized in interpreter
145 signal FTU_dac_array_sig : FTU_dac_array_type; -- initialized in interpreter
146 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter
147 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter
148 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
149 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
150 signal FTU_dna_sig : std_logic_vector(63 downto 0); -- initialized in interpreter
151
152 -- rx_enable and tx_enable lines from different FTM_ftu_rs485_interface
153 -- initialized in corresponding interface
154 signal rx_en_0_sig : STD_LOGIC;
155 signal tx_en_0_sig : STD_LOGIC;
156 signal rx_en_1_sig : STD_LOGIC;
157 signal tx_en_1_sig : STD_LOGIC;
158 signal rx_en_2_sig : STD_LOGIC;
159 signal tx_en_2_sig : STD_LOGIC;
160 signal rx_en_3_sig : STD_LOGIC;
161 signal tx_en_3_sig : STD_LOGIC;
162
163 signal tx_start_0_sig : std_logic := '0';
164 signal tx_data_0_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
165 signal tx_busy_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
166 signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
167 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0
168 signal rx_busy_0_sig : std_logic; -- initialized in FTU_rs485_interface_0
169
170 signal tx_start_1_sig : std_logic := '0';
171 signal tx_data_1_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
172 signal tx_busy_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
173 signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
174 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1
175 signal rx_busy_1_sig : std_logic; -- initialized in FTU_rs485_interface_1
176
177 signal tx_start_2_sig : std_logic := '0';
178 signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
179 signal tx_busy_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
180 signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
181 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2
182 signal rx_busy_2_sig : std_logic; -- initialized in FTU_rs485_interface_2
183
184 signal tx_start_3_sig : std_logic := '0';
185 signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
186 signal tx_busy_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
187 signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
188 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3
189 signal rx_busy_3_sig : std_logic; -- initialized in FTU_rs485_interface_3
190
191 -- signals to control and read out CRC
192 signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter
193 signal reset_crc_sig : std_logic;
194 signal enable_crc_sig : std_logic;
195 signal crc_data_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
196 signal reset_crc_from_FSM_sig : std_logic := '0';
197 signal reset_crc_from_interpreter_sig : std_logic;
198 signal enable_crc_from_FSM_sig : std_logic := '0';
199 signal enable_crc_from_interpreter_sig : std_logic;
200 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
201 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
202 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
203
204 -- various loop counters
205 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;
206 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0;
207 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0;
208 signal FTU_register_cnt : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) := 0;
209 signal FTU_command_cnt : integer range 0 to 3 := 0;
210 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0;
211 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0;
212 signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0;
213
214 -- counter to define timeout and number of retries
215 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
216 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
217
218 component FTM_ftu_rs485_interface
219 port(
220 clk : IN std_logic;
221 -- RS485
222 rx_d : IN std_logic;
223 rx_en : OUT std_logic;
224 tx_d : OUT std_logic;
225 tx_en : OUT std_logic;
226 -- FPGA
227 rx_data : OUT std_logic_vector (7 DOWNTO 0);
228 rx_busy : OUT std_logic := '0';
229 rx_valid : OUT std_logic := '0';
230 tx_data : IN std_logic_vector (7 DOWNTO 0);
231 tx_busy : OUT std_logic := '0';
232 tx_start : IN std_logic
233 );
234 end component;
235
236 component FTM_ftu_rs485_receiver
237 port(
238 rec_clk : in std_logic;
239 rec_reset : in std_logic;
240 --rx_busy : in std_logic;
241 rec_din : in std_logic_vector(7 downto 0);
242 rec_den : in std_logic;
243 rec_dout : out std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
244 rec_valid : out std_logic := '0'
245 );
246 end component;
247
248 component FTM_ftu_rs485_interpreter
249 port(
250 clk : IN std_logic;
251 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0);
252 block_valid : IN std_logic;
253 crc : IN std_logic_vector(7 downto 0);
254 FTU_brd_add : IN std_logic_vector(5 downto 0);
255 FTU_command : IN std_logic_vector(7 downto 0);
256 reset_crc : OUT std_logic := '0';
257 enable_crc : OUT std_logic := '0';
258 FTU_answer_ok : OUT std_logic := '0';
259 FTU_dac_array : OUT FTU_dac_array_type;
260 FTU_enable_array : OUT FTU_enable_array_type;
261 FTU_rate_array : OUT FTU_rate_array_type;
262 FTU_prescaling : OUT std_logic_vector(7 downto 0);
263 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
264 FTU_dna : OUT std_logic_vector(63 downto 0)
265 );
266 end component;
267
268 component ucrc_par
269 generic(
270 POLYNOMIAL : std_logic_vector;
271 INIT_VALUE : std_logic_vector;
272 DATA_WIDTH : integer range 2 to 256;
273 SYNC_RESET : integer range 0 to 1
274 );
275 port(
276 clk_i : in std_logic;
277 rst_i : in std_logic;
278 clken_i : in std_logic;
279 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
280 match_o : out std_logic;
281 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
282 );
283 end component;
284
285 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
286 PING, PING_END, FTU_LIST,
287 RATES, RATES_1, RATES_2, RATES_3,
288 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
289 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
290 PING_1, PING_2, PING_3, PING_END_1, PING_END_2, PING_END_3,
291 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3);
292 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
293
294begin
295
296 Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0
297 port map(
298 clk => clk_50MHz,
299 -- RS485
300 rx_d => rx_d_0,
301 rx_en => rx_en_0_sig,
302 tx_d => tx_d_0,
303 tx_en => tx_en_0_sig,
304 -- FPGA
305 rx_data => rx_data_0_sig,
306 rx_busy => rx_busy_0_sig,
307 rx_valid => rx_valid_0_sig,
308 tx_data => tx_data_0_sig,
309 tx_busy => tx_busy_0_sig,
310 tx_start => tx_start_0_sig
311 );
312
313 Inst_FTM_fTU_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1
314 port map(
315 clk => clk_50MHz,
316 -- RS485
317 rx_d => rx_d_1,
318 rx_en => rx_en_1_sig,
319 tx_d => tx_d_1,
320 tx_en => tx_en_1_sig,
321 -- FPGA
322 rx_data => rx_data_1_sig,
323 rx_busy => rx_busy_1_sig,
324 rx_valid => rx_valid_1_sig,
325 tx_data => tx_data_1_sig,
326 tx_busy => tx_busy_1_sig,
327 tx_start => tx_start_1_sig
328 );
329
330 Inst_FTM_fTU_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2
331 port map(
332 clk => clk_50MHz,
333 -- RS485
334 rx_d => rx_d_2,
335 rx_en => rx_en_2_sig,
336 tx_d => tx_d_2,
337 tx_en => tx_en_2_sig,
338 -- FPGA
339 rx_data => rx_data_2_sig,
340 rx_busy => rx_busy_2_sig,
341 rx_valid => rx_valid_2_sig,
342 tx_data => tx_data_2_sig,
343 tx_busy => tx_busy_2_sig,
344 tx_start => tx_start_2_sig
345 );
346
347 Inst_FTM_fTU_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3
348 port map(
349 clk => clk_50MHz,
350 -- RS485
351 rx_d => rx_d_3,
352 rx_en => rx_en_3_sig,
353 tx_d => tx_d_3,
354 tx_en => tx_en_3_sig,
355 -- FPGA
356 rx_data => rx_data_3_sig,
357 rx_busy => rx_busy_3_sig,
358 rx_valid => rx_valid_3_sig,
359 tx_data => tx_data_3_sig,
360 tx_busy => tx_busy_3_sig,
361 tx_start => tx_start_3_sig
362 );
363
364 Inst_FTM_ftu_rs485_receiver : FTM_ftu_rs485_receiver
365 port map(
366 rec_clk => clk_50MHz,
367 rec_reset => rec_reset_sig,
368 --rx_busy =>,
369 rec_din => rec_data_sig,
370 rec_den => rx_valid_sig,
371 rec_dout => rec_block_sig,
372 rec_valid => rec_valid_sig
373 );
374
375 Inst_FTM_ftu_rs485_interpreter : FTM_ftu_rs485_interpreter
376 port map(
377 clk => clk_50MHz,
378 data_block => rec_block_sig,
379 block_valid => start_int_sig,
380 crc => crc_sig,
381 FTU_brd_add => FTU_brd_add_sig,
382 FTU_command => FTU_command_sig,
383 reset_crc => reset_crc_from_interpreter_sig,
384 enable_crc => enable_crc_from_interpreter_sig,
385 FTU_answer_ok => FTU_answer_ok_sig,
386 FTU_dac_array => FTU_dac_array_sig,
387 FTU_enable_array => FTU_enable_array_sig,
388 FTU_rate_array => FTU_rate_array_sig,
389 FTU_prescaling => FTU_prescaling_sig,
390 FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
391 FTU_dna => FTU_dna_sig
392 );
393
394 Inst_ucrc_par : ucrc_par
395 generic map(
396 POLYNOMIAL => CRC_POLYNOMIAL,
397 INIT_VALUE => CRC_INIT_VALUE,
398 DATA_WIDTH => (FTU_RS485_BLOCK_WIDTH - 8),
399 SYNC_RESET => 1
400 )
401 port map(
402 clk_i => clk_50MHz,
403 rst_i => reset_crc_sig,
404 clken_i => enable_crc_sig,
405 data_i => crc_data_sig,
406 match_o => open,
407 crc_o => crc_sig_inv
408 );
409
410 -- Main finite state machine to control all 40 FTUs
411 FTM_ftu_rs485_control_FSM: process (clk_50MHz)
412 begin
413 if Rising_edge(clk_50MHz) then
414 case FTM_ftu_rs485_control_State is
415
416 when INIT => -- reset CRC register
417 reset_crc_from_FSM_sig <= '1';
418 FTM_ftu_rs485_control_State <= IDLE;
419
420 when IDLE => -- wait for command from outside
421 sel_crate_sig <= "111";
422 sel_crc_input_source_sig <= '0';
423 reset_crc_from_FSM_sig <= '0';
424 enable_crc_from_FSM_sig <= '0';
425 new_config_done <= '0';
426 ping_all_done <= '0';
427 read_rates_done <= '0';
428 if (new_config = '1') then
429 new_config_started <= '1';
430 ping_all_started <= '0';
431 read_rates_started <= '0';
432 FTM_ftu_rs485_control_State <= ACTIVE_LIST;
433 elsif (new_config = '0' and ping_all = '1') then
434 new_config_started <= '0';
435 ping_all_started <= '1';
436 read_rates_started <= '0';
437 rec_reset_sig <= '1';
438 FTM_ftu_rs485_control_State <= PING;
439 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then
440 new_config_started <= '0';
441 ping_all_started <= '0';
442 read_rates_started <= '1';
443 FTM_ftu_rs485_control_State <= RATES;
444 else
445 new_config_started <= '0';
446 ping_all_started <= '0';
447 read_rates_started <= '0';
448 FTM_ftu_rs485_control_State <= IDLE;
449 end if;
450
451 when ACTIVE_LIST => -- copy active FTU list from inputs to array
452 active_FTU_array_sig(0) <= ftu_active_cr0;
453 active_FTU_array_sig(1) <= ftu_active_cr1;
454 active_FTU_array_sig(2) <= ftu_active_cr2;
455 active_FTU_array_sig(3) <= ftu_active_cr3;
456 FTM_ftu_rs485_control_State <= READ_CONFIG;
457
458-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list
459-- if (active_FTU_list_cnt < NO_OF_CRATES) then
460-- active_FTU_list_cnt <= active_FTU_list_cnt + 1;
461-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1;
462-- else
463-- active_FTU_list_cnt <= 0;
464-- FTM_ftu_rs485_control_State <= READ_CONFIG;
465-- end if;
466
467-- when ACTIVE_LIST_1 =>
468-- if (static_RAM_busy = '0') then
469-- read_static_RAM <= '1';
470-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH);
471-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2;
472-- end if;
473
474-- when ACTIVE_LIST_2 =>
475-- if (static_RAM_started = '1') then
476-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;
477-- end if;
478
479-- when ACTIVE_LIST_3 =>
480-- if (static_RAM_ready = '1') then
481-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;
482-- read_static_RAM <= '0';
483-- FTM_ftu_rs485_control_State <= ACTIVE_LIST;
484-- end if;
485
486 when READ_CONFIG => -- read configuration of FTUs (one by one)
487 if (crate_cnt < NO_OF_CRATES) then
488 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
489 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
490 if (FTU_register_cnt < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1)) then
491 FTU_register_cnt <= FTU_register_cnt + 1;
492 FTM_ftu_rs485_control_State <= READ_CONFIG_1;
493 else
494 FTU_cnt <= FTU_cnt + 1;
495 FTU_register_cnt <= 0;
496 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
497 rec_reset_sig <= '1';
498 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
499 else
500 FTM_ftu_rs485_control_State <= READ_CONFIG;
501 end if;
502 end if;
503 else
504 crate_cnt <= crate_cnt + 1;
505 FTU_cnt <= 0;
506 FTM_ftu_rs485_control_State <= READ_CONFIG;
507 end if;
508 else
509 crate_cnt <= 0;
510 new_config_started <= '0';
511 new_config_done <= '1';
512 sel_crate_sig <= "111";
513 FTM_ftu_rs485_control_State <= IDLE;
514 end if;
515
516 when READ_CONFIG_1 =>
517 if (static_RAM_busy = '0') then
518 read_static_RAM <= '1';
519 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
520 crate_cnt * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
521 FTU_cnt * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
522 (FTU_register_cnt - 1), STATIC_RAM_ADDR_WIDTH);
523 FTM_ftu_rs485_control_State <= READ_CONFIG_2;
524 end if;
525
526 when READ_CONFIG_2 =>
527 if (static_RAM_started = '1') then
528 FTM_ftu_rs485_control_State <= READ_CONFIG_3;
529 end if;
530
531 when READ_CONFIG_3 =>
532 if (static_RAM_ready = '1') then
533 if ((FTU_register_cnt - 1) < NO_OF_FTU_ENABLE_REG) then
534 FTU_enable_array_RAM_sig(FTU_register_cnt - 1) <= data_static_RAM;
535 elsif ((FTU_register_cnt - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
536 FTU_dac_array_RAM_sig((FTU_register_cnt - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
537 elsif ((FTU_register_cnt - 1) = (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
538 FTU_prescaling_RAM_sig <= data_static_RAM;
539 end if;
540 read_static_RAM <= '0';
541 FTM_ftu_rs485_control_State <= READ_CONFIG;
542 end if;
543
544 when TRANSMIT_CONFIG => -- send configuration to FTUs (one by one)
545 rec_reset_sig <= '0';
546 if (FTU_command_cnt = 0) then -- DACs
547 FTU_command_cnt <= FTU_command_cnt + 1;
548 enable_crc_from_FSM_sig <= '1';
549 crc_data_from_FSM_sig <= "00000000"
550 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
551 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
552 & "00000000"
553 & FTU_dac_array_RAM_sig(4)(15 downto 8) & FTU_dac_array_RAM_sig(4)(7 downto 0)
554 & FTU_dac_array_RAM_sig(3)(15 downto 8) & FTU_dac_array_RAM_sig(3)(7 downto 0)
555 & FTU_dac_array_RAM_sig(2)(15 downto 8) & FTU_dac_array_RAM_sig(2)(7 downto 0)
556 & FTU_dac_array_RAM_sig(1)(15 downto 8) & FTU_dac_array_RAM_sig(1)(7 downto 0)
557 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0)
558 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
559 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
560 & FTU_RS485_START_DELIM;
561 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
562 FTU_command_sig <= "00000000";
563 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
564 elsif (FTU_command_cnt = 1) then -- enables
565 FTU_command_cnt <= FTU_command_cnt + 1;
566 enable_crc_from_FSM_sig <= '1';
567 crc_data_from_FSM_sig <= "00000000"
568 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
569 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
570 & "00000000" & "00000000" & "00000000"
571 & FTU_enable_array_RAM_sig(3)(15 downto 8) & FTU_enable_array_RAM_sig(3)(7 downto 0)
572 & FTU_enable_array_RAM_sig(2)(15 downto 8) & FTU_enable_array_RAM_sig(2)(7 downto 0)
573 & FTU_enable_array_RAM_sig(1)(15 downto 8) & FTU_enable_array_RAM_sig(1)(7 downto 0)
574 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0)
575 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
576 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
577 & FTU_RS485_START_DELIM;
578 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
579 FTU_command_sig <= "00000011";
580 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
581 elsif (FTU_command_cnt = 2) then -- prescaling
582 FTU_command_cnt <= FTU_command_cnt + 1;
583 enable_crc_from_FSM_sig <= '1';
584 crc_data_from_FSM_sig <= "00000000"
585 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
586 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
587 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
588 & "00000000" & "00000000" & "00000000" & "00000000"
589 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0)
590 & "00000110" & FIRMWARE_ID & FTM_ADDRESS
591 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
592 & FTU_RS485_START_DELIM;
593 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
594 FTU_command_sig <= "00000110";
595 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
596 else
597 FTU_command_cnt <= 0;
598 enable_crc_from_FSM_sig <= '0';
599 FTM_ftu_rs485_control_State <= READ_CONFIG;
600 end if;
601
602 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation
603 enable_crc_from_FSM_sig <= '0';
604 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
605
606 when TRANSMIT_CONFIG_2 => -- transmit byte by byte
607 if (tx_busy_sig = '0') then
608 if (frame_cnt < 27) then
609 frame_cnt <= frame_cnt + 1;
610 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
611 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
612 tx_start_sig <= '1';
613 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
614 elsif (frame_cnt = 27) then
615 frame_cnt <= frame_cnt + 1;
616 tx_data_sig <= crc_sig;
617 tx_start_sig <= '1';
618 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
619 else
620 frame_cnt <= 0;
621 reset_crc_from_FSM_sig <= '1';
622 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
623 end if;
624 else
625 tx_start_sig <= '0';
626 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
627 end if;
628
629 when TRANSMIT_CONFIG_3 => -- wait for FTU answer
630 reset_crc_from_FSM_sig <= '0';
631 if (FTU_answer_ok_sig = '1') then
632 timeout_cnt <= 0;
633 retry_cnt <= 0;
634 sel_crc_input_source_sig <= '0';
635 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
636 else
637 if (timeout_cnt < FTU_RS485_TIMEOUT) then
638 timeout_cnt <= timeout_cnt + 1;
639 sel_crc_input_source_sig <= '1';
640 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
641 else
642 timeout_cnt <= 0;
643 sel_crc_input_source_sig <= '0';
644 rec_reset_sig <= '1';
645 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
646 retry_cnt <= retry_cnt + 1;
647 FTU_command_cnt <= FTU_command_cnt - 1; -- try this command again
648 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
649 else
650 retry_cnt <= 0;
651 FTU_command_cnt <= FTU_command_cnt; -- move to next command;
652 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
653 end if;
654 end if;
655 end if;
656
657 when PING => -- ping all FTUs
658 rec_reset_sig <= '0';
659 if (crate_cnt < NO_OF_CRATES) then
660 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
661 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
662 FTU_cnt <= FTU_cnt + 1;
663 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
664 enable_crc_from_FSM_sig <= '1';
665 crc_data_from_FSM_sig <= "00000000"
666 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
667 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
668 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
669 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
670 & "00000101" & FIRMWARE_ID & FTM_ADDRESS
671 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
672 & FTU_RS485_START_DELIM;
673 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
674 FTU_command_sig <= "00000101";
675 FTM_ftu_rs485_control_State <= PING_1;
676 else
677 FTM_ftu_rs485_control_State <= PING;
678 end if;
679 else
680 crate_cnt <= crate_cnt + 1;
681 FTU_cnt <= 0;
682 FTM_ftu_rs485_control_State <= PING;
683 end if;
684 else
685 crate_cnt <= 0;
686 FTM_ftu_rs485_control_State <= PING_END;
687 end if;
688
689 when PING_1 => -- wait one cycle for CRC calculation
690 enable_crc_from_FSM_sig <= '0';
691 rec_reset_sig <= '1';
692 FTM_ftu_rs485_control_State <= PING_2;
693
694 when PING_2 => -- transmit byte by byte
695 rec_reset_sig <= '0';
696 if (tx_busy_sig = '0') then
697 if (frame_cnt < 27) then
698 frame_cnt <= frame_cnt + 1;
699 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
700 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
701 tx_start_sig <= '1';
702 FTM_ftu_rs485_control_State <= PING_2;
703 elsif (frame_cnt = 27) then
704 frame_cnt <= frame_cnt + 1;
705 tx_data_sig <= crc_sig;
706 tx_start_sig <= '1';
707 FTM_ftu_rs485_control_State <= PING_2;
708 else
709 frame_cnt <= 0;
710 reset_crc_from_FSM_sig <= '1';
711 FTM_ftu_rs485_control_State <= PING_3;
712 end if;
713 else
714 tx_start_sig <= '0';
715 FTM_ftu_rs485_control_State <= PING_2;
716 end if;
717
718 when PING_3 => -- wait for FTU answer
719 reset_crc_from_FSM_sig <= '0';
720 if (FTU_answer_ok_sig = '1') then
721 FTU_answer_array_sig(crate_cnt) <= FTU_answer_array_sig(crate_cnt) + 1;
722 no_of_FTU_answer_sig <= no_of_FTU_answer_sig + 1;
723 timeout_cnt <= 0;
724 sel_crc_input_source_sig <= '0';
725 FTM_ftu_rs485_control_State <= FTU_LIST;
726 else
727 if (timeout_cnt < FTU_RS485_TIMEOUT) then
728 timeout_cnt <= timeout_cnt + 1;
729 sel_crc_input_source_sig <= '1';
730 FTM_ftu_rs485_control_State <= PING_3;
731 else
732 timeout_cnt <= 0;
733 sel_crc_input_source_sig <= '0';
734 rec_reset_sig <= '1';
735 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
736 retry_cnt <= retry_cnt + 1;
737 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
738 FTM_ftu_rs485_control_State <= PING;
739 else
740 FTU_cnt <= FTU_cnt; -- move on
741 FTM_ftu_rs485_control_State <= FTU_LIST;
742 end if;
743 end if;
744 end if;
745
746 when FTU_LIST => -- fill FTU-list for actual FTU
747 rec_reset_sig <= '0';
748 if (FTU_list_reg_cnt < NO_OF_FTU_LIST_REG) then
749 FTU_list_reg_cnt <= FTU_list_reg_cnt + 1;
750 FTM_ftu_rs485_control_State <= FTU_LIST_1;
751 else
752 FTU_list_reg_cnt <= 0;
753 retry_cnt <= 0;
754 FTM_ftu_rs485_control_State <= PING;
755 end if;
756
757 when FTU_LIST_1 =>
758 if (FTUlist_RAM_busy = '0') then
759 write_FTUlist_RAM <= '1';
760 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
761 (FTU_cnt - 1)* NO_OF_FTU_LIST_REG +
762 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
763 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
764 if ((FTU_list_reg_cnt - 1) = 0) then
765 data_FTUlist_RAM <= "000000" & conv_std_logic_vector((retry_cnt + 1),2) & "00" & FTU_brd_add_sig;
766 elsif ((FTU_list_reg_cnt - 1) = 1) then
767 data_FTUlist_RAM <= FTU_dna_sig(63 downto 48);
768 elsif ((FTU_list_reg_cnt - 1) = 2) then
769 data_FTUlist_RAM <= FTU_dna_sig(47 downto 32);
770 elsif ((FTU_list_reg_cnt - 1) = 3) then
771 data_FTUlist_RAM <= FTU_dna_sig(31 downto 16);
772 elsif ((FTU_list_reg_cnt - 1) = 4) then
773 data_FTUlist_RAM <= FTU_dna_sig(15 downto 0);
774 elsif ((FTU_list_reg_cnt - 1) = 5) then
775 data_FTUlist_RAM <= "00000000" & FTU_crc_error_cnt_sig;
776 end if;
777 else
778 data_FTUlist_RAM <= (others => '0');
779 end if;
780 FTM_ftu_rs485_control_State <= FTU_LIST_2;
781 end if;
782
783 when FTU_LIST_2 =>
784 if (FTUlist_RAM_started = '1') then
785 write_FTUlist_RAM <= '0';
786 FTM_ftu_rs485_control_State <= FTU_LIST_3;
787 end if;
788
789 when FTU_LIST_3 =>
790 if (FTUlist_RAM_ready = '1') then
791 FTM_ftu_rs485_control_State <= FTU_LIST;
792 end if;
793
794 when PING_END => -- add final ping statistics to FTU-list
795 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then
796 FTU_list_header_cnt <= FTU_list_header_cnt + 1;
797 FTM_ftu_rs485_control_State <= PING_END_1;
798 else
799 FTU_list_header_cnt <= 0;
800 ping_all_started <= '0';
801 ping_all_done <= '1';
802 sel_crate_sig <= "111";
803 FTU_answer_array_sig(0) <= 0;
804 FTU_answer_array_sig(1) <= 0;
805 FTU_answer_array_sig(2) <= 0;
806 FTU_answer_array_sig(3) <= 0;
807 no_of_FTU_answer_sig <= 0;
808 FTM_ftu_rs485_control_State <= IDLE;
809 end if;
810
811 when PING_END_1 =>
812 if (FTUlist_RAM_busy = '0') then
813 write_FTUlist_RAM <= '1';
814 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
815 if ((FTU_list_header_cnt - 1) = 0) then
816 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16);
817 elsif ((FTU_list_header_cnt - 1) < 5) then
818 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16);
819 elsif ((FTU_list_header_cnt - 1) < 9) then
820 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6);
821 end if;
822 FTM_ftu_rs485_control_State <= PING_END_2;
823 end if;
824
825 when PING_END_2 =>
826 if (FTUlist_RAM_started = '1') then
827 write_FTUlist_RAM <= '0';
828 FTM_ftu_rs485_control_State <= PING_END_3;
829 end if;
830
831 when PING_END_3 =>
832 if (FTUlist_RAM_ready = '1') then
833 FTM_ftu_rs485_control_State <= PING_END;
834 end if;
835
836 when RATES => -- read all FTU rates
837 rec_reset_sig <= '0';
838 if (crate_cnt < NO_OF_CRATES) then
839 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
840 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
841 FTU_cnt <= FTU_cnt + 1;
842 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
843 enable_crc_from_FSM_sig <= '1';
844 crc_data_from_FSM_sig <= "00000000"
845 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
846 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
847 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
848 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
849 & "00000010" & FIRMWARE_ID & FTM_ADDRESS
850 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
851 & FTU_RS485_START_DELIM;
852 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
853 FTU_command_sig <= "00000010";
854 FTM_ftu_rs485_control_State <= RATES_1;
855 else
856 FTM_ftu_rs485_control_State <= RATES;
857 end if;
858 else
859 crate_cnt <= crate_cnt + 1;
860 FTU_cnt <= 0;
861 FTM_ftu_rs485_control_State <= RATES;
862 end if;
863 else
864 crate_cnt <= 0;
865 read_rates_started <= '0';
866 read_rates_done <= '1';
867 sel_crate_sig <= "111";
868 FTM_ftu_rs485_control_State <= IDLE;
869 end if;
870
871 when RATES_1 => -- wait one cycle for CRC calculation
872 enable_crc_from_FSM_sig <= '0';
873 FTM_ftu_rs485_control_State <= RATES_2;
874
875 when RATES_2 => -- transmit byte by byte
876 if (tx_busy_sig = '0') then
877 if (frame_cnt < 27) then
878 frame_cnt <= frame_cnt + 1;
879 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
880 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
881 tx_start_sig <= '1';
882 FTM_ftu_rs485_control_State <= RATES_2;
883 elsif (frame_cnt = 27) then
884 frame_cnt <= frame_cnt + 1;
885 tx_data_sig <= crc_sig;
886 tx_start_sig <= '1';
887 FTM_ftu_rs485_control_State <= RATES_2;
888 else
889 frame_cnt <= 0;
890 reset_crc_from_FSM_sig <= '1';
891 FTM_ftu_rs485_control_State <= RATES_3;
892 end if;
893 else
894 tx_start_sig <= '0';
895 FTM_ftu_rs485_control_State <= RATES_2;
896 end if;
897
898 when RATES_3 => -- wait for FTU answer
899 reset_crc_from_FSM_sig <= '0';
900 if (FTU_answer_ok_sig = '1') then
901 timeout_cnt <= 0;
902 sel_crc_input_source_sig <= '0';
903 FTM_ftu_rs485_control_State <= RATES;
904 else
905 if (timeout_cnt < FTU_RS485_TIMEOUT) then
906 timeout_cnt <= timeout_cnt + 1;
907 sel_crc_input_source_sig <= '1';
908 FTM_ftu_rs485_control_State <= RATES_3;
909 else
910 timeout_cnt <= 0;
911 sel_crc_input_source_sig <= '0';
912 rec_reset_sig <= '1';
913 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
914 retry_cnt <= retry_cnt + 1;
915 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
916 FTM_ftu_rs485_control_State <= RATES;
917 else
918 FTU_cnt <= FTU_cnt; -- move on
919 FTM_ftu_rs485_control_State <= RATES;
920 end if;
921 end if;
922 end if;
923
924 end case;
925 end if;
926 end process FTM_ftu_rs485_control_FSM;
927
928 -- Process to multiplex the different crate buses
929 sel_crate_process: process (sel_crate_sig,
930 rx_en_0_sig, rx_en_1_sig, rx_en_2_sig, rx_en_3_sig,
931 tx_en_0_sig, tx_en_1_sig, tx_en_2_sig, tx_en_3_sig,
932 rx_valid_0_sig, rx_valid_1_sig, rx_valid_2_sig, rx_valid_3_sig,
933 rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
934 tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
935 rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig,
936 tx_start_sig, tx_data_sig)
937 begin
938 case sel_crate_sig is
939 when "000" => -- crate 0
940 rx_en_sig <= rx_en_0_sig;
941 tx_en_sig <= tx_en_0_sig;
942 rx_valid_sig <= rx_valid_0_sig;
943 rec_data_sig <= rx_data_0_sig;
944 tx_busy_sig <= tx_busy_0_sig;
945 rx_busy_sig <= rx_busy_0_sig;
946 tx_start_0_sig <= tx_start_sig;
947 tx_start_1_sig <= '0';
948 tx_start_2_sig <= '0';
949 tx_start_3_sig <= '0';
950 tx_data_0_sig <= tx_data_sig;
951 tx_data_1_sig <= (others => '0');
952 tx_data_2_sig <= (others => '0');
953 tx_data_3_sig <= (others => '0');
954 when "001" => -- crate 1
955 rx_en_sig <= rx_en_1_sig;
956 tx_en_sig <= tx_en_1_sig;
957 rx_valid_sig <= rx_valid_1_sig;
958 rec_data_sig <= rx_data_1_sig;
959 tx_busy_sig <= tx_busy_1_sig;
960 rx_busy_sig <= rx_busy_1_sig;
961 tx_start_0_sig <= '0';
962 tx_start_1_sig <= tx_start_sig;
963 tx_start_2_sig <= '0';
964 tx_start_3_sig <= '0';
965 tx_data_0_sig <= (others => '0');
966 tx_data_1_sig <= tx_data_sig;
967 tx_data_2_sig <= (others => '0');
968 tx_data_3_sig <= (others => '0');
969 when "010" => -- crate 2
970 rx_en_sig <= rx_en_2_sig;
971 tx_en_sig <= tx_en_2_sig;
972 rx_valid_sig <= rx_valid_2_sig;
973 rec_data_sig <= rx_data_2_sig;
974 tx_busy_sig <= tx_busy_2_sig;
975 rx_busy_sig <= rx_busy_2_sig;
976 tx_start_0_sig <= '0';
977 tx_start_1_sig <= '0';
978 tx_start_2_sig <= tx_start_sig;
979 tx_start_3_sig <= '0';
980 tx_data_0_sig <= (others => '0');
981 tx_data_1_sig <= (others => '0');
982 tx_data_2_sig <= tx_data_sig;
983 tx_data_3_sig <= (others => '0');
984 when "011" => -- crate 3
985 rx_en_sig <= rx_en_3_sig;
986 tx_en_sig <= tx_en_3_sig;
987 rx_valid_sig <= rx_valid_3_sig;
988 rec_data_sig <= rx_data_3_sig;
989 tx_busy_sig <= tx_busy_3_sig;
990 rx_busy_sig <= rx_busy_3_sig;
991 tx_start_0_sig <= '0';
992 tx_start_1_sig <= '0';
993 tx_start_2_sig <= '0';
994 tx_start_3_sig <= tx_start_sig;
995 tx_data_0_sig <= (others => '0');
996 tx_data_1_sig <= (others => '0');
997 tx_data_2_sig <= (others => '0');
998 tx_data_3_sig <= tx_data_sig;
999 when others => -- no crate specified
1000 rx_en_sig <= '0';
1001 tx_en_sig <= '0';
1002 rx_valid_sig <= '0';
1003 rec_data_sig <= (others => '0');
1004 tx_busy_sig <= '0';
1005 rx_busy_sig <= '0';
1006 tx_start_0_sig <= '0';
1007 tx_start_1_sig <= '0';
1008 tx_start_2_sig <= '0';
1009 tx_start_3_sig <= '0';
1010 tx_data_0_sig <= (others => '0');
1011 tx_data_1_sig <= (others => '0');
1012 tx_data_2_sig <= (others => '0');
1013 tx_data_3_sig <= (others => '0');
1014 end case;
1015 end process;
1016
1017 -- Process to select the CRC input source (FSM or interpreter)
1018 sel_crc_cource_process : process (sel_crc_input_source_sig,
1019 reset_crc_from_interpreter_sig, reset_crc_from_FSM_sig,
1020 enable_crc_from_interpreter_sig, enable_crc_from_FSM_sig,
1021 rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0), crc_data_from_FSM_sig)
1022 begin
1023 case sel_crc_input_source_sig is
1024 when '0' => -- FSM
1025 reset_crc_sig <= reset_crc_from_FSM_sig;
1026 enable_crc_sig <= enable_crc_from_FSM_sig;
1027 crc_data_sig <= crc_data_from_FSM_sig;
1028 when '1' => -- interpreter
1029 reset_crc_sig <= reset_crc_from_interpreter_sig;
1030 enable_crc_sig <= enable_crc_from_interpreter_sig;
1031 crc_data_sig <= rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0);
1032 when others => -- signal undefined
1033 reset_crc_sig <= reset_crc_from_FSM_sig;
1034 enable_crc_sig <= enable_crc_from_FSM_sig;
1035 crc_data_sig <= crc_data_from_FSM_sig;
1036 end case;
1037 end process;
1038
1039 rx_en <= rx_en_sig;
1040 tx_en <= tx_en_sig;
1041
1042 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
1043 start_int_sig <= rec_valid_sig and (not rx_busy_sig); -- avoid continuing to early after FTU answer
1044
1045end Behavioral;
1046
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