source: firmware/FTM/ftu_control/FTM_ftu_control.vhd@ 11191

Last change on this file since 11191 was 10929, checked in by weitzel, 14 years ago
FTM: patch in LP interface to correct for swapped channels; change in FTUcontrol to fix first-board-bug
File size: 53.2 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 17:54:04 02/02/2011
6-- Design Name:
7-- Module Name: FTM_ftu_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Communication of FTM with the 40 FTU boards of the FACT camera
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25library ftm_definitions;
26USE ftm_definitions.ftm_array_types.all;
27USE ftm_definitions.ftm_constants.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTM_ftu_control is
35 port(
36 clk_50MHz : in std_logic; -- main clock
37
38 -- global bus enables for FTU crates 0-3
39 rx_en : out STD_LOGIC; -- receiver enable
40 tx_en : out STD_LOGIC; -- transmitter enable
41
42 -- FTU crate 0 data I/O
43 rx_d_0 : in STD_LOGIC;
44 tx_d_0 : out STD_LOGIC;
45
46 -- FTU crate 1 data I/O
47 rx_d_1 : in STD_LOGIC;
48 tx_d_1 : out STD_LOGIC;
49
50 -- FTU crate 2 data I/O
51 rx_d_2 : in STD_LOGIC;
52 tx_d_2 : out STD_LOGIC;
53
54 -- FTU crate 3 data I/O
55 rx_d_3 : in STD_LOGIC;
56 tx_d_3 : out STD_LOGIC;
57
58 -- commands from FTM main control
59 new_config : in std_logic;
60 ping_all : in std_logic;
61 read_rates : in std_logic;
62
63 -- answers to FTM main control
64 read_rates_started : out std_logic := '0';
65 read_rates_done : out std_logic := '0';
66 new_config_started : out std_logic := '0';
67 new_config_done : out std_logic := '0';
68 ping_all_started : out std_logic := '0';
69 ping_all_done : out std_logic := '0';
70
71 -- active FTU lists
72 ftu_active_cr0 : in std_logic_vector (15 downto 0);
73 ftu_active_cr1 : in std_logic_vector (15 downto 0);
74 ftu_active_cr2 : in std_logic_vector (15 downto 0);
75 ftu_active_cr3 : in std_logic_vector (15 downto 0);
76
77 --error message interface to ethernet control
78 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
79 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
80 ftu_error_send : out std_logic := '0';
81 ftu_error_send_ack : in std_logic;
82 ftu_error_send_ready : in std_logic;
83
84 -- communication with static (config) RAM
85 -- this RAM is only read by FTU_control
86 static_RAM_busy : in std_logic;
87 static_RAM_started : in std_logic;
88 static_RAM_ready : in std_logic;
89 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
90 read_static_RAM : out std_logic := '0';
91 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
92
93 -- communication with dynamic RAM (e.g. rates)
94 -- this RAM is only written by FTU_control
95 dynamic_RAM_busy : in std_logic;
96 dynamic_RAM_started : in std_logic;
97 dynamic_RAM_ready : in std_logic;
98 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
99 write_dynamic_RAM : out std_logic := '0';
100 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
101
102 -- communication with FTU-list RAM
103 -- this RAM is only written by FTU_control
104 FTUlist_RAM_busy : in std_logic;
105 FTUlist_RAM_started : in std_logic;
106 FTUlist_RAM_ready : in std_logic;
107 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
108 write_FTUlist_RAM : out std_logic := '0';
109 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
110
111 );
112end FTM_ftu_control;
113
114architecture Behavioral of FTM_ftu_control is
115
116 -- list of active FTUs, read out from static RAM before starting to contact FTUs
117 signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
118 --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0'));
119
120 -- signals to count the number of responding FTUs (per crate and total) in case of a ping
121 signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
122 signal no_of_FTU_answer_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE) := 0;
123
124 -- FTU configuration data, read out from static RAM (board by board)
125 signal FTU_dac_array_RAM_sig : FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
126 signal FTU_enable_array_RAM_sig : FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
127 signal FTU_prescaling_RAM_sig : std_logic_vector(15 downto 0) := (others => '0');
128
129 -- signals for receiver of FTU communication
130 signal rec_reset_sig : std_logic := '0'; -- reset
131 signal rec_data_sig : std_logic_vector (7 DOWNTO 0);
132 signal rec_block_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- initialized in FTM_ftu_rs485_receiver
133 signal rec_valid_sig : std_logic; -- initialized in FTM_ftu_rs485_receiver
134
135 -- select signal to multiplex the different crates
136 signal sel_crate_sig : STD_LOGIC_VECTOR (2 downto 0) := "111";
137
138 -- global signals after multiplexer
139 signal rx_en_sig : std_logic := '0';
140 signal tx_en_sig : std_logic := '0';
141 signal rx_valid_sig : std_logic := '0';
142 signal tx_busy_sig : std_logic := '0';
143 signal tx_start_sig : std_logic := '0';
144 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
145 signal rx_busy_sig : std_logic := '0';
146 signal start_int_sig : std_logic := '0';
147
148 -- signals for interpreter of FTU communication
149 signal FTU_brd_add_sig : std_logic_vector (5 DOWNTO 0) := (others => '0');
150 signal FTU_command_sig : std_logic_vector (7 DOWNTO 0) := (others => '1');
151 signal FTU_answer_ok_sig : std_logic; -- initialized in interpreter
152 signal FTU_dac_array_sig : FTU_dac_array_type; -- initialized in interpreter
153 signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter
154 signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter
155 signal FTU_overflow_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
156 signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
157 signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter
158 signal FTU_dna_sig : std_logic_vector(63 downto 0); -- initialized in interpreter
159
160 -- rx_enable and tx_enable lines from different FTM_ftu_rs485_interface
161 -- initialized in corresponding interface
162 signal rx_en_0_sig : STD_LOGIC;
163 signal tx_en_0_sig : STD_LOGIC;
164 signal rx_en_1_sig : STD_LOGIC;
165 signal tx_en_1_sig : STD_LOGIC;
166 signal rx_en_2_sig : STD_LOGIC;
167 signal tx_en_2_sig : STD_LOGIC;
168 signal rx_en_3_sig : STD_LOGIC;
169 signal tx_en_3_sig : STD_LOGIC;
170
171 signal tx_start_0_sig : std_logic := '0';
172 signal tx_data_0_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
173 signal tx_busy_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
174 signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0
175 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0
176 signal rx_busy_0_sig : std_logic; -- initialized in FTU_rs485_interface_0
177
178 signal tx_start_1_sig : std_logic := '0';
179 signal tx_data_1_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
180 signal tx_busy_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
181 signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1
182 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1
183 signal rx_busy_1_sig : std_logic; -- initialized in FTU_rs485_interface_1
184
185 signal tx_start_2_sig : std_logic := '0';
186 signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
187 signal tx_busy_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
188 signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2
189 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2
190 signal rx_busy_2_sig : std_logic; -- initialized in FTU_rs485_interface_2
191
192 signal tx_start_3_sig : std_logic := '0';
193 signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
194 signal tx_busy_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
195 signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3
196 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3
197 signal rx_busy_3_sig : std_logic; -- initialized in FTU_rs485_interface_3
198
199 -- signals to control and read out CRC
200 signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter
201 signal reset_crc_sig : std_logic;
202 signal enable_crc_sig : std_logic;
203 signal crc_data_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
204 signal reset_crc_from_FSM_sig : std_logic := '0';
205 signal reset_crc_from_interpreter_sig : std_logic;
206 signal enable_crc_from_FSM_sig : std_logic := '0';
207 signal enable_crc_from_interpreter_sig : std_logic;
208 signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
209 signal crc_data_from_FSM_sig_cp : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
210 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
211 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
212
213 -- various loop counters
214 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;
215 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0;
216 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0;
217 signal FTU_register_cnt : integer range 0 to (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) := 0;
218 signal FTU_command_cnt : integer range 0 to 3 := 0;
219 signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0;
220 signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0;
221 signal FTU_list_header_cnt : integer range 0 to (FTU_LIST_RAM_OFFSET + 1):= 0;
222 signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0;
223
224 -- counter to define timeout and number of retries
225 signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
226 signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
227
228 --Zwischenrechnungen
229 signal FTU_cnt_offset_sig : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0;
230 signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0;
231
232 component FTM_ftu_rs485_interface
233 port(
234 clk : IN std_logic;
235 -- RS485
236 rx_d : IN std_logic;
237 rx_en : OUT std_logic;
238 tx_d : OUT std_logic;
239 tx_en : OUT std_logic;
240 -- FPGA
241 rx_data : OUT std_logic_vector (7 DOWNTO 0);
242 rx_busy : OUT std_logic := '0';
243 rx_valid : OUT std_logic := '0';
244 tx_data : IN std_logic_vector (7 DOWNTO 0);
245 tx_busy : OUT std_logic := '0';
246 tx_start : IN std_logic
247 );
248 end component;
249
250 component FTM_ftu_rs485_receiver
251 port(
252 rec_clk : in std_logic;
253 rec_reset : in std_logic;
254 --rx_busy : in std_logic;
255 rec_din : in std_logic_vector(7 downto 0);
256 rec_den : in std_logic;
257 rec_dout : out std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0');
258 rec_valid : out std_logic := '0'
259 );
260 end component;
261
262 component FTM_ftu_rs485_interpreter
263 port(
264 clk : IN std_logic;
265 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0);
266 block_valid : IN std_logic;
267 crc : IN std_logic_vector(7 downto 0);
268 FTU_brd_add : IN std_logic_vector(5 downto 0);
269 FTU_command : IN std_logic_vector(7 downto 0);
270 reset_crc : OUT std_logic := '0';
271 enable_crc : OUT std_logic := '0';
272 FTU_answer_ok : OUT std_logic := '0';
273 FTU_dac_array : OUT FTU_dac_array_type;
274 FTU_enable_array : OUT FTU_enable_array_type;
275 FTU_rate_array : OUT FTU_rate_array_type;
276 FTU_overflow : OUT std_logic_vector(7 downto 0);
277 FTU_prescaling : OUT std_logic_vector(7 downto 0);
278 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
279 FTU_dna : OUT std_logic_vector(63 downto 0)
280 );
281 end component;
282
283 component ucrc_par
284 generic(
285 POLYNOMIAL : std_logic_vector;
286 INIT_VALUE : std_logic_vector;
287 DATA_WIDTH : integer range 2 to 256;
288 SYNC_RESET : integer range 0 to 1
289 );
290 port(
291 clk_i : in std_logic;
292 rst_i : in std_logic;
293 clken_i : in std_logic;
294 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
295 match_o : out std_logic;
296 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)
297 );
298 end component;
299
300 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
301 PING, PING_END, FTU_LIST,
302 SEND_ERROR_1, SEND_ERROR_2,
303 RATES, RATES_1, RATES_2, RATES_3,
304 DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3,
305 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
306 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
307 PING_1, PING_2, PING_3, PING_END_1, PING_END_2, PING_END_3,
308 FTU_LIST_1, FTU_LIST_2, FTU_LIST_3);
309 signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
310 signal after_error_State : FTM_ftu_rs485_control_StateType;
311
312begin
313
314 Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0
315 port map(
316 clk => clk_50MHz,
317 -- RS485
318 rx_d => rx_d_0,
319 rx_en => rx_en_0_sig,
320 tx_d => tx_d_0,
321 tx_en => tx_en_0_sig,
322 -- FPGA
323 rx_data => rx_data_0_sig,
324 rx_busy => rx_busy_0_sig,
325 rx_valid => rx_valid_0_sig,
326 tx_data => tx_data_0_sig,
327 tx_busy => tx_busy_0_sig,
328 tx_start => tx_start_0_sig
329 );
330
331 Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1
332 port map(
333 clk => clk_50MHz,
334 -- RS485
335 rx_d => rx_d_1,
336 rx_en => rx_en_1_sig,
337 tx_d => tx_d_1,
338 tx_en => tx_en_1_sig,
339 -- FPGA
340 rx_data => rx_data_1_sig,
341 rx_busy => rx_busy_1_sig,
342 rx_valid => rx_valid_1_sig,
343 tx_data => tx_data_1_sig,
344 tx_busy => tx_busy_1_sig,
345 tx_start => tx_start_1_sig
346 );
347
348 Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2
349 port map(
350 clk => clk_50MHz,
351 -- RS485
352 rx_d => rx_d_2,
353 rx_en => rx_en_2_sig,
354 tx_d => tx_d_2,
355 tx_en => tx_en_2_sig,
356 -- FPGA
357 rx_data => rx_data_2_sig,
358 rx_busy => rx_busy_2_sig,
359 rx_valid => rx_valid_2_sig,
360 tx_data => tx_data_2_sig,
361 tx_busy => tx_busy_2_sig,
362 tx_start => tx_start_2_sig
363 );
364
365 Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3
366 port map(
367 clk => clk_50MHz,
368 -- RS485
369 rx_d => rx_d_3,
370 rx_en => rx_en_3_sig,
371 tx_d => tx_d_3,
372 tx_en => tx_en_3_sig,
373 -- FPGA
374 rx_data => rx_data_3_sig,
375 rx_busy => rx_busy_3_sig,
376 rx_valid => rx_valid_3_sig,
377 tx_data => tx_data_3_sig,
378 tx_busy => tx_busy_3_sig,
379 tx_start => tx_start_3_sig
380 );
381
382 Inst_FTM_ftu_rs485_receiver : FTM_ftu_rs485_receiver
383 port map(
384 rec_clk => clk_50MHz,
385 rec_reset => rec_reset_sig,
386 --rx_busy =>,
387 rec_din => rec_data_sig,
388 rec_den => rx_valid_sig,
389 rec_dout => rec_block_sig,
390 rec_valid => rec_valid_sig
391 );
392
393 Inst_FTM_ftu_rs485_interpreter : FTM_ftu_rs485_interpreter
394 port map(
395 clk => clk_50MHz,
396 data_block => rec_block_sig,
397 block_valid => start_int_sig,
398 crc => crc_sig,
399 FTU_brd_add => FTU_brd_add_sig,
400 FTU_command => FTU_command_sig,
401 reset_crc => reset_crc_from_interpreter_sig,
402 enable_crc => enable_crc_from_interpreter_sig,
403 FTU_answer_ok => FTU_answer_ok_sig,
404 FTU_dac_array => FTU_dac_array_sig,
405 FTU_enable_array => FTU_enable_array_sig,
406 FTU_rate_array => FTU_rate_array_sig,
407 FTU_overflow => FTU_overflow_sig,
408 FTU_prescaling => FTU_prescaling_sig,
409 FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
410 FTU_dna => FTU_dna_sig
411 );
412
413 Inst_ucrc_par : ucrc_par
414 generic map(
415 POLYNOMIAL => CRC_POLYNOMIAL,
416 INIT_VALUE => CRC_INIT_VALUE,
417 DATA_WIDTH => (FTU_RS485_BLOCK_WIDTH - 8),
418 SYNC_RESET => 1
419 )
420 port map(
421 clk_i => clk_50MHz,
422 rst_i => reset_crc_sig,
423 clken_i => enable_crc_sig,
424 data_i => crc_data_sig,
425 match_o => open,
426 crc_o => crc_sig_inv
427 );
428
429 -- Main finite state machine to control all 40 FTUs
430 FTM_ftu_rs485_control_FSM: process (clk_50MHz)
431 begin
432 if Rising_edge(clk_50MHz) then
433 case FTM_ftu_rs485_control_State is
434
435 when INIT => -- reset CRC register
436 reset_crc_from_FSM_sig <= '1';
437 FTM_ftu_rs485_control_State <= IDLE;
438
439 when IDLE => -- wait for command from outside
440 sel_crate_sig <= "111";
441 sel_crc_input_source_sig <= '0';
442 reset_crc_from_FSM_sig <= '0';
443 enable_crc_from_FSM_sig <= '0';
444 --new_config_done <= '0';
445 --ping_all_done <= '0';
446 --read_rates_done <= '0';
447 if (new_config = '1') then
448 new_config_done <= '0';--
449 new_config_started <= '1';
450 ping_all_started <= '0';
451 read_rates_started <= '0';
452 FTM_ftu_rs485_control_State <= ACTIVE_LIST;
453 elsif (new_config = '0' and ping_all = '1') then
454 ping_all_done <= '0';--
455 new_config_started <= '0';
456 ping_all_started <= '1';
457 read_rates_started <= '0';
458 rec_reset_sig <= '1';
459 FTM_ftu_rs485_control_State <= PING;
460 elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then
461 read_rates_done <= '0';--
462 new_config_started <= '0';
463 ping_all_started <= '0';
464 read_rates_started <= '1';
465 FTM_ftu_rs485_control_State <= RATES;
466 else
467 new_config_started <= '0';
468 ping_all_started <= '0';
469 read_rates_started <= '0';
470 FTM_ftu_rs485_control_State <= IDLE;
471 end if;
472
473 when ACTIVE_LIST => -- copy active FTU list from inputs to array
474 active_FTU_array_sig(0) <= ftu_active_cr0;
475 active_FTU_array_sig(1) <= ftu_active_cr1;
476 active_FTU_array_sig(2) <= ftu_active_cr2;
477 active_FTU_array_sig(3) <= ftu_active_cr3;
478 FTM_ftu_rs485_control_State <= READ_CONFIG;
479
480-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list
481-- if (active_FTU_list_cnt < NO_OF_CRATES) then
482-- active_FTU_list_cnt <= active_FTU_list_cnt + 1;
483-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1;
484-- else
485-- active_FTU_list_cnt <= 0;
486-- FTM_ftu_rs485_control_State <= READ_CONFIG;
487-- end if;
488
489-- when ACTIVE_LIST_1 =>
490-- if (static_RAM_busy = '0') then
491-- read_static_RAM <= '1';
492-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH);
493-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2;
494-- end if;
495
496-- when ACTIVE_LIST_2 =>
497-- if (static_RAM_started = '1') then
498-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;
499-- end if;
500
501-- when ACTIVE_LIST_3 =>
502-- if (static_RAM_ready = '1') then
503-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;
504-- read_static_RAM <= '0';
505-- FTM_ftu_rs485_control_State <= ACTIVE_LIST;
506-- end if;
507
508 when READ_CONFIG => -- read configuration of FTUs (one by one)
509 if (crate_cnt < NO_OF_CRATES) then
510 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
511 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
512 if (FTU_register_cnt < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1)) then
513 FTU_register_cnt <= FTU_register_cnt + 1;
514 FTM_ftu_rs485_control_State <= READ_CONFIG_1;
515 else
516 FTU_cnt <= FTU_cnt + 1;
517 FTU_register_cnt <= 0;
518 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
519 rec_reset_sig <= '1';
520 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
521 else
522 FTM_ftu_rs485_control_State <= READ_CONFIG;
523 end if;
524 end if;
525 else
526 crate_cnt <= crate_cnt + 1;
527 FTU_cnt <= 0;
528 FTM_ftu_rs485_control_State <= READ_CONFIG;
529 end if;
530 else
531 crate_cnt <= 0;
532 new_config_started <= '0';
533 new_config_done <= '1';
534 sel_crate_sig <= "111";
535 FTM_ftu_rs485_control_State <= IDLE;
536 end if;
537
538 when READ_CONFIG_1 =>
539 if (static_RAM_busy = '0') then
540 read_static_RAM <= '1';
541 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_CFG_FTU_OFFSET +
542 crate_cnt * NO_OF_FTUS_PER_CRATE * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
543 FTU_cnt * (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG + 1) +
544 (FTU_register_cnt - 1), STATIC_RAM_ADDR_WIDTH);
545 FTM_ftu_rs485_control_State <= READ_CONFIG_2;
546 end if;
547
548 when READ_CONFIG_2 =>
549 if (static_RAM_started = '1') then
550 FTM_ftu_rs485_control_State <= READ_CONFIG_3;
551 end if;
552
553 when READ_CONFIG_3 =>
554 if (static_RAM_ready = '1') then
555 if ((FTU_register_cnt - 1) < NO_OF_FTU_ENABLE_REG) then
556 FTU_enable_array_RAM_sig(FTU_register_cnt - 1) <= data_static_RAM;
557 elsif ((FTU_register_cnt - 1) < (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
558 FTU_dac_array_RAM_sig((FTU_register_cnt - 1) - NO_OF_FTU_ENABLE_REG) <= data_static_RAM;
559 elsif ((FTU_register_cnt - 1) = (NO_OF_FTU_ENABLE_REG + NO_OF_FTU_DAC_REG)) then
560 FTU_prescaling_RAM_sig <= data_static_RAM;
561 end if;
562 read_static_RAM <= '0';
563 FTM_ftu_rs485_control_State <= READ_CONFIG;
564 end if;
565
566 when TRANSMIT_CONFIG => -- send configuration to FTUs (one by one)
567 rec_reset_sig <= '0';
568 if (FTU_command_cnt = 0) then -- DACs
569 FTU_command_cnt <= FTU_command_cnt + 1;
570 enable_crc_from_FSM_sig <= '1';
571 crc_data_from_FSM_sig <= "00000000"
572 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
573 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
574 & "00000000"
575 & FTU_dac_array_RAM_sig(4)(15 downto 8) & FTU_dac_array_RAM_sig(4)(7 downto 0)
576 & FTU_dac_array_RAM_sig(3)(15 downto 8) & FTU_dac_array_RAM_sig(3)(7 downto 0)
577 & FTU_dac_array_RAM_sig(2)(15 downto 8) & FTU_dac_array_RAM_sig(2)(7 downto 0)
578 & FTU_dac_array_RAM_sig(1)(15 downto 8) & FTU_dac_array_RAM_sig(1)(7 downto 0)
579 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0)
580 & "00000000" & FIRMWARE_ID & FTM_ADDRESS
581 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
582 & FTU_RS485_START_DELIM;
583 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
584 FTU_command_sig <= "00000000";
585 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
586 elsif (FTU_command_cnt = 1) then -- enables
587 FTU_command_cnt <= FTU_command_cnt + 1;
588 enable_crc_from_FSM_sig <= '1';
589 crc_data_from_FSM_sig <= "00000000"
590 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
591 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
592 & "00000000" & "00000000" & "00000000"
593 & FTU_enable_array_RAM_sig(3)(15 downto 8) & FTU_enable_array_RAM_sig(3)(7 downto 0)
594 & FTU_enable_array_RAM_sig(2)(15 downto 8) & FTU_enable_array_RAM_sig(2)(7 downto 0)
595 & FTU_enable_array_RAM_sig(1)(15 downto 8) & FTU_enable_array_RAM_sig(1)(7 downto 0)
596 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0)
597 & "00000011" & FIRMWARE_ID & FTM_ADDRESS
598 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
599 & FTU_RS485_START_DELIM;
600 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
601 FTU_command_sig <= "00000011";
602 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
603 elsif (FTU_command_cnt = 2) then -- prescaling
604 FTU_command_cnt <= FTU_command_cnt + 1;
605 enable_crc_from_FSM_sig <= '1';
606 crc_data_from_FSM_sig <= "00000000"
607 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
608 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
609 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
610 & "00000000" & "00000000" & "00000000" & "00000000"
611 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0)
612 & "00000110" & FIRMWARE_ID & FTM_ADDRESS
613 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2)
614 & FTU_RS485_START_DELIM;
615 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2);
616 FTU_command_sig <= "00000110";
617 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1;
618 else
619 FTU_command_cnt <= 0;
620 enable_crc_from_FSM_sig <= '0';
621 FTM_ftu_rs485_control_State <= READ_CONFIG;
622 end if;
623
624 when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation
625 enable_crc_from_FSM_sig <= '0';
626 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
627 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
628
629 when TRANSMIT_CONFIG_2 => -- transmit byte by byte
630 if (tx_busy_sig = '0') then
631 if (frame_cnt < 27) then
632 frame_cnt <= frame_cnt + 1;
633 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
634 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
635 tx_start_sig <= '1';
636 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
637 elsif (frame_cnt = 27) then
638 frame_cnt <= frame_cnt + 1;
639 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
640 tx_data_sig <= crc_sig;
641 tx_start_sig <= '1';
642 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
643 else
644 frame_cnt <= 0;
645 reset_crc_from_FSM_sig <= '1';
646 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
647 end if;
648 else
649 tx_start_sig <= '0';
650 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
651 end if;
652
653 when TRANSMIT_CONFIG_3 => -- wait for FTU answer
654 reset_crc_from_FSM_sig <= '0';
655 if (FTU_answer_ok_sig = '1') then
656 timeout_cnt <= 0;
657 retry_cnt <= 0;
658 sel_crc_input_source_sig <= '0';
659 if (retry_cnt = 0) then -- no errors
660 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
661 else -- send error message and move to next command;
662 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
663 after_error_State <= TRANSMIT_CONFIG;
664 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
665 end if;
666 else
667 if (timeout_cnt < FTU_RS485_TIMEOUT) then
668 timeout_cnt <= timeout_cnt + 1;
669 sel_crc_input_source_sig <= '1';
670 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_3;
671 else
672 timeout_cnt <= 0;
673 sel_crc_input_source_sig <= '0';
674 rec_reset_sig <= '1';
675 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
676 retry_cnt <= retry_cnt + 1;
677 FTU_command_cnt <= FTU_command_cnt - 1; -- try this command again
678 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
679 else
680 retry_cnt <= 0;
681 FTU_command_cnt <= FTU_command_cnt; -- send error message and move to next command
682 ftu_error_calls <= (others => '0');
683 after_error_State <= TRANSMIT_CONFIG;
684 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
685 end if;
686 end if;
687 end if;
688
689 when SEND_ERROR_1 => -- send an error message
690 ftu_error_send <= '1';
691 if (ftu_error_send_ack = '1') then
692 ftu_error_send <= '0';
693 FTM_ftu_rs485_control_State <= SEND_ERROR_2;
694 end if;
695
696 when SEND_ERROR_2 =>
697 if (ftu_error_send_ready = '1') then
698 FTM_ftu_rs485_control_State <= after_error_state;
699 end if;
700
701 when PING => -- ping all FTUs
702 rec_reset_sig <= '0';
703 if (crate_cnt < NO_OF_CRATES) then
704 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
705 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
706 FTU_cnt <= FTU_cnt + 1;
707 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
708 enable_crc_from_FSM_sig <= '1';
709 crc_data_from_FSM_sig <= "00000000"
710 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
711 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
712 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
713 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
714 & "00000101" & FIRMWARE_ID & FTM_ADDRESS
715 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
716 & FTU_RS485_START_DELIM;
717 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
718 FTU_command_sig <= "00000101";
719 FTM_ftu_rs485_control_State <= PING_1;
720 else
721 FTM_ftu_rs485_control_State <= PING;
722 end if;
723 else
724 crate_cnt <= crate_cnt + 1;
725 FTU_cnt <= 0;
726 FTM_ftu_rs485_control_State <= PING;
727 end if;
728 else
729 crate_cnt <= 0;
730 FTM_ftu_rs485_control_State <= PING_END;
731 end if;
732
733 when PING_1 => -- wait one cycle for CRC calculation
734 enable_crc_from_FSM_sig <= '0';
735 --rec_reset_sig <= '1';
736 FTM_ftu_rs485_control_State <= PING_2;
737
738 when PING_2 => -- transmit byte by byte
739 rec_reset_sig <= '0';
740 if (tx_busy_sig = '0') then
741 if (frame_cnt < 27) then
742 frame_cnt <= frame_cnt + 1;
743 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
744 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
745 tx_start_sig <= '1';
746 FTM_ftu_rs485_control_State <= PING_2;
747 elsif (frame_cnt = 27) then
748 frame_cnt <= frame_cnt + 1;
749 tx_data_sig <= crc_sig;
750 tx_start_sig <= '1';
751 rec_reset_sig <= '1'; -- new
752 FTM_ftu_rs485_control_State <= PING_2;
753 else
754 frame_cnt <= 0;
755 reset_crc_from_FSM_sig <= '1';
756 FTM_ftu_rs485_control_State <= PING_3;
757 end if;
758 else
759 tx_start_sig <= '0';
760 FTM_ftu_rs485_control_State <= PING_2;
761 end if;
762
763 when PING_3 => -- wait for FTU answer
764 reset_crc_from_FSM_sig <= '0';
765 if (FTU_answer_ok_sig = '1') then
766 FTU_answer_array_sig(crate_cnt) <= FTU_answer_array_sig(crate_cnt) + 1;
767 no_of_FTU_answer_sig <= no_of_FTU_answer_sig + 1;
768 timeout_cnt <= 0;
769 sel_crc_input_source_sig <= '0';
770 FTM_ftu_rs485_control_State <= FTU_LIST;
771 else
772 if (timeout_cnt < FTU_RS485_TIMEOUT) then
773 timeout_cnt <= timeout_cnt + 1;
774 sel_crc_input_source_sig <= '1';
775 FTM_ftu_rs485_control_State <= PING_3;
776 else
777 timeout_cnt <= 0;
778 sel_crc_input_source_sig <= '0';
779 rec_reset_sig <= '1';
780 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
781 retry_cnt <= retry_cnt + 1;
782 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
783 FTM_ftu_rs485_control_State <= PING;
784 else
785 FTU_cnt <= FTU_cnt; -- move on
786 FTM_ftu_rs485_control_State <= FTU_LIST;
787 end if;
788 end if;
789 end if;
790
791 when FTU_LIST => -- fill FTU-list for actual FTU
792 rec_reset_sig <= '0';
793 if (FTU_list_reg_cnt < NO_OF_FTU_LIST_REG) then
794 FTU_list_reg_cnt <= FTU_list_reg_cnt + 1;
795 FTM_ftu_rs485_control_State <= FTU_LIST_1;
796 else
797 FTU_list_reg_cnt <= 0;
798 retry_cnt <= 0;
799 FTM_ftu_rs485_control_State <= PING;
800 end if;
801
802 when FTU_LIST_1 =>
803 if (FTUlist_RAM_busy = '0') then
804 write_FTUlist_RAM <= '1';
805 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
806 (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) +
807 ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) +
808 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
809 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
810 if ((FTU_list_reg_cnt - 1) = 0) then
811 data_FTUlist_RAM <= "000000" & conv_std_logic_vector((retry_cnt + 1),2) & "00" & FTU_brd_add_sig;
812 elsif ((FTU_list_reg_cnt - 1) = 1) then
813 data_FTUlist_RAM <= FTU_dna_sig(63 downto 48);
814 elsif ((FTU_list_reg_cnt - 1) = 2) then
815 data_FTUlist_RAM <= FTU_dna_sig(47 downto 32);
816 elsif ((FTU_list_reg_cnt - 1) = 3) then
817 data_FTUlist_RAM <= FTU_dna_sig(31 downto 16);
818 elsif ((FTU_list_reg_cnt - 1) = 4) then
819 data_FTUlist_RAM <= FTU_dna_sig(15 downto 0);
820 elsif ((FTU_list_reg_cnt - 1) = 5) then
821 data_FTUlist_RAM <= "00000000" & FTU_crc_error_cnt_sig;
822 end if;
823 else
824 data_FTUlist_RAM <= (others => '0');
825 end if;
826 FTM_ftu_rs485_control_State <= FTU_LIST_2;
827 end if;
828
829 when FTU_LIST_2 =>
830 if (FTUlist_RAM_started = '1') then
831 write_FTUlist_RAM <= '0';
832 FTM_ftu_rs485_control_State <= FTU_LIST_3;
833 end if;
834
835 when FTU_LIST_3 =>
836 if (FTUlist_RAM_ready = '1') then
837 FTM_ftu_rs485_control_State <= FTU_LIST;
838 end if;
839
840 when PING_END => -- add final ping statistics to FTU-list
841 if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then
842 --FTU_list_header_cnt <= FTU_list_header_cnt + 1;
843 FTM_ftu_rs485_control_State <= PING_END_1;
844 else
845 FTU_list_header_cnt <= 0;
846 ping_all_started <= '0';
847 ping_all_done <= '1';
848 sel_crate_sig <= "111";
849 FTU_answer_array_sig(0) <= 0;
850 FTU_answer_array_sig(1) <= 0;
851 FTU_answer_array_sig(2) <= 0;
852 FTU_answer_array_sig(3) <= 0;
853 no_of_FTU_answer_sig <= 0;
854 FTM_ftu_rs485_control_State <= IDLE;
855 end if;
856
857 when PING_END_1 =>
858 if (FTUlist_RAM_busy = '0') then
859 write_FTUlist_RAM <= '1';
860 --addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
861 addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt), FTU_LIST_RAM_ADDR_WIDTH);
862 --if ((FTU_list_header_cnt - 1) = 0) then
863 if ((FTU_list_header_cnt) = 0) then
864 data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16);
865 --elsif ((FTU_list_header_cnt - 1) < 5) then
866 elsif ((FTU_list_header_cnt) < 5) then
867 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16);
868 data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 1), 16);
869 --elsif ((FTU_list_header_cnt - 1) < 9) then
870 elsif ((FTU_list_header_cnt) < 9) then
871 --data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6);
872 --data_FTUlist_RAM <= conv_std_logic_vector(FTU_list_header_cnt - 6, 16);
873 data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 5);
874 end if;
875 FTM_ftu_rs485_control_State <= PING_END_2;
876 end if;
877
878 when PING_END_2 =>
879 if (FTUlist_RAM_started = '1') then
880 write_FTUlist_RAM <= '0';
881 FTM_ftu_rs485_control_State <= PING_END_3;
882 end if;
883
884 when PING_END_3 =>
885 if (FTUlist_RAM_ready = '1') then
886 FTU_list_header_cnt <= FTU_list_header_cnt + 1;
887 FTM_ftu_rs485_control_State <= PING_END;
888 end if;
889
890 when RATES => -- read all FTU rates
891 rec_reset_sig <= '0';
892 if (crate_cnt < NO_OF_CRATES) then
893 sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
894 if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
895 FTU_cnt <= FTU_cnt + 1;
896 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
897 enable_crc_from_FSM_sig <= '1';
898 crc_data_from_FSM_sig <= "00000000"
899 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
900 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
901 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
902 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
903 & "00000010" & FIRMWARE_ID & FTM_ADDRESS
904 & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
905 & FTU_RS485_START_DELIM;
906 FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
907 FTU_command_sig <= "00000010";
908 FTM_ftu_rs485_control_State <= RATES_1;
909 else
910 FTM_ftu_rs485_control_State <= RATES;
911 end if;
912 else
913 crate_cnt <= crate_cnt + 1;
914 FTU_cnt <= 0;
915 FTM_ftu_rs485_control_State <= RATES;
916 end if;
917 else
918 crate_cnt <= 0;
919 read_rates_started <= '0';
920 read_rates_done <= '1';
921 sel_crate_sig <= "111";
922 FTM_ftu_rs485_control_State <= IDLE;
923 end if;
924
925 when RATES_1 => -- wait one cycle for CRC calculation
926 enable_crc_from_FSM_sig <= '0';
927 --rec_reset_sig <= '1'; --new
928 crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
929 FTM_ftu_rs485_control_State <= RATES_2;
930
931 when RATES_2 => -- transmit byte by byte
932 rec_reset_sig <= '0'; --new
933 if (tx_busy_sig = '0') then
934 if (frame_cnt < 27) then
935 frame_cnt <= frame_cnt + 1;
936 tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
937 crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
938 tx_start_sig <= '1';
939 FTM_ftu_rs485_control_State <= RATES_2;
940 elsif (frame_cnt = 27) then
941 frame_cnt <= frame_cnt + 1;
942 ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
943 tx_data_sig <= crc_sig;
944 tx_start_sig <= '1';
945 rec_reset_sig <= '1';
946 FTM_ftu_rs485_control_State <= RATES_2;
947 else
948 frame_cnt <= 0;
949 reset_crc_from_FSM_sig <= '1';
950 FTM_ftu_rs485_control_State <= RATES_3;
951 end if;
952 else
953 tx_start_sig <= '0';
954 FTM_ftu_rs485_control_State <= RATES_2;
955 end if;
956
957 when RATES_3 => -- wait for FTU answer
958 reset_crc_from_FSM_sig <= '0';
959 if (FTU_answer_ok_sig = '1') then
960 timeout_cnt <= 0;
961 sel_crc_input_source_sig <= '0';
962 --FTM_ftu_rs485_control_State <= RATES;
963 if (retry_cnt = 0) then -- no errors
964 FTM_ftu_rs485_control_State <= DD_RAM;
965 else -- send error message and move to next command;
966 ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
967 after_error_State <= DD_RAM;
968 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
969 end if;
970 else
971 if (timeout_cnt < FTU_RS485_TIMEOUT) then
972 timeout_cnt <= timeout_cnt + 1;
973 sel_crc_input_source_sig <= '1';
974 FTM_ftu_rs485_control_State <= RATES_3;
975 else
976 timeout_cnt <= 0;
977 sel_crc_input_source_sig <= '0';
978 rec_reset_sig <= '1';
979 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
980 retry_cnt <= retry_cnt + 1;
981 FTU_cnt <= FTU_cnt - 1; -- repeat this FTU
982 FTM_ftu_rs485_control_State <= RATES;
983 else
984 --retry_cnt <= 0;
985 FTU_cnt <= FTU_cnt; -- move on
986 ftu_error_calls <= (others => '0');
987 after_error_State <= DD_RAM;
988 FTM_ftu_rs485_control_State <= SEND_ERROR_1;
989 end if;
990 end if;
991 end if;
992
993 when DD_RAM => -- write rates of actual FTU to DD RAM
994 rec_reset_sig <= '0';
995 if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then
996 DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1;
997 FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG);
998 crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG);
999 FTM_ftu_rs485_control_State <= DD_RAM_1;
1000 else
1001 DD_RAM_reg_cnt <= 0;
1002 retry_cnt <= 0;
1003 FTM_ftu_rs485_control_State <= RATES;
1004 end if;
1005
1006 when DD_RAM_1 =>
1007 if (dynamic_RAM_busy = '0') then
1008 write_dynamic_RAM <= '1';
1009 addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1010 crate_cnt_offset_sig +
1011 --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) +
1012 --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1013 FTU_cnt_offset_sig +
1014 (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1015 if ( (retry_cnt < FTU_RS485_NO_OF_RETRY)
1016 and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG))
1017 and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then
1018 if ((DD_RAM_reg_cnt - 1) = 0) then
1019 data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16);
1020 elsif ((DD_RAM_reg_cnt - 1) = 1) then
1021 data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0);
1022 elsif ((DD_RAM_reg_cnt - 1) = 2) then
1023 data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16);
1024 elsif ((DD_RAM_reg_cnt - 1) = 3) then
1025 data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0);
1026 elsif ((DD_RAM_reg_cnt - 1) = 4) then
1027 data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16);
1028 elsif ((DD_RAM_reg_cnt - 1) = 5) then
1029 data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0);
1030 elsif ((DD_RAM_reg_cnt - 1) = 6) then
1031 data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16);
1032 elsif ((DD_RAM_reg_cnt - 1) = 7) then
1033 data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0);
1034 elsif ((DD_RAM_reg_cnt - 1) = 8) then
1035 data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16);
1036 elsif ((DD_RAM_reg_cnt - 1) = 9) then
1037 data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0);
1038 elsif ((DD_RAM_reg_cnt - 1) = 10) then
1039 data_dynamic_RAM <= "00000000" & FTU_overflow_sig;
1040 elsif ((DD_RAM_reg_cnt - 1) = 11) then
1041 data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig;
1042-- elsif ((DD_RAM_reg_cnt - 1) = 10) then
1043-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1044-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1045-- FTU_cnt_offset_sig +
1046-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1047-- elsif ((DD_RAM_reg_cnt - 1) = 11) then
1048-- --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH);
1049-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
1050-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
1051-- FTU_cnt_offset_sig +
1052-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
1053 end if;
1054 else
1055 data_dynamic_RAM <= (others => '0');
1056 end if;
1057 FTM_ftu_rs485_control_State <= DD_RAM_2;
1058 end if;
1059
1060 when DD_RAM_2 =>
1061 if (dynamic_RAM_started = '1') then
1062 write_dynamic_RAM <= '0';
1063 FTM_ftu_rs485_control_State <= DD_RAM_3;
1064 end if;
1065
1066 when DD_RAM_3 =>
1067 if (dynamic_RAM_ready = '1') then
1068 FTM_ftu_rs485_control_State <= DD_RAM;
1069 end if;
1070
1071 end case;
1072 end if;
1073 end process FTM_ftu_rs485_control_FSM;
1074
1075 -- Process to multiplex the different crate buses
1076 sel_crate_process: process (sel_crate_sig,
1077 rx_en_0_sig, rx_en_1_sig, rx_en_2_sig, rx_en_3_sig,
1078 tx_en_0_sig, tx_en_1_sig, tx_en_2_sig, tx_en_3_sig,
1079 rx_valid_0_sig, rx_valid_1_sig, rx_valid_2_sig, rx_valid_3_sig,
1080 rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
1081 tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
1082 rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig,
1083 tx_start_sig, tx_data_sig)
1084 begin
1085 case sel_crate_sig is
1086 when "000" => -- crate 0
1087 rx_en_sig <= rx_en_0_sig;
1088 tx_en_sig <= tx_en_0_sig;
1089 rx_valid_sig <= rx_valid_0_sig;
1090 rec_data_sig <= rx_data_0_sig;
1091 tx_busy_sig <= tx_busy_0_sig;
1092 rx_busy_sig <= rx_busy_0_sig;
1093 tx_start_0_sig <= tx_start_sig;
1094 tx_start_1_sig <= '0';
1095 tx_start_2_sig <= '0';
1096 tx_start_3_sig <= '0';
1097 tx_data_0_sig <= tx_data_sig;
1098 tx_data_1_sig <= (others => '0');
1099 tx_data_2_sig <= (others => '0');
1100 tx_data_3_sig <= (others => '0');
1101 when "001" => -- crate 1
1102 rx_en_sig <= rx_en_1_sig;
1103 tx_en_sig <= tx_en_1_sig;
1104 rx_valid_sig <= rx_valid_1_sig;
1105 rec_data_sig <= rx_data_1_sig;
1106 tx_busy_sig <= tx_busy_1_sig;
1107 rx_busy_sig <= rx_busy_1_sig;
1108 tx_start_0_sig <= '0';
1109 tx_start_1_sig <= tx_start_sig;
1110 tx_start_2_sig <= '0';
1111 tx_start_3_sig <= '0';
1112 tx_data_0_sig <= (others => '0');
1113 tx_data_1_sig <= tx_data_sig;
1114 tx_data_2_sig <= (others => '0');
1115 tx_data_3_sig <= (others => '0');
1116 when "010" => -- crate 2
1117 rx_en_sig <= rx_en_2_sig;
1118 tx_en_sig <= tx_en_2_sig;
1119 rx_valid_sig <= rx_valid_2_sig;
1120 rec_data_sig <= rx_data_2_sig;
1121 tx_busy_sig <= tx_busy_2_sig;
1122 rx_busy_sig <= rx_busy_2_sig;
1123 tx_start_0_sig <= '0';
1124 tx_start_1_sig <= '0';
1125 tx_start_2_sig <= tx_start_sig;
1126 tx_start_3_sig <= '0';
1127 tx_data_0_sig <= (others => '0');
1128 tx_data_1_sig <= (others => '0');
1129 tx_data_2_sig <= tx_data_sig;
1130 tx_data_3_sig <= (others => '0');
1131 when "011" => -- crate 3
1132 rx_en_sig <= rx_en_3_sig;
1133 tx_en_sig <= tx_en_3_sig;
1134 rx_valid_sig <= rx_valid_3_sig;
1135 rec_data_sig <= rx_data_3_sig;
1136 tx_busy_sig <= tx_busy_3_sig;
1137 rx_busy_sig <= rx_busy_3_sig;
1138 tx_start_0_sig <= '0';
1139 tx_start_1_sig <= '0';
1140 tx_start_2_sig <= '0';
1141 tx_start_3_sig <= tx_start_sig;
1142 tx_data_0_sig <= (others => '0');
1143 tx_data_1_sig <= (others => '0');
1144 tx_data_2_sig <= (others => '0');
1145 tx_data_3_sig <= tx_data_sig;
1146 when others => -- no crate specified
1147 rx_en_sig <= '0';
1148 tx_en_sig <= '0';
1149 rx_valid_sig <= '0';
1150 rec_data_sig <= (others => '0');
1151 tx_busy_sig <= '0';
1152 rx_busy_sig <= '0';
1153 tx_start_0_sig <= '0';
1154 tx_start_1_sig <= '0';
1155 tx_start_2_sig <= '0';
1156 tx_start_3_sig <= '0';
1157 tx_data_0_sig <= (others => '0');
1158 tx_data_1_sig <= (others => '0');
1159 tx_data_2_sig <= (others => '0');
1160 tx_data_3_sig <= (others => '0');
1161 end case;
1162 end process;
1163
1164 -- Process to select the CRC input source (FSM or interpreter)
1165 sel_crc_cource_process : process (sel_crc_input_source_sig,
1166 reset_crc_from_interpreter_sig, reset_crc_from_FSM_sig,
1167 enable_crc_from_interpreter_sig, enable_crc_from_FSM_sig,
1168 rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0), crc_data_from_FSM_sig)
1169 begin
1170 case sel_crc_input_source_sig is
1171 when '0' => -- FSM
1172 reset_crc_sig <= reset_crc_from_FSM_sig;
1173 enable_crc_sig <= enable_crc_from_FSM_sig;
1174 crc_data_sig <= crc_data_from_FSM_sig;
1175 when '1' => -- interpreter
1176 reset_crc_sig <= reset_crc_from_interpreter_sig;
1177 enable_crc_sig <= enable_crc_from_interpreter_sig;
1178 crc_data_sig <= rec_block_sig((FTU_RS485_BLOCK_WIDTH - 9) downto 0);
1179 when others => -- signal undefined
1180 reset_crc_sig <= reset_crc_from_FSM_sig;
1181 enable_crc_sig <= enable_crc_from_FSM_sig;
1182 crc_data_sig <= crc_data_from_FSM_sig;
1183 end case;
1184 end process;
1185
1186 rx_en <= rx_en_sig;
1187 tx_en <= tx_en_sig;
1188
1189 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
1190 start_int_sig <= rec_valid_sig and (not rx_busy_sig); -- avoid continuing to early after FTU answer
1191
1192end Behavioral;
1193
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