source: firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd@ 14259

Last change on this file since 14259 was 10418, checked in by weitzel, 14 years ago
New FTM firmare: dna, fad_broadcast, FTU error messages, rates readout
File size: 8.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 02/04/2011
6-- Design Name:
7-- Module Name: FTM_ftu_rs485_interpreter - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: data interpreter of FTM RS485 module for FTU communication
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftm_definitions;
27USE ftm_definitions.ftm_array_types.all;
28USE ftm_definitions.ftm_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTM_ftu_rs485_interpreter is
36 port(
37 clk : IN std_logic;
38 data_block : IN std_logic_vector(FTU_RS485_BLOCK_WIDTH - 1 downto 0); -- from receiver
39 block_valid : IN std_logic; -- from receiver
40 crc : IN std_logic_vector(7 downto 0); -- from ucrc_par
41 FTU_brd_add : IN std_logic_vector(5 downto 0); -- from FTM_ftu_control FSM
42 FTU_command : IN std_logic_vector(7 downto 0); -- from FTM_ftu_control FSM
43 reset_crc : OUT std_logic := '0';
44 enable_crc : OUT std_logic := '0';
45 FTU_answer_ok : OUT std_logic := '0';
46 FTU_dac_array : OUT FTU_dac_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
47 FTU_enable_array : OUT FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
48 FTU_rate_array : OUT FTU_rate_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
49 FTU_overflow : OUT std_logic_vector(7 downto 0) := (others => '0');
50 FTU_prescaling : OUT std_logic_vector(7 downto 0) := (others => '0');
51 FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0) := (others => '0');
52 FTU_dna : OUT std_logic_vector(63 downto 0) := (others => '0')
53 );
54end FTM_ftu_rs485_interpreter;
55
56architecture Behavioral of FTM_ftu_rs485_interpreter is
57
58 signal block_valid_sr : std_logic_vector(3 downto 0) := (others => '0');
59
60 type FTM_ftu_rs485_interpreter_StateType is (INIT, WAIT_FOR_DATA, WAIT_CRC, CHECK_CRC, CHECK_HEADER, CHECK_CMD, DECODE);
61 signal FTM_ftu_rs485_interpreter_State : FTM_ftu_rs485_interpreter_StateType;
62
63begin
64
65 FTM_ftu_rs485_interpreter_FSM: process (clk)
66 begin
67 if Rising_edge(clk) then
68 case FTM_ftu_rs485_interpreter_State is
69
70 when INIT => -- reset CRC register
71 reset_crc <= '1';
72 FTU_answer_ok <= '0';
73 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
74
75 when WAIT_FOR_DATA => -- default state, waiting for valid 28-byte block
76 block_valid_sr <= block_valid_sr(2 downto 0) & block_valid;
77 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal
78 enable_crc <= '1';
79 FTM_ftu_rs485_interpreter_State <= WAIT_CRC;
80 else
81 enable_crc <= '0';
82 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
83 end if;
84 reset_crc <= '0';
85 FTU_answer_ok <= '0';
86
87 when WAIT_CRC => -- wait one cycle for CRC calculation
88 enable_crc <= '0';
89 FTU_answer_ok <= '0';
90 FTM_ftu_rs485_interpreter_State <= CHECK_CRC;
91
92 when CHECK_CRC => -- check whether CRC matches
93 reset_crc <= '1';
94 FTU_answer_ok <= '0';
95 if ( crc = data_block((FTU_RS485_BLOCK_WIDTH - 1) downto (FTU_RS485_BLOCK_WIDTH - 8)) ) then
96 FTM_ftu_rs485_interpreter_State <= CHECK_HEADER;
97 else
98 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
99 end if;
100
101 when CHECK_HEADER => -- check start delimiter and addresses
102 if (data_block(7 downto 0) = FTU_RS485_START_DELIM) and
103 (data_block(15 downto 8) = FTM_ADDRESS) and
104 (data_block(23 downto 16) = ("00" & FTU_brd_add)) then
105 FTM_ftu_rs485_interpreter_State <= CHECK_CMD;
106 else
107 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
108 end if;
109 reset_crc <= '0';
110 FTU_answer_ok <= '0';
111
112 when CHECK_CMD => -- check command
113 reset_crc <= '0';
114 if (data_block(39 downto 32) = FTU_command) then
115 FTM_ftu_rs485_interpreter_State <= DECODE;
116 FTU_answer_ok <= '1';
117 else
118 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
119 FTU_answer_ok <= '0';
120 end if;
121
122 when DECODE => -- decode instruction
123 FTU_answer_ok <= '0';
124 if(data_block(39 downto 32) = "00000000") then -- set DACs
125 FTU_dac_array <= (data_block( 55 downto 40),
126 data_block( 71 downto 56),
127 data_block( 87 downto 72),
128 data_block(103 downto 88),
129 data_block(119 downto 104)
130 );
131 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
132 elsif (data_block(39 downto 32) = "00000001") then -- read DACs
133 FTU_dac_array <= (data_block( 55 downto 40),
134 data_block( 71 downto 56),
135 data_block( 87 downto 72),
136 data_block(103 downto 88),
137 data_block(119 downto 104)
138 );
139 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
140 elsif (data_block(39 downto 32) = "00000010") then -- read rates
141 FTU_rate_array <= (data_block( 71 downto 40),
142 data_block(103 downto 72),
143 data_block(135 downto 104),
144 data_block(167 downto 136),
145 data_block(199 downto 168)
146 );
147 FTU_overflow <= data_block(207 downto 200);
148 FTU_crc_error_cnt <= data_block(215 downto 208);
149 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
150 elsif (data_block(39 downto 32) = "00000011") then -- set enables
151 FTU_enable_array <= (data_block( 55 downto 40),
152 data_block( 71 downto 56),
153 data_block( 87 downto 72),
154 data_block(103 downto 88)
155 );
156 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
157 elsif (data_block(39 downto 32) = "00000100") then -- read enables
158 FTU_enable_array <= (data_block( 55 downto 40),
159 data_block( 71 downto 56),
160 data_block( 87 downto 72),
161 data_block(103 downto 88)
162 );
163 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
164 elsif (data_block(39 downto 32) = "00000110") then -- set counter mode
165 FTU_prescaling <= data_block(47 downto 40);
166 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
167 elsif (data_block(39 downto 32) = "00000111") then -- read counter mode
168 FTU_prescaling <= data_block(47 downto 40);
169 FTU_overflow <= data_block(55 downto 48);
170 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
171 elsif (data_block(39 downto 32) = "00000101") then -- ping pong
172 FTU_dna <= data_block(103 downto 40);
173 FTU_crc_error_cnt <= data_block(215 downto 208);
174 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
175 else
176 FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
177 end if;
178
179 end case;
180 end if;
181 end process FTM_ftu_rs485_interpreter_FSM;
182
183end Behavioral;
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