source: firmware/FTM/ftu_control/ucrc_par.vhd@ 19285

Last change on this file since 19285 was 10175, checked in by weitzel, 15 years ago
first version of FTM_ftu_control, not yet tested
File size: 6.8 KB
Line 
1----------------------------------------------------------------------
2---- ----
3---- Ultimate CRC. ----
4---- ----
5---- This file is part of the ultimate CRC projectt ----
6---- http://www.opencores.org/cores/ultimate_crc/ ----
7---- ----
8---- Description ----
9---- CRC generator/checker, parallel implementation. ----
10---- ----
11---- ----
12---- To Do: ----
13---- - ----
14---- ----
15---- Author(s): ----
16---- - Geir Drange, gedra@opencores.org ----
17---- ----
18----------------------------------------------------------------------
19---- ----
20---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
21---- ----
22---- This source file may be used and distributed without ----
23---- restriction provided that this copyright statement is not ----
24---- removed from the file and that any derivative work contains ----
25---- the original copyright notice and the associated disclaimer. ----
26---- ----
27---- This source file is free software; you can redistribute it ----
28---- and/or modify it under the terms of the GNU General ----
29---- Public License as published by the Free Software Foundation; ----
30---- either version 2.0 of the License, or (at your option) any ----
31---- later version. ----
32---- ----
33---- This source is distributed in the hope that it will be ----
34---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
35---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
36---- PURPOSE. See the GNU General Public License for more details.----
37---- ----
38---- You should have received a copy of the GNU General ----
39---- Public License along with this source; if not, download it ----
40---- from http://www.gnu.org/licenses/gpl.txt ----
41---- ----
42----------------------------------------------------------------------
43--
44-- CVS Revision History
45--
46-- $Log: not supported by cvs2svn $
47-- Revision 1.1 2005/05/09 15:58:38 gedra
48-- Parallel implementation
49--
50--
51--
52
53library ieee;
54use ieee.std_logic_1164.all;
55
56entity ucrc_par is
57 generic (
58 POLYNOMIAL : std_logic_vector;
59 INIT_VALUE : std_logic_vector;
60 DATA_WIDTH : integer range 2 to 256;
61 SYNC_RESET : integer range 0 to 1); -- use sync./async reset
62 port (
63 clk_i : in std_logic; -- clock
64 rst_i : in std_logic; -- init CRC
65 clken_i : in std_logic; -- clock enable
66 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input
67 match_o : out std_logic; -- CRC match flag
68 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output
69end ucrc_par;
70
71architecture rtl of ucrc_par is
72
73 constant msb : integer := POLYNOMIAL'length - 1;
74 constant init_msb : integer := INIT_VALUE'length - 1;
75 constant p : std_logic_vector(msb downto 0) := POLYNOMIAL;
76 constant dw : integer := DATA_WIDTH;
77 constant pw : integer := POLYNOMIAL'length;
78 type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0);
79 type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1);
80 signal crca : fb_array;
81 signal da, ma : dmsb_array;
82 signal crc, zero : std_logic_vector(msb downto 0);
83 signal arst, srst : std_logic;
84
85begin
86
87-- Parameter checking: Invalid generics will abort simulation/synthesis
88 PCHK1 : if msb /= init_msb generate
89 process
90 begin
91 report "POLYNOMIAL and INIT_VALUE vectors must be equal length!"
92 severity failure;
93 wait;
94 end process;
95 end generate PCHK1;
96
97 PCHK2 : if (msb < 3) or (msb > 31) generate
98 process
99 begin
100 report "POLYNOMIAL must be of order 4 to 32!"
101 severity failure;
102 wait;
103 end process;
104 end generate PCHK2;
105
106 PCHK3 : if p(0) /= '1' generate -- LSB must be 1
107 process
108 begin
109 report "POLYNOMIAL must have lsb set to 1!"
110 severity failure;
111 wait;
112 end process;
113 end generate PCHK3;
114
115-- Generate vector of each data bit
116 CA : for i in 1 to dw generate -- data bits
117 DAT : for j in 1 to msb generate
118 da(i)(j) <= data_i(i - 1);
119 end generate DAT;
120 end generate CA;
121
122-- Generate vector of each CRC MSB
123 MS0 : for i in 1 to msb generate
124 ma(1)(i) <= crc(msb);
125 end generate MS0;
126 MSP : for i in 2 to dw generate
127 MSU : for j in 1 to msb generate
128 ma(i)(j) <= crca(i - 1)(msb);
129 end generate MSU;
130 end generate MSP;
131
132-- Generate feedback matrix
133 crca(1)(0) <= da(1)(1) xor crc(msb);
134 crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1));
135 FB : for i in 2 to dw generate
136 crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb);
137 crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor
138 ((da(i) xor ma(i)) and p(msb downto 1));
139 end generate FB;
140
141-- Reset signal
142 SR : if SYNC_RESET = 1 generate
143 srst <= rst_i;
144 arst <= '0';
145 end generate SR;
146 AR : if SYNC_RESET = 0 generate
147 srst <= '0';
148 arst <= rst_i;
149 end generate AR;
150
151-- CRC process
152 crc_o <= crc;
153 zero <= (others => '0');
154
155 CRCP : process (clk_i, arst)
156 begin
157 if arst = '1' then -- async. reset
158 crc <= INIT_VALUE;
159 match_o <= '0';
160 elsif rising_edge(clk_i) then
161 if srst = '1' then -- sync. reset
162 crc <= INIT_VALUE;
163 match_o <= '0';
164 elsif clken_i = '1' then
165 crc <= crca(dw);
166 if crca(dw) = zero then
167 match_o <= '1';
168 else
169 match_o <= '0';
170 end if;
171 end if;
172 end if;
173 end process;
174
175end rtl;
176
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