source: firmware/FTM/test_firmware/FTM_test1/FTM_test1.vhd@ 14259

Last change on this file since 14259 was 10046, checked in by vogler, 14 years ago
Test firmware for FTM hardware testing
  • Property svn:executable set to *
File size: 11.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 12 August 2010
6-- Design Name:
7-- Module Name: FTU_test1 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board: blinking with the on-board LED's
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26---- Uncomment the following library declaration if instantiating
27---- any Xilinx primitives in this code.
28--library UNISIM;
29--use UNISIM.VComponents.all;
30
31entity FTM_test1 is
32 port(
33
34
35-- Clock
36 clk : IN STD_LOGIC; -- external clock from
37 -- oscillator U47
38
39-- connection to the WIZnet W5300 ethernet controller
40-- on IO-Bank 1
41-------------------------------------------------------------------------------
42 -- W5300 data bus
43-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
44
45
46 -- W5300 address bus
47-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
48 -- the W5300 is operated in the
49 -- 16-bit mode
50
51 -- W5300 controll signals
52 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
53 -- W_CS is also routed to testpoint JP7
54-- W_CS : out STD_LOGIC; -- W5300 chip select
55-- W_INT : IN STD_LOGIC; -- interrupt
56-- W_RD : out STD_LOGIC; -- read
57-- W_WR : out STD_LOGIC; -- write
58-- W_RES : out STD_LOGIC; -- reset W5300 chip
59
60 -- W5300 buffer ready indicator
61-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
62
63 -- testpoints (T18) associated with the W5300 on IO-bank 1
64-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
65
66
67
68-- SPI Interface
69-- connection to the EEPROM U36 (AL25L016M) and
70-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
71-- on IO-Bank 1
72-------------------------------------------------------------------------------
73-- S_CLK : out STD_LOGIC; -- SPI clock
74
75 -- EEPROM
76-- MOSI : out STD_LOGIC; -- master out slave in
77-- MISO : in STD_LOGIC; -- master in slave out
78-- EE_CS : out STD_LOGIC; -- EEPROM chip select
79
80 -- temperature sensors U45, U46, U48 and U49
81-- SIO : inout STD_LOGIC; -- serial IO
82-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
83
84
85
86-- Trigger primitives inputs
87-- on IO-Bank 2
88-------------------------------------------------------------------------------
89-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
90-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
91-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
92-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
93
94
95
96-- NIM inputs
97------------------------------------------------------------------------------
98 -- on IO-Bank 3
99-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
100-- Veto : in STD_LOGIC; -- trigger veto input
101-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
102
103 -- on IO-Bank 0
104-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
105
106
107
108-- LEDs on IO-Banks 0 and 3
109-------------------------------------------------------------------------------
110 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
111 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
112 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
113
114
115
116-- Clock conditioner LMK03000
117-- on IO-Bank 3
118-------------------------------------------------------------------------------
119-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
120-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
121-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
122
123-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
124-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
125
126
127
128
129-- various RS-485 Interfaces
130-- on IO-Bank 3
131-------------------------------------------------------------------------------
132 -- Bus 1: FTU slow control
133-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
134-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
135
136-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0
137-- Bus1_TxD_0 : out STD_LOGIC;
138
139-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
140-- Bus1_TxD_1 : out STD_LOGIC;
141
142-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
143-- Bus1_TxD_2 : out STD_LOGIC;
144
145-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
146-- Bus1_TxD_3 : out STD_LOGIC;
147
148
149 -- Bus 2: Trigger-ID to FAD boards
150-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
151-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
152
153-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
154-- Bus2_TxD_0 : out STD_LOGIC;
155
156-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
157-- Bus2_TxD_1 : out STD_LOGIC;
158
159-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
160-- Bus2_TxD_2 : out STD_LOGIC;
161
162-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
163-- Bus2_TxD_3 : out STD_LOGIC;
164
165
166-- auxiliary access
167-- Aux_Rx_D : in STD_LOGIC; --
168-- Aux_Tx_D : out STD_LOGIC; --
169-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
170-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
171
172
173-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
174-- TrID_Rx_D : in STD_LOGIC; --
175-- TrID_Tx_D : out STD_LOGIC; --
176
177
178-- Crate-Resets
179-- on IO-Bank 3
180-------------------------------------------------------------------------------
181-- Crate_Res0 : out STD_LOGIC; --
182-- Crate_Res1 : out STD_LOGIC; --
183-- Crate_Res2 : out STD_LOGIC; --
184-- Crate_Res3 : out STD_LOGIC; --
185
186
187-- Busy signals from the FAD boards
188-- on IO-Bank 3
189-------------------------------------------------------------------------------
190-- Busy0 : in STD_LOGIC; --
191-- Busy1 : in STD_LOGIC; --
192-- Busy2 : in STD_LOGIC; --
193-- Busy3 : in STD_LOGIC; --
194
195
196
197-- NIM outputs
198-- on IO-Bank 0
199-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
200-------------------------------------------------------------------------------
201-- calibration
202-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
203-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
204-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
205-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
206
207-- auxiliarry / spare NIM outputs
208-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
209-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
210-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
211-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
212
213
214
215-- fast control signal outputs
216-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
217-- conversion stage
218-------------------------------------------------------------------------------
219-- RES_p : out STD_LOGIC; -- RES+ Reset
220-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
221
222-- TRG_p : out STD_LOGIC; -- TRG+ Trigger
223-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
224
225-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
226-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
227-- TIM_Sel : out STD_LOGIC; -- Time Marker selector on
228 -- IO-Bank 2
229
230-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
231
232
233
234-- LVDS calibration outputs
235-- on IO-Bank 0
236-------------------------------------------------------------------------------
237-- to connector J13
238-- Cal_0_p : out STD_LOGIC;
239-- Cal_0_n : out STD_LOGIC;
240-- Cal_1_p : out STD_LOGIC;
241-- Cal_1_n : out STD_LOGIC;
242-- Cal_2_p : out STD_LOGIC;
243-- Cal_2_n : out STD_LOGIC;
244-- Cal_3_p : out STD_LOGIC;
245-- Cal_3_n : out STD_LOGIC;
246
247-- to connector J12
248-- Cal_4_p : out STD_LOGIC;
249-- Cal_4_n : out STD_LOGIC;
250-- Cal_5_p : out STD_LOGIC;
251-- Cal_5_n : out STD_LOGIC;
252-- Cal_6_p : out STD_LOGIC;
253-- Cal_6_n : out STD_LOGIC;
254-- Cal_7_p : out STD_LOGIC;
255-- Cal_7_n : out STD_LOGIC;
256
257
258-- Testpoints
259-------------------------------------------------------------------------------
260 TP : inout STD_LOGIC_VECTOR(32 downto 0)
261-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
262
263-- Board ID - inputs
264-- local board-ID "solder programmable"
265-- all on 'input only' pins
266-------------------------------------------------------------------------------
267-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
268 );
269end FTM_test1;
270
271
272architecture Behavioral of FTM_test1 is
273
274 component FTM_test1_dcm
275 port ( CLKIN_IN : in std_logic;
276 CLKFX_OUT : out std_logic;
277 CLKIN_IBUFG_OUT : out std_logic);
278 end component;
279
280 component Clock_Divider
281 port(
282 clock : IN STD_LOGIC;
283 enable_out : OUT STD_LOGIC
284 );
285 end component;
286
287 signal clk_250M_sig : STD_LOGIC;
288 signal enable_sig : STD_LOGIC;
289
290
291
292
293begin
294
295 Inst_FTU_test1_dcm : FTM_test1_dcm
296 port map(
297 CLKIN_IN => clk,
298 CLKFX_OUT => clk_250M_sig,
299 CLKIN_IBUFG_OUT => open
300 );
301
302 Inst_Clock_Divider : Clock_Divider
303 port map (
304 clock => clk_250M_sig,
305 enable_out => enable_sig
306 );
307
308 LED_red(0) <= enable_sig;
309 LED_red(1) <= enable_sig;
310 LED_red(2) <= enable_sig;
311 LED_red(3) <= enable_sig;
312
313 LED_ye(0) <= enable_sig;
314 LED_ye(1) <= enable_sig;
315
316 LED_gn(0) <= enable_sig;
317 LED_gn(1) <= enable_sig;
318
319 TP(0) <= clk_250M_sig;
320
321end Behavioral;
322
323
324
325
326library IEEE;
327use IEEE.STD_LOGIC_1164.ALL;
328use IEEE.STD_LOGIC_ARITH.ALL;
329use IEEE.STD_LOGIC_UNSIGNED.ALL;
330
331entity Clock_Divider is
332 port(
333 clock : in std_logic;
334 enable_out: out std_logic
335 );
336end entity Clock_Divider;
337
338architecture RTL of Clock_Divider is
339
340 --constant max_count : integer := 5000000/1000000; -- for simulation
341 constant max_count : integer := 250000000/1; -- for implementation
342 constant final_count : integer := 100;
343
344begin
345
346 process(clock)
347 variable count : integer range 0 to max_count;
348 variable count2 : integer range 0 to final_count;
349 begin
350 if rising_edge(clock) then
351 --enable_out <= '0';
352 if count2 = final_count then
353 enable_out <= '0';
354 else
355 if count < max_count/2 then
356 enable_out <= '0';
357 count := count + 1;
358 elsif count < max_count then
359 enable_out <= '1';
360 count := count + 1;
361 else
362 count := 0;
363 enable_out <= '0';
364 count2 := count2 + 1;
365 end if;
366 end if;
367 end if;
368 end process;
369
370end architecture RTL;
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