source: firmware/FTM/test_firmware/FTM_test2/FTM_test2.vhd@ 13501

Last change on this file since 13501 was 10046, checked in by vogler, 15 years ago
Test firmware for FTM hardware testing
  • Property svn:executable set to *
File size: 15.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 13 October 2010
6-- Design Name:
7-- Module Name: FTU_test2 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board:
12-- NIM and LVDS output stages
13-- fast signal distribution (partially)
14-- crate resets
15--
16--
17--
18-- Dependencies:
19--
20-- Revision:
21-- Revision 0.01 - File Created
22-- Additional Comments:
23--
24----------------------------------------------------------------------------------
25
26library IEEE;
27use IEEE.STD_LOGIC_1164.ALL;
28use IEEE.STD_LOGIC_ARITH.ALL;
29use IEEE.STD_LOGIC_UNSIGNED.ALL;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTM_test2 is
37 port(
38
39
40-- Clock
41 clk : IN STD_LOGIC; -- external clock from
42 -- oscillator U47
43
44-- connection to the WIZnet W5300 ethernet controller
45-- on IO-Bank 1
46-------------------------------------------------------------------------------
47 -- W5300 data bus
48-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
49
50
51 -- W5300 address bus
52-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
53 -- the W5300 is operated in the
54 -- 16-bit mode
55
56 -- W5300 controll signals
57 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
58 -- W_CS is also routed to testpoint JP7
59-- W_CS : out STD_LOGIC; -- W5300 chip select
60-- W_INT : IN STD_LOGIC; -- interrupt
61-- W_RD : out STD_LOGIC; -- read
62-- W_WR : out STD_LOGIC; -- write
63-- W_RES : out STD_LOGIC; -- reset W5300 chip
64
65 -- W5300 buffer ready indicator
66-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
67
68 -- testpoints (T18) associated with the W5300 on IO-bank 1
69-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
70
71
72
73-- SPI Interface
74-- connection to the EEPROM U36 (AL25L016M) and
75-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
76-- on IO-Bank 1
77-------------------------------------------------------------------------------
78-- S_CLK : out STD_LOGIC; -- SPI clock
79
80 -- EEPROM
81-- MOSI : out STD_LOGIC; -- master out slave in
82-- MISO : in STD_LOGIC; -- master in slave out
83-- EE_CS : out STD_LOGIC; -- EEPROM chip select
84
85 -- temperature sensors U45, U46, U48 and U49
86-- SIO : inout STD_LOGIC; -- serial IO
87-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
88
89
90
91-- Trigger primitives inputs
92-- on IO-Bank 2
93-------------------------------------------------------------------------------
94-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
95-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
96-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
97-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
98
99
100
101-- NIM inputs
102------------------------------------------------------------------------------
103 -- on IO-Bank 3
104-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
105-- Veto : in STD_LOGIC; -- trigger veto input
106-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
107
108 -- on IO-Bank 0
109-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
110
111
112
113-- LEDs on IO-Banks 0 and 3
114-------------------------------------------------------------------------------
115-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
116-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
117-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
118
119
120
121-- Clock conditioner LMK03000
122-- on IO-Bank 3
123-------------------------------------------------------------------------------
124-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
125-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
126-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
127
128-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
129-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
130
131
132
133
134-- various RS-485 Interfaces
135-- on IO-Bank 3
136-------------------------------------------------------------------------------
137 -- Bus 1: FTU slow control
138-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
139-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
140
141-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0
142-- Bus1_TxD_0 : out STD_LOGIC;
143
144-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
145-- Bus1_TxD_1 : out STD_LOGIC;
146
147-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
148-- Bus1_TxD_2 : out STD_LOGIC;
149
150-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
151-- Bus1_TxD_3 : out STD_LOGIC;
152
153
154 -- Bus 2: Trigger-ID to FAD boards
155-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
156-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
157
158-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
159-- Bus2_TxD_0 : out STD_LOGIC;
160
161-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
162-- Bus2_TxD_1 : out STD_LOGIC;
163
164-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
165-- Bus2_TxD_2 : out STD_LOGIC;
166
167-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
168-- Bus2_TxD_3 : out STD_LOGIC;
169
170
171-- auxiliary access
172-- Aux_Rx_D : in STD_LOGIC; --
173-- Aux_Tx_D : out STD_LOGIC; --
174-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
175-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
176
177
178-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
179-- TrID_Rx_D : in STD_LOGIC; --
180-- TrID_Tx_D : out STD_LOGIC; --
181
182
183-- Crate-Resets
184-- on IO-Bank 3
185-------------------------------------------------------------------------------
186 Crate_Res0 : out STD_LOGIC; --
187 Crate_Res1 : out STD_LOGIC; --
188 Crate_Res2 : out STD_LOGIC; --
189 Crate_Res3 : out STD_LOGIC; --
190
191
192-- Busy signals from the FAD boards
193-- on IO-Bank 3
194-------------------------------------------------------------------------------
195-- Busy0 : in STD_LOGIC; --
196-- Busy1 : in STD_LOGIC; --
197-- Busy2 : in STD_LOGIC; --
198-- Busy3 : in STD_LOGIC; --
199
200
201
202-- NIM outputs
203-- on IO-Bank 0
204-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
205-------------------------------------------------------------------------------
206-- calibration
207 Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
208 Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
209 Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
210 Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
211
212-- auxiliarry / spare NIM outputs
213 NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
214 NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
215 NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
216 NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
217
218
219
220-- fast control signal outputs
221-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
222-- conversion stage
223-------------------------------------------------------------------------------
224 RES_p : out STD_LOGIC; -- RES+ Reset
225 RES_n : out STD_LOGIC; -- RES- IO-Bank 0
226
227 TRG_p : out STD_LOGIC; -- TRG+ Trigger
228 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
229
230 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
231 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
232 TIM_Sel : out STD_LOGIC; -- Time Marker selector on
233 -- IO-Bank 2
234
235-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
236
237
238
239-- LVDS calibration outputs
240-- on IO-Bank 0
241-------------------------------------------------------------------------------
242-- to connector J13
243 Cal_0_p : out STD_LOGIC;
244 Cal_0_n : out STD_LOGIC;
245 Cal_1_p : out STD_LOGIC;
246 Cal_1_n : out STD_LOGIC;
247 Cal_2_p : out STD_LOGIC;
248 Cal_2_n : out STD_LOGIC;
249 Cal_3_p : out STD_LOGIC;
250 Cal_3_n : out STD_LOGIC;
251
252-- to connector J12
253 Cal_4_p : out STD_LOGIC;
254 Cal_4_n : out STD_LOGIC;
255 Cal_5_p : out STD_LOGIC;
256 Cal_5_n : out STD_LOGIC;
257 Cal_6_p : out STD_LOGIC;
258 Cal_6_n : out STD_LOGIC;
259 Cal_7_p : out STD_LOGIC;
260 Cal_7_n : out STD_LOGIC
261
262
263-- Testpoints
264-------------------------------------------------------------------------------
265-- TP : inout STD_LOGIC_VECTOR(32 downto 0)
266-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
267
268-- Board ID - inputs
269-- local board-ID "solder programmable"
270-- all on 'input only' pins
271-------------------------------------------------------------------------------
272-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
273 );
274end FTM_test2;
275
276
277
278
279
280architecture Behavioral of FTM_test2 is
281
282 component FTM_test1_dcm
283 port ( CLKIN_IN : in std_logic;
284 CLKFX_OUT : out std_logic;
285 CLKIN_IBUFG_OUT : out std_logic);
286 end component;
287
288 component Clock_Divider
289 port(
290 clock : IN STD_LOGIC;
291 enable_out : OUT STD_LOGIC
292 );
293 end component;
294
295 signal clk_200M_sig : STD_LOGIC;
296 signal enable_sig : STD_LOGIC;
297
298
299begin
300
301
302 OBUFDS_inst_TRG : OBUFDS
303 generic map (
304 IOSTANDARD => "DEFAULT")
305 port map (
306 O => TRG_p, -- Diff_p output (connect directly to top-level port)
307 OB => TRG_n, -- Diff_n output (connect directly to top-level port)
308 I => enable_sig -- Buffer input
309 );
310
311
312
313 OBUFDS_inst_RES : OBUFDS
314 generic map (
315 IOSTANDARD => "DEFAULT")
316 port map (
317 O => RES_p, -- Diff_p output (connect directly to top-level port)
318 OB => RES_n, -- Diff_n output (connect directly to top-level port)
319 I => enable_sig -- Buffer input
320 );
321
322
323
324 OBUFDS_inst_TIM : OBUFDS
325 generic map (
326 IOSTANDARD => "DEFAULT")
327 port map (
328 O => TIM_Run_p, -- Diff_p output (connect directly to top-level port)
329 OB => TIM_Run_n, -- Diff_n output (connect directly to top-level port)
330 I => enable_sig -- Buffer input
331 );
332
333 TIM_Sel <= '0';
334
335 Crate_Res0 <= enable_sig;
336 Crate_Res1 <= enable_sig;
337 Crate_Res2 <= enable_sig;
338 Crate_Res3 <= enable_sig;
339
340
341
342
343
344 OBUFDS_inst_Cal_NIM1 : OBUFDS
345 generic map (
346 IOSTANDARD => "DEFAULT")
347 port map (
348 O => Cal_NIM1_p, -- Diff_p output (connect directly to top-level port)
349 OB => Cal_NIM1_n, -- Diff_n output (connect directly to top-level port)
350 I => enable_sig -- Buffer input
351 );
352
353
354 OBUFDS_inst_Cal_NIM2 : OBUFDS
355 generic map (
356 IOSTANDARD => "DEFAULT")
357 port map (
358 O => Cal_NIM2_p, -- Diff_p output (connect directly to top-level port)
359 OB => Cal_NIM2_n, -- Diff_n output (connect directly to top-level port)
360 I => not enable_sig -- Buffer input
361 );
362
363
364
365
366 OBUFDS_inst_NIM_Out0 : OBUFDS
367 generic map (
368 IOSTANDARD => "DEFAULT")
369 port map (
370 O => NIM_Out0_p, -- Diff_p output (connect directly to top-level port)
371 OB => NIM_Out0_n, -- Diff_n output (connect directly to top-level port)
372 I => enable_sig -- Buffer input
373 );
374
375
376 OBUFDS_inst_NIM_Out1 : OBUFDS
377 generic map (
378 IOSTANDARD => "DEFAULT")
379 port map ( O => NIM_Out1_p, -- Diff_p output (connect directly to top-level port)
380 OB => NIM_Out1_n, -- Diff_n output (connect directly to top-level port)
381 I => enable_sig -- Buffer input
382 );
383
384
385
386
387
388 OBUFDS_inst_Cal_0 : OBUFDS
389 generic map (
390 IOSTANDARD => "DEFAULT")
391 port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port)
392 OB => Cal_0_n , -- Diff_n output (connect directly to top-level port)
393 I => enable_sig -- Buffer input
394 );
395
396 OBUFDS_inst_Cal_1 : OBUFDS
397 generic map (
398 IOSTANDARD => "DEFAULT")
399 port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port)
400 OB => Cal_1_n , -- Diff_n output (connect directly to top-level port)
401 I => enable_sig -- Buffer input
402 );
403
404 OBUFDS_inst_Cal_2 : OBUFDS
405 generic map (
406 IOSTANDARD => "DEFAULT")
407 port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port)
408 OB => Cal_2_n , -- Diff_n output (connect directly to top-level port)
409 I => enable_sig -- Buffer input
410 );
411
412 OBUFDS_inst_Cal_3 : OBUFDS
413 generic map (
414 IOSTANDARD => "DEFAULT")
415 port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port)
416 OB => Cal_3_n , -- Diff_n output (connect directly to top-level port)
417 I => enable_sig -- Buffer input
418 );
419
420 OBUFDS_inst_Cal_4 : OBUFDS
421 generic map (
422 IOSTANDARD => "DEFAULT")
423 port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port)
424 OB => Cal_4_n , -- Diff_n output (connect directly to top-level port)
425 I => enable_sig -- Buffer input
426 );
427
428 OBUFDS_inst_Cal_5 : OBUFDS
429 generic map (
430 IOSTANDARD => "DEFAULT")
431 port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port)
432 OB => Cal_5_n , -- Diff_n output (connect directly to top-level port)
433 I => enable_sig -- Buffer input
434 );
435
436 OBUFDS_inst_Cal_6 : OBUFDS
437 generic map (
438 IOSTANDARD => "DEFAULT")
439 port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port)
440 OB => Cal_6_n , -- Diff_n output (connect directly to top-level port)
441 I => enable_sig -- Buffer input
442 );
443
444 OBUFDS_inst_Cal_7 : OBUFDS
445 generic map (
446 IOSTANDARD => "DEFAULT")
447 port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port)
448 OB => Cal_7_n , -- Diff_n output (connect directly to top-level port)
449 I => enable_sig -- Buffer input
450 );
451
452
453
454
455
456
457
458 Inst_FTU_test2_dcm : FTM_test1_dcm
459 port map(
460 CLKIN_IN => clk,
461 CLKFX_OUT => clk_200M_sig,
462 CLKIN_IBUFG_OUT => open
463 );
464
465
466 Inst_Clock_Divider : Clock_Divider
467 port map (
468 clock => clk_200M_sig,
469 enable_out => enable_sig
470 );
471
472
473end Behavioral;
474
475
476
477
478library IEEE;
479use IEEE.STD_LOGIC_1164.ALL;
480use IEEE.STD_LOGIC_ARITH.ALL;
481use IEEE.STD_LOGIC_UNSIGNED.ALL;
482
483entity Clock_Divider is
484 port(
485 clock : in std_logic;
486 enable_out: out std_logic
487 );
488end entity Clock_Divider;
489
490architecture RTL of Clock_Divider is
491
492 --constant max_count : integer := 5000000/1000000; -- for simulation
493 constant max_count : integer := 2500/1; -- for implementation
494-- constant final_count : integer := 100;
495
496begin
497
498 process(clock)
499 variable count : integer range 0 to max_count;
500-- variable count2 : integer range 0 to final_count;
501 begin
502 if rising_edge(clock) then
503 --enable_out <= '0';
504-- if count2 = final_count then
505-- enable_out <= '0';
506-- else
507 if count < max_count/2 then
508 enable_out <= '0';
509 count := count + 1;
510 elsif count < max_count then
511 enable_out <= '1';
512 count := count + 1;
513 else
514 count := 0;
515 enable_out <= '0';
516-- count2 := count2 + 1;
517 end if;
518-- end if;
519 end if;
520 end process;
521
522end architecture RTL;
523
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